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A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

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Mario Garrido, Member, IEEE , Miguel ngel Snchez, Mara Luisa Lpez-Vallejo, and Jess Grajal

based fast Fourier transform (FFT). The proposed architecture follows a

conflict-free strategy that only requires a total memory of size N and a

few additional multiplexers. The control is also simple, as it is generated

directly from the bits of a counter. Apart from the low complexity,

the FFT has been implemented on a Virtex-5 field programmable gate

array (FPGA) using DSP slices. The goal has been to reduce the use of

distributed logic, which is scarce in the target FPGA. With this purpose,

most of the hardware has been implemented in DSP48E. As a result, the

proposed FPGA is efficient in terms of hardware resources, as is shown

by the experimental results.

mable gate array (FPGA), memory-based architecture, radix-4,

VLSI.

I. I NTRODUCTION

Fig. 1. Proposed memory-based radix-4 FFT architecture. The PE is

The fast Fourier transform (FFT) is one of the most important composed of a radix-4 butterfly and three rotators.

algorithms in the field of digital signal processing, used to calculate

the discrete Fourier transform efficiently. The FFT is part of numerous

systems in a large variety of applications. Sometimes the system radix-4 approaches, it uses the minimum memory of N samples and a

demands the computation of the FFT at a very high rate. For this few additional multiplexers. Furthermore, the proposed approach has

purpose, pipelined FFTs are mainly used [1], [2]. In other systems, been implemented using DSP48E slices on a field programmable gate

the demands in terms of performance are not so strict. Instead, there array (FPGA). The implementation allows to integrate the compo-

are demands in terms of area or hardware resources occupied by the nents of the architecture in the DSP48E, which reduces the hardware,

architecture. Under these circumstances, the designers usually resort especially the amount of distributed logic. As a result, the proposed

to memory-based FFTs [3][11], also called in-place or iterative approach is a compact solution for the FPGA that takes an advantage

FFTs. of the use of DSP48E slices, leaving room in the FPGA for other

Memory-based FFTs consists of a memory or bank of memories complex and area demanding elements.

that store the data. These data are read from memory, processed by This brief is organized as follows. Section II describes the proposed

butterflies and rotators, and stored again in memory. This process memory-based FFT. Section III explains the implementation using

repeats iteratively until all the stages of the FFT algorithm are DSP slices. Section IV compares the proposed FFT to the previous

calculated. The advantage of memory-based FFTs is the reduction in memory-based FFTs. Section V presents an application where the

the number of butterflies and rotators, as they are reused for different proposed FFT has been used. Section VI shows the experimental

stages of the FFT. results on the FPGA. Finally, Section VII summarizes the main

There exist numerous memory-based FFT architectures in the lit- conclusions of this brief.

erature. They mainly differ in the size of the processing element (PE)

(butterflies and rotators). The most typical approach is to use a II. P ROPOSED M EMORY-BASED FFT

radix-2 butterfly [3][5], but there are cases of radix-4 [6], [7] A. Basic Architecture

and other radices [8][11]. Memory-based FFTs also differ in the

The basic architecture of the proposed 4096-point FFT is shown in

access strategy to the memory, which in most cases provides conflict-

Fig. 1. The architecture uses radix-4 and computes the FFT algorithm

free access. The amount of memory used in an N-point memory-

iteratively in six iterations, which comes from the fact that in a radix-r

based FFT is generally N or 2N. Apart from the memory, the

memory-based FFT, the number of iterations is

access strategy may demand extra multiplexers [7], buffers, or cache

memories. log2 N n

It = = . (1)

This brief presents a novel radix-4 memory-based FFT. The pro- log2 r log2 r

posed design has several advantages. With respect to the previous The proposed design includes four memories of N/4 samples in

parallel instead of a single memory of N samples. This allows to read

Manuscript received January 22, 2016; revised April 5, 2016; accepted

May 3, 2016. This work was supported by the Swedish ELLIIT Program. and write data simultaneously in all the memories, which reduces the

M. Garrido is with the Department of Electrical Engineering, latency and increases the throughput of the circuit. Thus, at every

Linkping University, Linkping SE-581 83, Sweden (e-mail: clock cycle, the PE receives and provides four samples in parallel,

mario.garrido.galvez@liu.se). one from and to each memory.

M. . Snchez and M. L. Lpez-Vallejo are with the Department of

Electrical Engineering, Universidad Politcnica de Madrid, Madrid 28040,

Spain (e-mail: masanchez@die.upm.es; marisa@die.upm.es). B. Conflict-Free Access

J. Grajal is with the Department of Signal, Systems and Radiocommuni-

cations, Universidad Politcnica de Madrid, Madrid 28040, Spain (e-mail:

As all four memories are accessed simultaneously, it must be

jesus@gmr.ssr.upm.es). assured that the four samples processed in the PE every clock cycle

Digital Object Identifier 10.1109/TVLSI.2016.2567784 come from different memories. This demands a conflict-free memory

1063-8210 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

Fig. 2. Circuits for the permutations in the multiplexers. They only consist

of multiplexers controlled by the bits of the counter. (a) 1 . (b) 3 . Fig. 3. Generation of the memory address for MEM2. The counter is

replicated twice and the corresponding bits are selected by the multiplexer.

Note that the circuit only consists of NOT gates and the multiplexer.

access strategy as shown next. The notation in this brief is the same

one used in previous works [12], [13].

Initially, samples are stored in natural order in the memories. is carried out by the memories. It only affects the content of the

Samples 0 to N/4 1 are stored in MEM0, N/4 to N/2 1 in memories. The memory address is obtained as

MEM1, and so on. If we number the samples from 0 to N 1 Wi+1 = Ri = c2i1 m 1 , c2i2 m 0 , . . . c1 m 1 , c0 m 0

with an index I bn1 bn2 . . . b0 , the position in memory of each

cn3 , . . . , c2i (8)

sample I is

where m 1 m 0 values are the bits that indicate the memory, ci values

P1 bn3 , bn4 . . . , b0 | bn1 , bn2 . (2) are the bits of the control counter, Wi+1 is the writing address at

serial (address) parallel (memory) iteration i + 1, and Ri is the reading address at iteration i. Note that

Wi+1 = Ri . This means that at each iteration, data are written in the

Bits bn1 and bn2 indicate in which of the four memories the addresses that are emptied in the previous iteration. This optimization

sample is stored, whereas bits bn3 , . . . , b0 are the address. allows to only use a total memory of N. For the first iteration,

In a radix-2 FFT, the butterfly at stage s operates on samples whose W1 = R0 is equal to the control counter. The generation of

indexes differ in the bit bns [2]. For radix-4, the butterfly at stage the memory address is shown in Fig. 3 for MEM2, for which

s operates on samples that differ in bits bn2s1 bn2s . At each m 1 m 0 = 10.

iteration of the FFT, these samples must arrive in parallel to the PE. The third permutation

For the first stage/iteration, bits bn1 bn2 are already in different

memories according to (2). For the second iteration, samples that 3 (u n1 , . . . , u 0 ) = u n1 , . . . , u 2 |u 3 u 1 , u 2 u 0 (9)

differ in bits bn3 bn4 need to arrive in parallel to the PE. This is is the permutation of the multiplexers after the memories, shown in

achieved by calculating the permutation Fig. 2(b). As 1 , it only determines the memory in which data are

stored.

(u n1 , . . . , u 2 |u 1 , u 0 ) = u n3 , u n4 , . . . , u 0 |u n1 , u n2 (3)

Finally, the first time that samples are read from the memory, the

on the data in position P1 , which leads to the position permutation 3 is disabled, i.e., the control signals are set to 00. This

happens because samples in the memory are already in the order

P2 bn5 , bn6 , . . . , b0 , bn1 , bn2 | bn3 , bn4 . (4) demanded by the PE.

Fig. 4 shows the data management for a 16-point FFT. The top

serial parallel

part of Fig. 4 shows the data orders at the different stages of the

For the rest of iterations, the same permutation is carried out to enable circuit below. First, data are stored in memory. Fig. 4 shows the

the correct samples into the PE. content of the different addresses in M0M3. These data are read

The permutation in (3) is carried out in three steps according to R0 = c1 c0 , i.e., data from the memories are read in

order. The data bypass the multiplexer after the memory, which is

= 3 2 1 . (5) disabled in this iteration, and inputs the butterfly. The data order

does not change until after the multiplexer that calculates 1 . This

The first permutation

multiplexer is controlled by cn3 cn4 = c1 c0 and only permutes

1 (u n1 , . . . , u 0 ) = u n1 , . . . , u 2 |u n1 u 1 , u n2 u 0 (6) parallel data that arrive in the same clock cycle according to 1 . The

data at the output of the multiplexer are stored again in memory. The

is the permutation of the multiplexers before the memories, where writing address is W1 = c1 c0 , which is equal to R0 to avoid memory

() represents the logic XOR function. The circuit that calculates access conflicts, as shown in (8). The memories are read according

this permutation is shown in Fig. 2(a). This permutation determines to R1 = c1 m 1 , c0 m 0 . Note that the writing and the reading in

the memory in which data are going to be stored. The permutation the memories lead to a permutation 2 on data that arrive in series

1 is controlled by the bits cn3 and cn4 . These are the two MSBs to the memories. Finally, a second parallel permutation, 3 , provides

of the control counter with bits cn3 , . . . , c0 . Thus, the control is the order required at the input of the butterfly for the second iteration.

simple, as it is taken directly from the bits of the counter. The output of the butterfly provides the output of the FFT.

The second permutation

C. Rotations

2 (u n1 , . . . , u 0 ) = u n3 , . . . , u 2 , u n1 u 1 , u n2 u 0 |u 1 , u 0 The rotations of the FFT are performed by three complex multi-

(7) pliers. Each of them is connected to a rotation memory, which is an

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Fig. 4. Data management example for a 16-point memory-based FFT. Here, W1 = R0 = c1 c0 and R1 = c1 m 1 , c0 m 0 .

are the bits of the counter. Each enable signal EN i is activated at iteration i

and the iterations after that one.

TABLE I

O UTPUTS OF THE M ODULE BTF0 AS A F UNCTION

OF THE C ONTROL B ITS

ROM of N/4 addresses that store the sine and cosine components

TABLE II

of the rotation angle = m(2 /N)i, where m {1, 2, 3} is

O UTPUTS OF THE M ODULE BTF1 AS A F UNCTION

the memory and i is the memory address. The memory address OF THE C ONTROL B ITS

of the rotation memories is generated in a simple way from the

control counter, as shown in Fig. 5. The address is the same for all

three memories and is obtained by enabling the bits of the counter

depending on the iteration.

The proposed architecture has been implemented on a Virtex-5

XC5VSX95T FPGA. The VSX family is characterized by including may be reduced when increasing the word length. Fig. 6 shows the

a large number of DSP48E and a small amount of distributed logic. architecture.

Thus, we have pursued to maximize the use of DSP48E and minimize The memories MEM0 to MEM3 are implemented using block

the use of distributed logic by implementing on DSP48E all the RAM (BRAM) memories. Each memory has 1024 addresses and each

elements of the architecture except the memories. An advantage of address stores a sample of 24 + 24 bits for the real and imaginary

using DSP slices is that they can be clocked at high clock frequencies. parts, respectively.

Furthermore, the implementation on DSP slices allows for large word The module BTF0 consists of two DSP48E in which the use

lengths without reducing the clock frequency, compared with designs of the multiplier has been disabled and allows to work with four

implemented in the distributed logic, where the clock frequency inputs of 24 + 24 bits. The Arithmetic logic unit inside the DSP48E

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TABLE III

C OMPARISON OF A CCESS S TRATEGIES IN M EMORY-BASED FFT S

imaginary components of the data are operated jointly.

Both sets of multiplexers in Fig. 2 would represent a significant

cost if they were implemented in the distributed logic. In order to

avoid this, the connections between the memory and the PEs are

static, i.e., the outputs of the memories are always connected to the PE

without multiplexing. This demands to modify the PE. The module

BTF0 calculates the first crossed terms of the radix-4 butterfly and

incorporates the multiplexers in Fig. 2(b). Thus, the BTF0 changes

the operations of the DSP48E depending on the two LSBs of the

control counter, according to Table I.

The module BTF1 is analogous to BTF0. It consists of two

DSP48E and calculates the second part of the radix-4 butterfly. The Fig. 7. Block diagram of the spectrum analyzer. The FFT is included in the

operations that are executed depend on the bits cn3 cn4 of the system and consists of a control (CTRL) block and four processing (PROC)

control counter, as shown in Table II. blocks, one for each of the channels.

The module TWD in Fig. 6 calculates the multiplications by the keeping the same TPROC as other radix-4 designs. In particular, it only

twiddle factors. The twiddle factors are stored in the ROM memory, needs a total memory of N samples compared with 2N samples [6]

which is used in all the iterations of the FFT. While, in the first or 2N( + 1) samples [10]. Note, however, that the approach in [6]

iteration, the coefficients are read one by one in order, in the rest is intended for continuous flow whereas our approach is not. Com-

of iterations, the LSBs of the control counter are canceled in order pared with [7] the proposed design reduces significantly the number

to determine the address [14], as shown in Fig. 5. As the outputs of multiplexers to only 16 2-input multiplexers, compared with

of BTF1 are shuffled, the twiddle factors are also provided in this 16 16-input multiplexers and demultiplexers in [7], which is equiva-

shuffled order. During the last iteration, the module TWD does not lent to 240 2-input multiplexers.

need to calculate any rotation. Thus, the multipliers of this module are V. A PPLICATION C ASE

used to calculate the squared magnitude of the complex values, i.e.,

The proposed FFT has been used for spectrum analysis. Fig. 7

|C 2 + S 2 |, in order to determine the power at each output frequency.

shows the block diagram of the spectrum analyzer. The system

includes four channels. Each channel consists of a finite-impulse

IV. C OMPARISON response (FIR) filter, a decimation stage (DEC), a 4096-point iterative

Table III compares various memory-based FFTs. In the memory- FFT, and a periodogram analysis.

based FFTs, there is a tradeoff between the amount of resources of The FIR filter is in charge of the bandwidth adaptation. The

the architecture and the processing time, TPROC . This depends on the filtering is done with appropriate coefficients to avoid aliasing, and

radix. The higher the radix, the larger the PE. A large PE increases to reduce the band interferences and noise.

the area, but reduces TPROC After the filter, data are decimated by a factor L = 8. The DEC

N block provides one sample every 20 ns to the FFT.

TPROC = I t TMEM (10) Once all the samples are loaded into the FFT module, the calcu-

r

lation of the FFT starts. The FFT module applies a window to the

where TMEM is the access time to the memory. Thus, radix-2 FFTs

input sequence, and then calculates the FFT, and finally, the squared

in Table III need less resources [3][5], whereas the high-radix

magnitude of the FFT (periodogram) is calculated to obtain the power

FFTs [8][10] achieve higher throughput.

of the signals.

Radix-4 is in the middle between radix-2 and high radices.

Therefore, it presents a tradeoff between resources and performance. VI. E XPERIMENTAL R ESULTS

Among radix-4 designs [6], [7], [10], the proposed approach is Table IV summarizes the figures of merit of the proposed

characterized by the use of the least amount of resources, while 4096-point memory-based FFT shown in Fig. 7. It processes four

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F IGURES OF M ERIT OF THE P ROPOSED M EMORY-BASED been implemented efficiently on an FPGA making use of the DSP

FFT ON A V IRTEX -5 XC5VSX95T FPGA slices. The proposed design requires less distributed logic than the

previous results on FPGA, while keeping a comparable amount of

DSP slices and BRAM.

R EFERENCES

[1] S. He and M. Torkelson, Design and implementation of a 1024-point

pipeline FFT processor, in Proc. IEEE Custom Integr. Circuits Conf.,

May 1998, pp. 131134.

[2] M. Garrido, J. Grajal, M. A. Snchez, and O. Gustafsson, Pipelined

radix-2k feedforward FFT architectures, IEEE Trans. Very Large Scale

Integr. (VLSI) Syst., vol. 21, no. 1, pp. 2332, Jan. 2013.

[3] D. Cohen, Simplified control of FFT hardware, IEEE Trans. Acoust.,

Speech, Signal Process., vol. 24, no. 6, pp. 577579, Dec. 1976.

[4] Y. Ma and L. Wanhammar, A hardware efficient control of memory

addressing for high-performance FFT processors, IEEE Trans. Signal

Process., vol. 48, no. 3, pp. 917921, Mar. 2000.

[5] Z.-G. Ma, X.-B. Yin, and F. Yu, A novel memory-based FFT architec-

ture for real-valued signals based on a radix-2 decimation-in-frequency

algorithm, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 9,

channels of 4096 points each with a word length of 24 + 24 bits. The

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clock frequency is 200 MHz. Higher clock frequency up to 400 MHz [6] B. G. Jo and M. H. Sunwoo, New continuous-flow mixed-radix (CFMR)

is also supported to reduce the processing time TPROC . Higher input FFT processor using novel in-place strategy, IEEE Trans. Circuits Syst.

rate up to four samples per clock cycle is also feasible in order to I, Reg. Papers, vol. 52, no. 5, pp. 911919, May 2005.

reduce the load time TLOAD . Area is measured in terms of slices, [7] X. Xiao, E. Oruklu, and J. Saniie, Fast memory addressing scheme

slice Lookup tables (LUTs), DSP48E, and BRAM. for radix-4 FFT implementation, in Proc. IEEE Int. Conf. Electro/Inf.

Technol., Jun. 2009, pp. 437440.

The implementation has been done on an FPGA. This differs

[8] P.-Y. Tsai and C.-Y. Lin, A generalized conflict-free memory addressing

from most memory-based FFTs in the literature, which have been scheme for continuous-flow parallel-processing FFT processors with

implemented on Application specific integrated circuits. A previ- rescheduling, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19,

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systems, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 8,

would use 11452 slice LUTs, 11968 slice FF, 96 DSP48E, and 32 pp. 17521765, Aug. 2012.

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the 98 DSP48E and 31 BRAM of the proposed design. However, techniques for FFT architectures, IEEE Trans. Circuits Syst. I, Reg.

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1407 slice LUTs and 1163 slice FF, compared with the 11452 slice [11] C.-F. Hsiao, Y. Chen, and C.-Y. Lee, A generalized mixed-

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logic in the proposed design. Furthermore, with this hardware, the [12] M. Garrido, Efficient hardware architectures for the computation of

proposed architecture calculates a complex FFT, whereas [5] is only the FFT and other related signal processing algorithms in real time,

valid for real-valued signals. Ph.D. dissertation, Dept. Signals, Syst. Radiocommun., Tech. Univ.

Madrid, Madrid, Spain, 2009.

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