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Original Title: 02 chapter ii basic theory

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Basic Theory

2.1 Conventional CMOS Logic Technique

With the widespread use of mobile, hand-held and wireless electronics devices,

the demands for the innovation of low power VLSI arise. For most of the digital circuits

today, CMOS logic scheme has been the technology of choice for implementing low

power system. As the clock and logic and speed increase to meet the new performance

requirements, the energy requirement of CMOS circuits are becoming a major concern in

the design of these devices.

2.1.1 Power Consumption of CMOS Circuits

Figure 2.1: Total power in a CMOS inverter: The dynamic power, short circuit

power, and leakage power.

Power consumption in a CMOS circuit generally divided into three parts such as

dynamic power, short-circuit power and static (or leakage) power. This chapter illustrates

those power consumption components in Fig.2.1. This figure describes that dynamic

power consumption occurs during the output nodes capacitor CL is switched, means

charging process of the node capacitor. This power is also sometimes called as charging

power. The short-circuit power happens when both transistors PMOS and NMOS operate

simultaneously during short period of time of different input signal transitions (such as In

signal changes from 0-1 and 1-0). The other contributing power is the static power, which

is consumed at MOS transistor PMOS and NMOS are operating in the cutoff region, or

during standby mode of real electronic devices. Mathematically, the three sources of

power dissipation in digital CMOS circuits that illustrated in Fig. 2.1 which summarized

in the following equation:

Ptotal= Pdynamic + Psc +Pstat (2.1)

To make it is clear for readers in this final thesis, the researcher will briefly explain each

factor of equation (2.1) in the following sub-sections.

Dynamic power consumption of a CMOS circuit is typically the dominant factor

in the total power dissipation in micro-meter or earlier CMOS technology. The value of

dynamic power depends on switching frequency f, amplitude of power supply Vdd.

Figure 2.2: (a) Conventional CMOS inverter, (b) A CMOS pull up network (PUN) RC

equivalent model for charging phase, (c) A CMOS pull down network (PDN) RC

equivalent model for discharging phase, the load capacitance CL of the output node.

The size of CL depends heavily on physical property of the used process technology, the

length of the wires to the subsequent cell and the numbers of subsequent cells of an

integrated circuit. To reduce this CL in the circuit system is one of challenges of logic

designers, particularly, in the placement and routing of the circuits layout. This is

normally causes the mismatching values of design parameters, such as power

consumption and/or peak current traces.

In this part, we analyze mathematically, how big the energy is stored in the output nodes

capacitor. Figure 2.2(a) shows a static CMOS logic inverter. The operation of this

inverter logic is that when the state of input signal Vx changes from 1 to 0, the transistor

MP is switched ON, the current supply from Vdd is flowing down to charge the output

node of CL from initial condition of Vy ( 0_ )= 0 to Vy=Vdd. The internal equivalent RC

model during this operation is called as pull-up network (PUN), as shown in Fig.2.2(b).

on the other hand, when the state of input signal Vx charges from 0 to 1, the transistor

MN is switched ON, the output node of Vy is discharged from initial condition of

Vy(0_)=Vdd to Vy=0 level (grounded). The internal equivalent RC model during this

operation is called pull-down network (PDN), as shown in Fig. 2.2(c). From the Fig. 2.2,

the total power dissipation can be calculated using each network system. By considering

the MOS resistance value of 1/gmn=1/gmp= R, CL=C, we can calculate the current

source that flows into the circuit, and then, further calculation of power dissipation of

each network system.

From the Kirchoff Voltage Law (KVL), the equation for pull-up (charging) network

shown in Fig. 2.2 has:

() + 1 0 () + (0_) += (2.2)

By using Laplace transform for Eq. (2.2), we define the instantaneous current of i (t)

1

() + () = (2.3)

() = (+1)

= 1 (2.4)

(+ )

Applying the inverse Laplace transform for Eq. (2.4), we define the following equation:

1

() = (2.5)

1

2

() = () () = ()2 = 2 + ) (2.6)

Therefore, the energy dissipated over the period = 0 = in Eq. (2.6) is expressed

as:

2

= 0 () + (0) = ( 2

1

+ 1) (2.7)

2

If, , :

1

= 2 (2.8)

2

Equation (2.8) shows that only half of the energy drawn from the power supply is stored

in the load capacitance; the other half is dissipated as heat by PUN resistor. All the signal

energy is dissipated during discharging in the PDN when the logic level in the output

node is 0, because no energy can enter the ground rail (Q. = . 0 = 0) [33].

Therefore, the total amount of energy dissipated as heat during charging and discharging

is

= +

= (12) 2 + (12) 2

= 2 (2.9)

Finally, the average dynamic power ( ) is consumed by the cells during a certain

period of time T can be formulated as shown in (2.10). In this equation, the f denotes the

clock frequency, and is the switching activity factor of the cell. The activity factor

corresponds to the average number 0 1 transition that occurs at the output cell in each

clock cycle.

= 2 . (2.10)

From the aforementioned equation, it is apparent that the energy consumption in a

conventional CMOS circuit can be reduced by scaling down the supply voltage of ,

decreasing the frequency of switching activity in the circuit, and/or lower the output node

capacitance.

Short circuit power () ) occurs because there is no finite zero period of rise time and

fall time of input signal transitions. During a certain interval time (herein after known as

short-circuit time or ) ) of the rise and fall edges of input signals, both PMOS and

NMOS of an static inverter logic will be ON-state simultaneously. At this time, the short-

circuit current path is established between the supply voltage and the common

ground. The detail discussion of short-circuit power was reported in[36], with an

expression shown in equation (2.11); where is gain factor of a MOS transistor,

represents the rise and fall time, f denotes a clock frequency, and the is the MOS

transistor threshold voltage.

1

= 12 ( 2 )3 . (2.11)

From the equation (2.10) and (2.11), we observe that short-circuit power is smaller than

the dynamic power, However, short-circuit power can also largely contribute to the huge

dynamic power when it comes to several cascaded buffer circuits or in inverter chain

circuit. For the clarity of dynamic and short circuit power, we have drawn both as

depicted in Fig. 2.31(gmbar).

Figure 2.3: simulation result of the shot-circuit and dynamic power consumptions of a

static CMOS inverter.

In a static CMOS inverter cells, static power consumption is typically very low. It

essentially consists of the power used when the transistor is not in the process of

switching. It occurs when small leakage current ( ) is flowing through the MOS

transistor that is turned off. Static power is increasing significantly proportional to the

shrinking of CMOS process technology.

There are several components that trigger the occurrence of leakage power [37]-[39];

such as: (1) Reverse bias diode leakage current = which occurs due to the reverse

bias current of p-n junction between diffusion region of the transistor and substrate. The

amplitude of this current is define as: = ( / 1), where A is a junction

area, is reverse saturations current density, is the reverse bias voltage across the

junction and = / is a thermal voltage; (2) Gate oxide tunneling current (0 ) is

the leak current that flows from oxide insulation to substrate. This value getting bigger

and bigger proportional to the scaling down of CMOS process technology, where the gate

oxide is also becoming thinner. The amplitude of this leak current is defined as =

2 / .

From this expression, the denotes the electric field across the oxide, B is the

physically-based exponential parameter; (3) Gate induced drain leakage (GIDL) is

another leakage current that increases exponentially due to the reduced gate oxide

thickness as estimated: = / where is the transverse electric field at the

surface; (4) Another component of leakage power is the subthreshold leakage current

( ). The subthreshold current flows from source to drain even if gate source voltage

below the threshold voltage of the device. This leak current occurs due to two

reasons, such as the weak inversion effect ( is lower but close to ) and the drain-

induced barrier lowering (DIBL). DIBL is the reduction of the threshold voltage of

transistor at high drain voltages. The subthreshold voltage is estimated as =

( + )/( ) [1 / ], where n is subthreshold swing

coefficient constant, is the linearized body effect coefficient, is the DIBL coefficient,

constant, and = 0 ()

2 1.8

, with 0 is zero bias electron mobility. All

components of leakage current that the author has just explained above are indicated in

Fig. 2.4. Thereby, the total summation of all leakage current components

aforementioned can be derived as:

= (2.12)

The previous section has explained the conventional CMOS power consumption, where

the global power dissipation is dominated by dynamic power (charging power). From the

given mathematical equations of each contributing components, we observe that the

common solution for power minimization is to reduce supply voltage . In this section,

this thesis introduces the adiabatic logic principle that is adopted in the authors secure

logic design to lower the peak supply current for resistance against power and

electromagnetic analysis attacks.

Adiabatic switching is commonly used to minimized energy loss during charging and

discharging. The word adiabatic (Greek adiabatos, which means impassable) indicates

a state change that occurs without heat loss or gain. During adiabatic switching, all the

nodes are charged or discharged at a constant current in order to minimize power

dissipation. This is accomplished by using AC power AC power supplies to initially

charge the circuit during specific adiabatic phases and then discharge the circuit to

recover the supplied charge. The principle of adiabatic switching can best be explained

by contrasting it with the conventional dissipative switching technique. The internal

equivalent RC model for charging and discharging output load capacitance is shown in

Fig. 2.5. The difference between the adiabatic inverter and the conventional CMOS

inverter is that, the conventional CMOS inverter uses the step voltage of , whereas the

adiabatic inverter uses power clock signal as source voltage, as can be seen in the Fig.

2.6(a) and (b) for CMOS and adiabatic model, respectively.

In adiabatic power consumptions analysis, the following calculation are done to obtain

the dissipated energy, where the is ramping time in Fig. 2.6(b):

1

() + () = (2.13)

Figure 2.5: (a) An adiabatic logic PUN equivalent RC model for charging phase, (b) An

adiabatic PDN equivalent RC model for discharging phase.

Applying the Laplace transform to Eq. (2.13), the following equations are derived

1

() + () = 2 (2.14)

1 1

() = ( +1)

2 =

( 1 ) (2.15)

+

1

() = (1 ) (2.16)

2 2 1

() = ()2 = (1 2 ) (2.17)

= () + (0)

0

2 2

2

1

= [ 2 ]

2 2 0

2 2 1 2

3

= (2 + ) (2.18)

2 2 2

2

= (2.19)

Figure 2.6: Comparison of the supply current transition for the equivalent RC models of

the (a) CMOS logic step voltage and (b) adiabatic logic ramped step voltage. (c) The

peak supply current of the adiabatic logic is significantly lower than that of the

conventional CMOS logic under the same parameters and conditions.

Analytical understanding of the Eq. (2.8) and Eq. (2.19), the energy dissipated by the

conventional CMOS inverter depends on the value of load C and the . On the other

hand, the most logical understanding for adiabatic inverter is that the energy dissipated

strongly depends on the transition switching time . Ideally, if the is the longer, energy

dissipation is nearly zero.

Figure 2.6(c) shown the comparison graph of the peak current traces of the conventional

CMOS logic and adiabatic logic using each respective equivalent RC model2. In this

figure, when 23 , the circuit operates in pull-up network, and the pull-down

network occurs at > 36 . For CMOS, a large amount and sudden flow of current can

be observed as indicated in Fig. 2.6(c). On the other hand, a gradual increase of supply

current peak could be seen in the same figure with red color trace. Similar shapes are

depicted during pull-down networks. By comparison, adiabatic circuit is sowing low peak

current. About five times lower than that of the CMOS peak current. Power consumption

is a function of instantaneous supply current and voltage, therefore, in adiabatic circuit, as

the total amount of current flow through the circuit is less, the power dissipation

definitely lower compare to the CMOS logic style.

2.3 FinFET

Conventional bulk MOSFET transistor suffers relatively large leakage current as the

technology scaling down. This leakage current makes the static power consumption

intolerable in deep submicron VLSI design. It is necessary to find a new device with

better gate control capability for substitute. FinFET is considered as a feasible choice.

FinFET is a sort of multi-gate transistor on SOI sub-strate [17], Figures 3(a) and (b)

illustrate the three dimensional diagram and cross sectional top view of a FinFET

transistor respectively. The thin vertical silicon fin is the conductive channel and the

poly-Si gate wraps the fin to control the channel effectively. It is because of this multi-

gate structure, FinFET devices diminish the Short Channel Effects (SCEs) and offer

higher on-state current, lower off-state current and faster switching speed [18].

It is noteworthy that the two vertical gate of FinFET can be separated by depositing oxide

on the top of silicon fin to get two independent gates, which will offer three different

operating modes for FinFET devices [19]. Figure 3(c) shows the electrical model

schematic of three operating modes.

Figure 2.7 FinFET model schematic, (a) three-dimensional diagram, (b) cross sectional

top view, (c) electrical model schematic.

Shorted gate (SG): the two gates are tied together as a single gate and FinFET is regarded

as a three-terminal device. This mode has the best gate control capability, so that the

transistor can work in the high performance state, including high on-state current and fast

switching speed.

Independent Gate (IG): in this mode, the two independent gates connect different gate

voltages. The device is worked as two parallel transistors is reduced and the flexibility of

design is increased.

Low power (LP): LP mode is a special IG mode. The two gates are divided into Front

Gate (FG), and Back Gate (BG). The FG connects to gate voltage, while the BG connects

to bias voltage ( ). Their relational expression is as follow:

= (2.20)

( + )

oxide thickness, and fin thickness, respectively. According to the above expression, if the

reverse bias voltage increases, the threshold voltage will follow the trend. Thus the power

consumption will decrease due to the direct correlation between leakage current and

threshold voltage.

In summary, FinFET has better device performance and more design flexibility (SG, IG,

and LP operating nodes) compared with bulk MOSFET.

The energy loss of adiabatic circuits is negligible without theoretically considering the

leakage power consumption. However, in the deep submicron stage, the leakage current

of bulk MOSFET transistor is biggish compared with the on state current. Adiabatic

circuits based on bulk MOSFET do not work well due to the relatively large current in

Recovery stage, especially in low-frequency field. In sect. 3, weve demonstrated the

significant advantages of FinFET devices compared with bulk MOSFET, i.e, lower off-

state current and higher on-state current. In this section we employ FinFET devices for

reconstructing adiabatic circuits to reduce the power consumption.

Fig. 2.8 Three adiabatic buffers based on SG mode FinFET.

Above figure depicts the three adiabatic buffer based on SG mode FinFETs. It is easy to

see that the bulk MOSFET transistors are substituted by SG mode FinFETs directly.

Because of the better control capability of FinFETs, the leakage current and switching

speed of the buffers are greatly improved. The main hindrance for energy recovery in

bulk MOSFET adiabatic circuit is the large leakage current in Hold and Recovery stage,

and a large part of the energy stored in capacitance is dissipated to the ground. For SG

mode FinFET adiabatic circuits, the significant reduction of leakage current improves the

recovery rate of the stored energy and reduces the power consumption in each clock

cycle.

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