Introduction to PSP

MOSFET Model

G. Gildenblat, X. Li, H. Wang, W. Wu
Department of Electrical Engineering
The Pennsylvania State University, USA

and

R. van Langevelde, A.J. Scholten, G.D.J. Smit and D.B.M. Klaassen
Philips Research Laboratories, The Netherlands

OUTLINE
† Origin and General Features of PSP
Project
† Technical Details
† Fitting Examples
† NQS
† Simulation Examples
† Conclusions

Key Objectives of PSP Project
† Merge the best features of the two
most advanced Surface-Potential-
Based Models (SPBM): SP and MM11
† Provide the modeling capabilities
down to 65nm node and beyond (in
the nearest future)
† Strengthen the infrastructure of the
SPBM

What Makes PSP Project Possible

† Similar approach to compact
modeling at PSU and Philips Research
† Similar modular structure of SP and
MM11
† Extension of Symmetric Linearization
Method beyond SP and MM11

Structure of PSP Model Global Parameter Set Local Parameter Set Core Intrinsic Extrinsic Support Modules JUNCAP PSP NQS .

Worth Noting PSP is far more than mixture of the best SP and MM11 modules. For example. the following PSP submodels go beyond both SP and MM11 versions. ‡ NQS ‡ Gate current .

including the output conductance degradation in long devices † Coulomb scattering and non-universality in the mobility model † Non-singular velocity-field relation enabling the modeling of RF distortions including intermodulation effects.General Features of PSP (I) † Physical surface-potential-based formulation in both intrinsic and extrinsic model modules † Physical and accurate description of the accumulation region † Inclusion of all relevant small-geometry effects † Modeling of the halo implant effects. † Complete Gummel symmetry .

flicker noise and channel- induced gate noise. † Advanced junction model including trap-assisted tunneling.General Features of PSP (II) † Mid-point bias linearization enabling accurate modeling of the ratio-based circuits (e. band-to-band tunneling and avalanche breakdown † Spline-collocation-based NQS model including all terminal currents † Stress model .g. R2R circuits) † Quantum-mechanical corrections † Correction for the polysilicon depletion effects † GIDL/GISL model † Surface-potential-based noise model including channel thermal noise.

OUTLINE † Origin and General Features of PSP † Technical Details † Fitting Examples † NQS † Simulation Examples † Conclusions .

5 -1.3 -1.2 Numerical Solution Analytical Approximation -40 -0.1 0 -20 -0.0 1.0 -0.5 0.1 40 Surface Potential (V) 0.0 0.5 Vgs (V) .5 1.0 20 Error (pV) -0.Surface Potential without Minority Carriers (for use in S/D overlap regions) 0.

PSP: ψs calculation VSB=1V with FPSP(u) .

Accuracy of ψs approximation .

It includes “universal” dependence on the vertical effective field Eeff and the deviations from the universality associated with the Coulomb scattering.Mobility PSP uses SP mobility model. MU0 ⋅ µ x µ= CS ⋅ qbm 2 1 + ( MUE ⋅ Eeff ) THEMU + ( qbm + qim ) 2 .

µE y Vd = 1 + (E y E c ) 2 This form also assures compliance with Gummel symmetry test and non-singular model behavior at Vds= 0. .Drift Velocity PSP uses MM11 drift velocity model that is conducive to the highly accurate description of saturation region including high order drain conductances.

. ∆ψ = ψ sd −ψ ss 1 + 1 + 2 ( ∆ψ Ec L ) 2 † No need for correction factors used in older SPBMs to reproduce proper behavior for small Vds † Subthreshold region is accurately modeled through ∆ψ † Velocity saturation is introduced in such a way that its effects automatically vanish in subthreshold.Drain Current 2 µ (W L )( qim + αφt ) ∆ψ Id = .

Lateral Field Gradient ( f = 1 − ( ε s qN sub ) ∂ ψ s ∂y 2 2 ) Most SPBMs use GCA: f = 1 HiSIM: f = f ( L. Vsb . Vgs .W ) ( SP. Vds ) . PSP: f = f L. W.

Symmetric Linearization (I) qi = qim − α (ψ s −ψ m )  2∆ψ  ψ ( y ) = ψ m + H 1 − 1 − ( y − ym )   HL  L  ∆ψ  y m = 1 +  2  4H  These equations are the same in SP and PSP .

Symmetric Linearization (II) Variable H in PSP is defined differently than in SP Without velocity saturation: H 0 = ( qim α ) + φt H SP = H 0 (1 + δ 0ξ ) −1 In SP: .  2  h = + 1 + 2ξ 2 2 2 ( ) 2 . ξ = ∆ψ Ec L −1 1  1 2 1 1 In PSP: H PSP = hH 0 1 + (ξ h )  .

Normalized Quasi-Static Charges Using Ward-Dutton partition qim α∆ψ  ∆ψ ∆ψ 2  QD = + 1 − − 2  2 12  2 H PSP 20 H PSP  α∆ψ 2 QI = qim − 12 H PSP ∆ψ 2 QG = Voxm − 12 H PSP QS = QI − QD QB = QG − QI .

Verification of Symmetric Linearization Normalized Transcapacitances 0. Vbs= 0 V.3 Cdg Cbg 0.9 Linearized CSM Original CSM Cgg 0.6 Csg 0.0 -1 0 1 2 3 4 Vgs (V) Vds = 2V. Vfb=-1V .

Based on MM11 formulation † Takes advantage of symmetric linearization to simplify expressions for the spectral densities † Experimentally verified . so it is not necessary to model this phenomena separately † Rigorously includes fluctuations in the velocity saturation term. 1/f noise. channel- induced gate noise and shot-noise in the gate-current † Thermal channel noise automatically becomes shot noise below threshold.PSP Noise Model † Includes thermal channel noise.

Example Drain (Sid) and gate (Sig) current noise spectral densities .

includes supply function † Includes contributions from both the channel and the overlap regions. PSP version is based on SP but is further developed † Experimentally verified using several processes from four different production facilities .Gate Current Model † Based on Tsu-Esaki formulation. Automatic scaling (no scaling parameters) † SP model extended MM11 formulation of Igate by including supply function.

0.025.042. 0.61 and 1V . Vds=0.Example Vsb=0V.

no binning) † NQS † Simulation Examples † Conclusions .OUTLINE † Origin and General Features of PSP † Technical Details † Fitting Examples (Global fit.

0 0.05 V 10 0.4 0.05 V -12 VDS = 0 .. ID-VGS for long/wide device 10 -6 VBS = 0 .4 0.2V 10 8 -7 10 I D ( µ A) 6 10 -8 I D (A) -9 4 10 -10 10 2 -11 10 VDS = 0 .0 0.8 1. –1.2 0.8 1.2 VGS (V) VGS (V) Philips 90nm LP-process NMOS W/L = 10µm/10µm .

05 V VDS = 0 .4 0.0 0..2V 30 10 g m ( µ A/V) g m / I D (1/V) 20 5 10 VDS = 0 .05 V 0. gm and gm/ID for long/wide device 15 40 VBS = 0 .2 10 -12 10 -11 10 -10 -9 10 10 10 -8 -7 10 -6 VGS (V) I D (A) Philips 90nm LP-process NMOS W/L = 10µm/10µm .8 1. –1.

1.8 1.34 .2 0.2V VBS = 0V -4 0.20 VGS = 0.4 0.10 10 -6 0.0 0.8 1.05 10 -7 10 0. ID-VDS for long/wide device 0.0 0.2 VDS (V) VDS (V) Philips 90nm LP-process NMOS W/L = 10µm/10µm .4 0..15 10 g DS (A/V) I D (mA) -5 0.

–1.2V -7 4 10 -8 10 -9 I D ( µ A) 3 10 I D (A) -10 10 -11 2 10 -12 10 -13 1 10 -14 VDS = 0 .4 0.05 V 10 -15 VDS = 0 .0 0.4 0.05 V 10 0..8 1.8 1.2 VGS (V) VGS (V) Philips 90nm LP-process NMOS W/L = 110nm/100nm . ID-VGS for short/narrow device 5 -6 10 VBS = 0 .2 0.0 0.

05 V 0.2 -15 -14 -13 -12 -11 -10 10 10 10 10 10 10 10 10 10 10 -9 -8 -7 -6 VGS (V) I D (A) Philips 90nm LP-process NMOS W/L = 110nm/100nm .2V 40 BS 6 30 g m ( µ A/V) g m / I D (1/V) 4 20 2 10 VDS = 0 .0 0.8 1. –1..4 0. gm and gm/ID for short/narrow device 8 V = 0 .05 V VDS = 0 .

8 1.2V VBS = 0V -4 0. 1.04 10 g DS (A/V) I D (mA) -5 0.0 0..06 VGS = 0.4 0.2 VDS (V) VDS (V) Philips 90nm LP-process NMOS W/L = 110nm/100nm .4 0.34 .0 0.8 1. ID-VDS for short/narrow device 0.02 10 -6 10 0.2 0.

Vds=0.CV Characteristics W/L = 800µm/90nm. Vsb=0 .

OUTLINE † Origin and General Features of PSP † Technical Details † Fitting Examples † NQS † Simulation Examples † Conclusions .

and all operation regions † Verified by comparison with experiments and channel segmentation method † Includes all major small-geometry effects † Similar to SP but further developed . includes all terminal currents.PSP NQS Model † Unified model for AC and transient simulations † Spline-collocation-based † Consistent with QS.

.Subcircuit-Based Implementation The differential equations to be solved: duk = − f k ( u1 .V2 ) . f 2 = f 2 (V1 .V2 ) V1=u1 V2=u2 R C R C Cf1 Cf2 R is sufficiently large so that the current flow through it is negligible ... u N ) dt Using sub-circuit approach (for N=2): f1 = f1 (V1 ..

8 1.0 0.8 1.6 0.6ns -2 -1 0.0 Time (ns) Time (ns) .4 0.0 0.6ns ID 1 IS 0 3V IB 3V QS -3V 0 -1 NQS 0.4 0.0 0.2 0.6 0.2 0. Extended Operation Range 2 3V 3V IG QS 2 -3V 1 NQS Currents (mA) Currents (mA) 0.

8 0.4 0.2 Currents (mA) 0V 0.6 Time (ns) .0 constant µ field-dependent µ -0.4 0.4 QS TCAD 0.2 0.0 0.6 3V 3V 1.3ns Symbols: NQS 0.Mobility Degradation Effects 1.

Wfing=10 µm. Nfing=6. pad open-short-dedicated open de-embedding (Tiemeijer et al.) L=3 µm.RF Modeling 90-nm Philips low-power technology Ground-signal-ground configuration. total width=120 µm † markers: measurements † dashed lines: PSP-QS † solid lines: PSP-NQS . MULT=2 i. common source bulk.w.o.

Re[Y11] PSP.5 V MM11.0 V VGS=1. SWNQS=9 VDS=1.5 V VGS=0. 5 segments .5 V VGS=1. SWNQS=5 PSP.

SWNQS=9 VDS=1. SWNQS=5 PSP.5 V VGS=0.0 V VGS=1.5 V MM11.5 V VGS=1. Cgg PSP. 5 segments .

0um .0/3. MN1. MN2 W/L=8.0/10.0um MP2. The “Killer” NOR Gate Vdd A MP1 X B MP2 Q MN2 MN1 MP1 W/L=8.

2 0.4 0. V(A) V(B) V(Q) NQS Node Voltages (V) 1.8 0.0 0 50 100 150 200 Time (ns) .6 V(Q) QS 1.

Node Voltage at X (V) 0 QS -5 NQS -10 0 50 100 150 200 Time (ns) PSP Default Parameter Set .

5 Node Voltage at X (V) 0 -5 QS -10 NQS -15 -20 0 50 100 150 200 Time (ns) Generic 90nm Process Parameter Set .

D. Grabinski. PSP development at PSU was supported in part by SRC. W. P. LSI Logic. Watson. J. Bendix.Acknowledgement The Authors are grateful to C. Freescale Semiconductor. G. Veeraraghavan for numerous stimulating discussion of the subject and to D. Foty. J. Victory. IBM and by simulation tools provided by Freescale Semiconductor. Mulvaney. McAndrew. Workman and S. B. Mentor Graphics and Agilent. Gloria and S. Boret for kindly providing the 90 nm RF data. . Arora. N.

philips.co /Philips_Models/mos_models/psp/index.PSP Code and Documentation http://www.html † documentation of the model and parameter extraction strategy † Verilog-A code † C-code † Modules that can be directly linked to Spectre and ADS .semiconductors.

Conclusions † The commonality between SP and MM11 has been used to merge them into a powerful new model – PSP † PSP has been extensively tested on several 90 nm nodes † PSP satisfies all the requirements for a next generation compact MOSFET model † PSP-SOI is in progress .