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Digital logic has evolved over the years and this process has led to the development of

a variety of families of digital logic integrated circuits. Each family has its own

advantages and limitations. This document describes the main logic families and their

characteristics. Among the technologies discussed here are DL, RTL, DTL, ECL, TTL,

CMOS and BiCMOS. All of these technologies were developed in the 1950s/1960s and

evolved over time. Some of these are still in use today.

Diode Logic (DL)

**Diode Logic (DL) is the most primitive of all the digital logic families. It is extremely
**

simple and inexpensive because it only uses passive components. In fact, it combines

diodes and resistors so sometimes it is known as Diode-Resistor Logic (DRL).

**Since DL does not use active components such as transistors, it does not provide
**

amplification and therefore inversion is not available. For this reason, DL only provides

AND and OR functions.

**Lack of amplification leads to signal degradation. This is due to the fact there is a
**

voltage drop across diodes and to the fact that when diodes conduct, a voltage divider

develops with the inputs.

**DL is an obsolete family, primarily due to its limitations in terms of inversion and
**

degradation.

1 www.ice77.net

OFFTIME = 100nS VA D1

ONTIME = 100nS CLK 1 2

DELAY = 0

STARTVAL = 1 V

1N4376 V

OPPVAL = 0

OFFTIME = 200nS VB D2

ONTIME = 200nS CLK 1 2

DELAY = 0

STARTVAL = 1 V

1N4376

OPPVAL = 0

R1

1k

0

DL implementation of the OR function

5.0V

2.5V

0V

V(VA:1) V(VB:1)

5.0V

**(250.000n,4.2321)
**

2.5V

SEL>>

0V

0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns

V(D2:K)

Time

Waveforms for the OR function

The circuit performs the correct logic but the voltage drop across the diode produces a

considerably lower high output voltage (4.2321V).

2 www.ice77.net

V+ V+

V1

R1

5Vdc

1k

OFFTIME = 100nS VA D1 0

ONTIME = 100nS CLK 2 1

DELAY = 0

STARTVAL = 1 V V

OPPVAL = 0 1N4376

OFFTIME = 200nS VB D2

ONTIME = 200nS CLK 2 1

DELAY = 0

STARTVAL = 1 V

OPPVAL = 0 1N4376

DL implementation of the AND function

5.0V

2.5V

0V

V(VA:1) V(VB:1)

5.0V

2.5V

(150.000n,767.935m)

SEL>>

0V

0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns

V(D1:A)

Time

Waveforms for the AND function

The circuit performs the correct logic but the voltage drop across the diode produces a

considerably higher low output voltage (767mV).

3 www.ice77.net

5V for high (1). RTL is known as Resistor-Capacitor Transistor Logic (RCTL). RTL is known as Direct-Coupled Transistor Logic (DCTL). uses active devices such as transistors and therefore can provide inversion. 2. The voltage range goes from 0V for low (0) to 3. RTL has two variants that attempt to improve some of its aspects: 1. When inputs are directly connected to the gate of the BJT. When capacitors are placed in parallel with input resistors. RTL is an obsolete digital logic family. RTL is very inefficient because it dissipates a great amount of power through heat. to speed up operation.ice77. This type of technology. 4 www. in order to save space and reduce fabrication costs. unlike DL.net . Fairchild Semiconductor introduced the first generation of RTL monolithic integrated circuits in either 1962 or 1963.Resistor-Transistor Logic (RTL) Resistor-Transistor Logic (RTL) was invented around 1956.

5Vdc R1 640 R2 Q1 OFFTIME = 100nS VA V ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 V 470 40240 OPPVAL = 0 0 RTL implementation of the NOT function 5.0V SEL>> 0V 0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns V(R1:1) Time Waveforms for the NOT function This circuit is nothing more than a common-emitter amplifier.0V 2. 0 V2 3.net .5V 0V V(VA:1) 4.0V 2. 5 www.ice77.

0V 2.5Vdc R1 OFFTIME = 100nS VA R3 640 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 470 V Q1 OPPVAL = 0 V 40240 OFFTIME = 200nS VB R4 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 V 470 R2 OPPVAL = 0 470 0 V4 -1Vdc 0 RTL implementation of the NOR function The NOR function can be implemented by the circuit shown above which consists of parallel inputs. a single BJT and two separate power supplies.5V SEL>> 0V V(VA:1) V(VB:1) 4. 5.0V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(Q1:c) Time Waveforms for the NOR function 6 www.net . 0 V3 3.0V 2.ice77.

OFFTIME = 100nS VA ONTIME = 100nS CLK 0 VA DELAY = 0 STARTVAL = 1 V OPPVAL = 0 V3 OFFTIME = 200nS VB 3. This solution has been used in 1962 for the Apollo Guidance Computer which. Compared to the previous. during the Apollo Project.0V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(R1:1) Time Waveforms for the NOR function 7 www. 5.5V SEL>> 0V V(VA:1) V(VB:1) 4.0V 2. this one has only one power supply but it has one BJT per input.5Vdc ONTIME = 200nS CLK VB DELAY = 0 STARTVAL = 1 V R1 OPPVAL = 0 640 Q1 Q2 V R3 R4 VA VB 470 40240 470 40240 0 RTL implementation of the NOR function (AGC) The NOR function can be implemented by the circuit shown above.0V 2. an advantage over the previous circuit.net . allowed astronauts to land on the Moon.ice77. The inputs are now isolated.

ice77. 0 V1 3.net . 8 www.5Vdc R3 640 V R1 Q1 OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 V 470 40240 OPPVAL = 0 R2 Q2 OFFTIME = 200nS VB ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 V 470 40240 OPPVAL = 0 0 RTL implementation of the NAND function The NAND function is implemented by the circuit shown above which consists of two parallel inputs. two stacked BJTs and a single power supply.

3.3.ice77.000n.5000) (250.net .3.9110) (50.0V (150.5000) 2.000n.0V 2.671m) SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(R3:1) Time Waveforms for the NAND function 9 www.5V 0V V(VA:1) V(VB:1) 5.000n.155.000n. 5.5V (350.

2. DTL is known as Complemented Transistor Diode Logic (CTDL).Diode-Transistor Logic (DTL) Diode-Transistor Logic (DTL) was invented in the 1950s.ice77. It is a major improvement over DL and RTL because it eliminates signal degradation and reduces power dissipation by means of a transistor which restores digital values and a set of input diodes which replace input resistors.net . When a Zener diode and a single power supply are connected to the base of the transistor. Signetics introduced the first generation of DTL monolithic integrated circuits in 1962. DTL is known as High-Threshold Logic (HTL). DTL has two variants that attempt to improve some of its aspects: 1. 10 www. DTL was used in the IBM 1401 decimal computer that was delivered in 1959. When a capacitor is placed in parallel with the base resistor and an inductor is placed in series with the collector resistor.

5V SEL>> 0V 0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns V(R2:1) Time Waveforms for the NOT function 11 www.0V 2.0V 2.net . 0 V1 5Vdc R2 R1 1k 4.5V 0V V(VA:1) 5.7k V D1 D2 Q1 OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 V D1N3902 D1N3902 MPS706 OPPVAL = 0 0 DTL implementation of the NOT function 5.ice77.

5V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(Q1:c) Time Waveforms for the NOR function 12 www.0V 2. R3 is in the circuit to limit excess current from entering the base of the transistor but slows down the switching of the circuit.net . 5.0V 2.5V SEL>> 0V V(VA:1) V(VB:1) 5.ice77. For this reason the NAND circuit is faster than this NOR circuit. 0 V1 5Vdc R2 4k OFFTIME = 100nS VA D1 ONTIME = 100nS CLK DELAY = 0 V STARTVAL = 1 D1N3902 V Q1 OPPVAL = 0 R3 2k MPS706 OFFTIME = 200nS VB D2 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 V D1N3902 OPPVAL = 0 R1 0 2k 0 DTL implementation of the NOR function (I) The NOR function can be implemented by the circuit shown above.

This NOR circuit is faster than the previous one.net . 0 0 0 V2 V1 V3 5Vdc 5Vdc 5Vdc R2 1k R1 R3 4. Eliminating the base resistor speeds up the circuit considerably.0V 2. this solution is a combination of two inverters. 5. it should be clear that the transition from 00 to 01 is much faster in the second NOR implementation. Essentially. 13 www.7k Q2 Q1 VB OFFTIME = 100nS VA D1 D2 MPS706 D3 D4 OFFTIME = 200nS ONTIME = 100nS CLK CLK ONTIME = 200nS DELAY = 0 DELAY = 0 STARTVAL = 1 V D1N3902 D1N3902 MPS706 D1N3902 D1N3902 V STARTVAL = 1 OPPVAL = 0 OPPVAL = 0 0 0 DTL implementation of the NOR function (II) The NOR function can also be implemented by the circuit shown above.5V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(Q2:c) Time Waveforms for the NOR function By comparing the waveforms for the two NOR circuits.ice77.5V 0V V(VA:1) V(VB:1) 5. The one on the left is the mirror image of the one of the right.0V 2.7k V 4. R2 is the common collector resistor.

5V 0V V(VA:1) V(VB:1) 5.7k OFFTIME = 100nS VA D2 ONTIME = 100nS CLK DELAY = 0 V STARTVAL = 1 D1N3902 V Q1 OPPVAL = 0 D1 D1N3902 MPS706 OFFTIME = 200nS VB D3 ONTIME = 200nS CLK DELAY = 0 STARTVAL = 1 V D1N3902 OPPVAL = 0 0 DTL implementation of the NAND function The NAND function is implemented by the circuit shown above.ice77. 0 V1 5Vdc R2 R1 1k 4.5V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(R2:1) Time Waveforms for the NAND function 14 www.0V 2. D1 avoids the situation where one of the inputs is 0 and a sufficient voltage builds at the base of the transistor to turn in into conduction.0V 2.net . 5.

it is possible to overdrive BJTs so they never enter the saturation region. Yourke at IBM. When MOSFETs replace BJTs. Since then.Emitter-Coupled Logic (ECL) Emittler-Coupled Logic (ECL) was invented in 1956 by Hannon S. VCC Output Input R1 R2 R3 220 245 Q5 907 PN2222 A+B Q6 V Q4 PN2222 -(A+B) Q1 Q2 Q3 PN2222 V R9 1k D1 PN2222 PN2222 PN2222 D1N4003 R10 D2 VEE 1k D1N4003 V V R4 R5 R7 R6 R8 VEE 50k 50k 6. Motorola introduced the first generation of ECL monolithic integrated circuits in 1962 and called it MECL I. ECL is also known as Current-Mode Logic (CML) or Current-Switch Emitter-Follower logic (CSEF). This type of situation allows extremely high speeds because overdriving avoids the diffusion time that affects the transistor when it transitions from the saturation region to the active region. ECL has been on the market and it’s still used today.70V VEE VCC TD = 0 V1 = -0. along with a specific range of input voltages. By using a differential amplifier.8V VA V2 = -1.ice77.net . input impedance is high and output impedance is low.1k 779 4.98k V1 = -0. ECL technology is know as Source-Coupled FET Logic (SCFL). ECL is fast but it requires a substantial amount of power which in turn produces high heat dissipation. ECL uses only NPN transistors.2Vdc PW = 2us TR = 0 VEE PER = 4us TF = 0 0Vdc PW = 4us PER = 8us 0 0 0 0 Circuit schematic for the MECL 10K by Motorola 15 www.8V VB TR = 0 V2 = -1. In ECL technology. ECL was originally known as Current-Steering Logic (CSL) because current can be steered to one side of the differential amplifier while the other side is practically shut off (typical feature of differential amplifiers).70V VEE VCC TF = 0 TD = 0 Compensation -5.

The output section is formed by Q5 and Q6.0us 6. Q2 or Q3) acts as a common-emitter stage with emitter degeneration which provides feedback and therefore additional stability. ECL is known as Positive Emitter-Coupled Logic (PECL). When VCC is reduced to 3.0us 2. For both inputs and outputs.2000u.5V SEL>> -2. One side is on and the other is off (one transistor draws all the current and starves the other transistor). provides temperature and voltage compensation. The input section has two inputs that are placed in parallel (VA and VB).0V V(Q1:b) V(Q2:b) -0.0us 7.9V and –0. When VCC=5V and VEE=0V. For output voltages.4V. The input range has an excursion of less than 1 V. compensation and output.000m) (1.0us 3. D2 and R8.5V -1.75V and –1. This is done to avoid variations in voltage from VCC (making it a ground is to set a stable point for the circuit). The upper power supply VCC is set to 0V. low logic (0) corresponds to 3.5V -2.0V (5.4V and high logic (1) corresponds to 4. The core of the circuit is the differential amplifier formed by Q1.3V. R7. R6 acts as a current source that sinks the current from the active branch of the differential amplifier.75V for a high signal (1).-800. 16 www.0us 4. ECL is known as Low- Voltage Positive Emitter-Coupled Logic (LVPECL). It varies between –1. The lower power supply VEE is –5.6965) -1. in order to reduce power. formed by Q4.-1.-1.5V -1.The circuit shown on the previous page can be divided into three sections: input. Q2 and Q3. With a 0 or a 1 at the input. 2. Essentially. R3.0V (5.7000) -1. it interfaces input and output stages and locks the circuit in the desired voltage/current range.580m) (1. low logic (0) corresponds to 1.ice77.2V. -0. the differential amplifier is overdriven.6V and high logic (1) corresponds to 2.6V for a low signal (0) and between –0.0us V(Q5:e) V(Q6:e) Time Waveforms for the OR/NOR functions ECL has two variants that attempt to improve some of its aspects: 1.2V. ECL was used in the IBM 7030 “Stretch” supercomputer that was delivered in 1961. The compensation section. D1.0000u.0us 8.-698.net .0000u.0V 0s 1. as previously explained.0000u. The active side (Q1.0us 5. ECL can only provide the OR and NOR functions.

the low logic signal (0) should be between 0V and 0.7V and 5V. F (fast) in 1979. The 6400 series did not have a great success and it was a transitional series between 5400 and 7400 in terms of temperature ranges. TTL has been on the market for a long time. S (Schottky) in 1969.8V and the high logic signal (1) should be between 2V and 5V. 1 According to Wikipedia. The 7400 family was designed for the regular market and became very popular.net . LS (low-power Schottky) and ALS (advanced low-power Schottky) in 1976?. particularly in the 70s and the 80s. 6400 and 7400 codes. ALS was born either in 1976. It was assigned the 5400. AS (advanced Schottky) in 1980? and G in 20041. Texas Instruments invented the 5400 line for military applications.Transistor-Transistor Logic (TTL) Transistor-Transistor Logic (TTL) was invented in 1961 by James L. TTL input and output Sylvania introduced the first generation of TTL monolithic integrated circuits in 1963. TTL has evolved and newer generations have been designed to speed up the technology as well as to reduce power consumption. 1980 or 1985 and AS was born either in 1980 or 1985. different generations of TTL technologies have been invented: L (low-power) and H (high-speed) came in 1964.5V the high logic signal (1) corresponds to values between 2. From 1964 to 2004. the low logic signal (0) stays between 0V and 0. Standard TTL chips works with a 5V power supply. TTL is also faster than DTL because it discharges the BE junction of the output transistor more quickly. at least until the advent of Very-Large Scale Integrated (VLSI) circuits. Buie at TRW. TTL replaced DTL’s diodes with multiple- emitter transistors.ice77. For the outputs. For the inputs. 17 www. The result was a higher level of integration. Since then. In an attempt to reduce the space utilized on a chip.

5V SEL>> 0V V(VA:1) 5.7k 1k MPSW43 Q1 V OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 Q2 STARTVAL = 1 V MPSW43 OPPVAL = 0 0 TTL implementation of the NOT function The NOT function is implemented by the circuit shown above.net .0V 2.5V 0V 0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns V(R2:1) Time Waveforms for the NOT function 18 www. This circuit is very similar to its DTL counterpart. 5. Notice that the two diodes are replaced by an NPN transistor in the np/pn sequence.0V 2.ice77. 0 V2 5Vdc R2 R1 4.

ice77.5V 0V V(VA:1) V(Q4:e) 5. This circuit is very similar to its DTL counterpart (diodes are replaced by transistors). 5.0V 2.5V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(R2:1) Time Waveforms for the NOR function 19 www.net . 0 0 0 V2 V1 V3 5Vdc 5Vdc 5Vdc R2 1k R1 R3 4.7k V 4.0V 2.7k Q3 Q1 Q2 Q4 OFFTIME = 100nS VA VB OFFTIME = 200nS ONTIME = 100nS CLK CLK ONTIME = 200nS DELAY = 0 DELAY = 0 STARTVAL = 1 V MPS706 MPS706 MPS706 MPS706 V STARTVAL = 1 OPPVAL = 0 OPPVAL = 0 0 0 TTL implementation of the NOR function The NOR function is implemented by the circuit shown above.

2 transistors (Q4 and Q5) and a diode (D1). 20 www. The totem-pole consists of a few additional components: 2 resistors (R3 and R4). the output is not symmetrical. it is a reasonable way to go about the high resistance problem. the chip offers high resistance at the collector of Q3 and this is undesirable because this situation lowers the fanout (the ability to connect many gates at the output without overloading the circuit). When the output of the circuit goes to logic 1. To overcome this deficiency. 0 V3 5Vdc R4 R2 130 R1 1.net .6k 4k Q4 MPS706 Q1 Q3 D1 OFFTIME = 100nS VA ONTIME = 100nS CLK MR504 DELAY = 0 STARTVAL = 1 V MPS706 MPS706 OPPVAL = 0 Q2 V OFFTIME = 200nS VB Q5 ONTIME = 200nS CLK DELAY = 0 MPS706 STARTVAL = 1 V MPS706 R3 OPPVAL = 0 1k 0 0 TTL implementation of the NAND function The NAND function is implemented by the circuit shown above. Although the solution is not optimal. The totem-pole is added to the right of what looks like a two-input inverter and it helps to overcome the high output resistance previously mentioned.ice77. the totem-pole was invented.

5V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(D1:2) Time Waveforms for the NAND function 21 www. 5.ice77.5V 0V V(VA:1) V(VB:1) 5.0V 2.net .0V 2.

Complementary Metal-Oxide Semiconductor (CMOS) Complementary Metal-Oxide Semiconductor (CMOS) was invented in 1963 by Frank Wanlass at Fairchild semiconductor. This type of technology introduced a new design approach that completely revolutionized the electronics industry: n and p transistors are dual to each other and that they can be combined to provide logic by reducing power consumption (as opposed to previous technologies where only one type of transistor was used). which became popular with the 7400 family. CMOS devices have speed limitations due to internal capacitance which slows down their operation. V is voltage and f is frequency (the activity factor is a number between 0 and 1 that describes how busy is a CMOS device). As a result. microprocessors and microcontrollers are now made of CMOS devices. CMOS technology became the leading technology for VLSI circuits because it could be highly integrated. When compared to older technologies. CMOS drastically reduces power consumption and heat dissipation. thus only when both transistors are simultaneously active and conduct current. CMOS can operate at different power supply voltages ranging from 3V to 15V. RCA introduced the first generation of CMOS monolithic integrated circuits either in 1968 or in 1970. CMOS has become famous with the 4000 family. 22 www. CMOS. C is capacitance. consumes power only during changes between logic states.net .ice77. Power dissipated is a function of four variables and it’s described by P=αCV2f where α is the so-called activity factor. in fact. CMOS is sensitive to electrostatic discharge or ESD so when handling CMOS devices. Just like TTL. additional care needs to be used to avoid damage.

ice77.net .23 www.

net .ice77.24 www.

0V 0V 0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns V(VA:1) V(M1:d) Time Waveforms for the NOT function The transistors are modeled with the following parameters: Wp=100µ. Cgdpo=511.7V. 5. Cbdp=2.0V 4.ice77. Cgsno=1. This circuit shows the symmetry and the duality of CMOS technology.293pF.Static circuits Static circuits do not use any external clock.329pF. Vtno=+0. The two transistors are complementary and they are mirror images of each other. Lp=2µ. Vtpo=-0.3pF Wn=100µ. 0 V1 5Vdc M2 IRFP9141 OFFTIME = 100nS VA ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 V V OPPVAL = 0 M1 IRFP253 0 Static CMOS implementation of the NOT function The NOT function is implemented by the circuit shown above.368pF.1pF.7V. Cgdno=496pF 25 www. Cgspo=818. Cbdn=4.0V 2. Ln=2µ.net .

for n NMOS transistors. Lp=2µ. Cbdn=4.0V 2. Vtpo=-0. For static CMOS circuits.368pF.293pF. Cbdp=2.ice77.net . 5.5V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(M1:d) Time Waveforms for the NOR function The transistors are modeled with the following parameters: Wp=100µ. Cgdno=496pF 26 www. Ln=2µ.7V. 0 V1 5Vdc OFFTIME = 100nS VA ONTIME = 100nS CLK VA DELAY = 0 M3 STARTVAL = 1 V OPPVAL = 0 VA OFFTIME = 200nS VB ONTIME = 200nS CLK VB IRFP9141 DELAY = 0 STARTVAL = 1 V OPPVAL = 0 M4 VB IRFP9141 V M1 M2 VA VB IRFP253 IRFP253 0 Static CMOS implementation of the NOR function The NOR function is implemented by the circuit shown above.1pF.5V 0V V(VA) V(VB) 5. This circuit shows the duality of CMOS technology. Vtno=+0. N transistors are complementary to P transistors (N in parallel and P in series). Cgsno=1.0V 2.329pF. Cgspo=818.7V. there is an equal number of PMOS transistors. Cgdpo=511.3pF Wn=100µ.

Cgdpo=511. Cgdno=496pF 27 www. Cgsno=1. Vtno=+0. N transistors are complementary to P transistors (N in series and P in parallel).0V 2. 5.329pF.7V. This circuit shows the duality of CMOS technology.0V 2. Vtpo=-0.ice77. for n NMOS transistors. 0 V1 5Vdc M3 M4 VA VB IRFP9141 IRFP9141 V M1 VA IRFP253 OFFTIME = 100nS VA ONTIME = 100nS CLK VA DELAY = 0 STARTVAL = 1 V OPPVAL = 0 M2 OFFTIME = 200nS VB ONTIME = 200nS CLK VB DELAY = 0 VB STARTVAL = 1 V OPPVAL = 0 IRFP253 0 Static CMOS implementation of the NAND function The NAND function is implemented by the circuit shown above.293pF.7V.1pF. Cgspo=818.3pF Wn=100µ. For static CMOS circuits. Ln=2µ.368pF. Lp=2µ. there is an equal number of PMOS transistors. Cbdp=2.net .5V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(M4:d) Time Waveforms for the NAND function The transistors are modeled with the following parameters: Wp=100µ. Cbdn=4.5V 0V V(VA) V(VB) 5.

885fF. Lp=100n.5V SEL>> 0V V(VA1) V(VB1) 4. It’s generally faster than standard CMOS circuits because eliminating PMOS transistors leads to a reduction in capacitance within the circuit.Complementary Pass-Transistor Logic (CPL) is a CMOS subclass that uses NMOS transistors to provide the logic.288fF.5fF Wn=100m. Cgsno=1. Vtno=+0.2fF.ice77. CPL needs complements of all inputs and provides complements of the implemented functions.net .3V.0V 2.0V 2.3Vdc U4A 1 2 VB0 0 V OR M5 M2N6659 74F04 VB1 CPL implementation of NOR/OR functions 5.0V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(M3:g) V(M6:g) Time Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=2µ.564fF 28 www.3V. Cgdpo=138. Vtpo=-0. V+ OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK VA1 VB0 DELAY = 0 STARTVAL = 1 V M3 OPPVAL = 0 U1A M1 M2N6659 1 2 VA0 VA1 M2N6845 74F04 OFFTIME = 200nS DSTM2 U3A ONTIME = 200nS CLK VB1 DELAY = 0 1 2 VB1 STARTVAL = 1 V OPPVAL = 0 U2A V NOR M2 M2N6659 1 2 74F04 VB0 VB1 74F04 V+ VB0 M6 V+ M4 M2N6659 VA0 M2N6845 V1 3. Cgspo=2. Cgdno=7. Cbdp=899. Cbdn=118fF. Ln=100n.

3Vdc 3. CVSL needs complements of all inputs and provides complements of the implemented functions. Vtno=+0. Cgsno=739. Vtpo=-0.14fF 30 www. Lp=1µ. Cgspo=2.397fF.4fF Wn=1m.0V 2.8fF. Cgdno=82. Ln=1µ. Cgdpo=306.3Vdc OFFTIME = 100nS DSTM1 M5 M6 ONTIME = 100nS CLK VA1 DELAY = 0 STARTVAL = 1 V OPPVAL = 0 U1A IRFF9110 IRFF9110 1 2 VA0 NOR OR 74F04 V V OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK VB1 DELAY = 0 M3 STARTVAL = 1 V OPPVAL = 0 U2A VA0 1 2 VB0 IRFF110 M1 M2 74F04 VA1 VB1 M4 IRFF110 IRFF110 VB0 IRFF110 0 0 Static CVSL implementation of NOR/OR functions 5. 0 0 V1 V2 3.0V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(M6:d) V(M2:d) Time Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=10µ.5V.5V.4fF.5V 0V V(VA1) V(VB1) 4. Cbdn=377.ice77.net . Cbdp=324.Cascode Voltage Switch Logic (CVSL) is a CMOS subclass that uses NMOS transistors to provide the logic.9fF. It’s generally faster than standard CMOS circuits because eliminating PMOS transistors leads to a reduction in capacitance within the circuit.0V 2.

4fF Wn=1m. Cbdn=377.397fF. Cgspo=2.net . Cgdno=82.ice77.0V 2.9fF.0V SEL>> 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(M4:d) V(M5:d) Time Waveforms for the NAND/AND functions The transistors are modeled with the following parameters: Wp=10µ. Cgdpo=306.5V 0V V(VA1) V(VB1) 4.4fF.3Vdc 3.14fF 31 www. Lp=1µ.5V.5V.8fF. Ln=1µ.0V 2. Cgsno=739.3Vdc OFFTIME = 100nS DSTM1 M5 M6 ONTIME = 100nS CLK VA1 DELAY = 0 STARTVAL = 1 V OPPVAL = 0 U1A IRFF9110 IRFF9110 1 2 VA0 NOR AND 74F04 V V OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK VB1 DELAY = 0 STARTVAL = 1 V M1 OPPVAL = 0 U2A VA1 1 2 VB0 M3 M4 IRFF110 VA0 VB0 74F04 M2 IRFF110 IRFF110 VB1 IRFF110 0 0 Static CVSL implementation of NAND/AND functions 5. Vtpo=-0. Cbdp=324. 0 0 V1 V2 3. Vtno=+0.

5V 0V V(VA1) V(VB1) 5. Ln=100n. 32 www. Cbdn=118fF. Cgsno=1.ice77.2fF.288fF. Cbdp=899.885fF.3V.3Vdc CLK V OR M4 M2N6659 74F04 VB1 0 Dynamic CPL implementation of the NOR/OR function 5. Cgspo=2. Cgdno=7.0V 2.5V SEL>> 0V 0s 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800ns V(U3A:Y) V(U4A:Y) V(CLK) Time Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=2µ.Dynamic circuits Dynamic circuits use external clocks.564fF The PMOS transistor (pr0B) is called the weak-keeper. It is small in size and it helps to avoid output voltage degradation.0V 2.net . Cgdpo=138. Lp=100n.3V. Vtno=+0. V+ OFFTIME = 200nS DSTM1 ONTIME = 200nS CLK VA1 VB0 DELAY = 0 STARTVAL = 1 V pr0A pr0B OPPVAL = 0 U1A M1 M2N6659 1 2 CLK VA0 VA1 M2N6845 M2N6845 74F04 OFFTIME = 400nS DSTM2 U3A ONTIME = 400nS CLK eV1A M2N6659 VB1 DELAY = 0 1 2 VB1 STARTVAL = 1 V OPPVAL = 0 U2A CLK V NOR M2 M2N6659 1 2 74F04 VB0 VB1 74F04 V+ OFFTIME = 100nS CLK ONTIME = 100nS CLK CLK DELAY = 0 STARTVAL = 1 VB0 V OPPVAL = 0 pr0C pr0D M3 M2N6659 CLK VA0 V+ M2N6845 M2N6845 U4A V1 eV1B M2N6659 1 2 VB0 3.5fF Wn=100m. Vtpo=-0.

397pF.5V 0V 0s 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800ns V(CLK) V(M3:d) V(M2:d) Time Waveforms for the NOR/OR functions The transistors are modeled with the following parameters: Wp=500µ.4pF Wn=1m. Cgsno=739. Cgdpo=306.0V 2.5V.3Vdc CLK OFFTIME = 200nS DSTM1 M5 M6 ONTIME = 200nS CLK pr0 VA1 DELAY = 0 STARTVAL = 1 V OPPVAL = 0 U1A IRFF9110 IRFF9110 1 2 VA0 NOR OR 74F04 V V OFFTIME = 400nS DSTM2 M3 ONTIME = 400nS CLK VB1 DELAY = 0 VA0 STARTVAL = 1 V OPPVAL = 0 U2A M1 M2 IRFF110 1 2 VB0 VA1 VB1 M4 74F04 IRFF110 IRFF110 VB0 IRFF110 OFFTIME = 100nS CLK ONTIME = 100nS CLK CLK DELAY = 0 STARTVAL = 1 V OPPVAL = 0 eV1 CLK IRFF110 0 Dynamic CVSL implementation of NOR/OR functions 5.8fF. Cbdp=324. Vtpo=-0. Lp=100n. Cgspo=2.net . Cgdno=82.9pF. Ln=1µ.5V SEL>> 0V V(VA1) V(VB1) 5. Vtno=+0.0V 2. 0 0 V1 V2 3.4fF.ice77.5V. Cbdn=377.14pF 34 www.3Vdc 3.

5V. Lp=100n.0V 2.9pF. Cgspo=2. Cgdpo=306. Ln=1µ.3Vdc 3. 0 0 V1 V2 3. Cbdn=377. Cbdp=324.ice77.5V 0V 0s 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800ns V(CLK) V(M3:d) V(M5:d) Time Waveforms for the NAND/AND functions The transistors are modeled with the following parameters: Wp=500µ.0V 2.397pF.8fF.5V SEL>> 0V V(VA1) V(VB1) 5. Cgdno=82.14pF 35 www.net .4fF.4pF Wn=1m. Vtpo=-0.5V. Cgsno=739.3Vdc CLK OFFTIME = 200nS DSTM1 M5 M6 ONTIME = 200nS CLK pr0 VA1 DELAY = 0 STARTVAL = 1 V OPPVAL = 0 U1A IRFF9110 IRFF9110 1 2 VA0 NAND AND 74F04 V V OFFTIME = 400nS DSTM2 ONTIME = 400nS CLK M1 VB1 DELAY = 0 STARTVAL = 1 V U2A VA1 OPPVAL = 0 M3 M4 1 2 IRFF110 VB0 VA0 VB0 M2 74F04 IRFF110 IRFF110 VB1 IRFF110 OFFTIME = 100nS CLK ONTIME = 100nS CLK CLK DELAY = 0 STARTVAL = 1 V OPPVAL = 0 eV1 CLK IRFF110 0 Dynamic CVSL implementation of NAND/AND functions 5. Vtno=+0.

0V 2.293fF. 36 www. Cgdpo=5. Domino does not need complements of all inputs.113fF Wn=1m.3V. Lp=1µ. Cgspo=818. these two signals overlap. The clock signal can also be split and two separate clocks can be supplied to the circuit. When the clock is 1 (evaluation phase). Vtno=+0.0V 2. Ln=1µ. It is small in size (1/10 of NMOS) and it helps to avoid output voltage degradation. Cbdn=4. Cgsno=1.Domino Logic is a CMOS subclass that uses NMOS transistors to provide the logic. NMOS transistors provide the logic to the output. Cgdno=4. Sometimes.5V SEL>> 0V V(VA) V(VB) 5.net . Cbdp=2. pr0 charges the node below it to 1.3Vdc wk pr0 IRFU9010 OFFTIME = 200nS VA ONTIME = 200nS CLK VA DELAY = 0 STARTVAL = 1 V IRFP9141 OPPVAL = 0 U1A OFFTIME = 400nS VB ONTIME = 400nS CLK 1 2 VB DELAY = 0 STARTVAL = 1 V 74F04 V OPPVAL = 0 M1 M2 CLK VA VB IRFP253 IRFP253 OFFTIME = 100nS CLK ONTIME = 100nS CLK CLK DELAY = 0 eV1 STARTVAL = 1 V OPPVAL = 0 IRFP253 0 Domino implementation of the OR function 5. Vtpo=-0.329fF. When the clocks is 0 (precharge phase).5V 0V 0s 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800ns V(CLK) V(U1A:Y) Time Waveforms for the OR function The transistors are modeled with the following parameters: Wp=1m.3V.368fF. It’s generally faster than standard CMOS circuits because eliminating PMOS transistors leads to a reduction in capacitance within the circuit. 0 V1 3.96fF PMOS transistor IRFU9010 acts as a weak-keeper.ice77.1fF.

368fF. Cgdno=4.net . Lp=1µ. Vtno=+0.ice77. Cgspo=818. 0 V1 3.3V.96fF PMOS transistor IRFF9233 acts as a weak-keeper. It is small in size (1/10 of NMOS) and it helps to avoid output voltage degradation.329fF. Cbdn=4.0V 2.3Vdc pr0 wk OFFTIME = 200nS VA ONTIME = 200nS CLK VA DELAY = 0 IRFP9141 IRFF9233 STARTVAL = 1 U1A V OPPVAL = 0 1 2 OFFTIME = 400nS VB ONTIME = 400nS CLK M2 74F04 V VB DELAY = 0 STARTVAL = 1 V VB OPPVAL = 0 IRFP253 CLK M1 OFFTIME = 100nS CLK VA ONTIME = 100nS CLK CLK DELAY = 0 STARTVAL = 1 V IRFP253 OPPVAL = 0 eV1 IRFP253 0 Dynamic CMOS implementation of the AND function 5.5V SEL>> 0V 0s 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800ns V(CLK) V(U1A:Y) Time Waveforms for the AND function The transistors are modeled with the following parameters: Wp=1m. Cgsno=1.113fF Wn=1m.293fF.1fF.0V 2. Cbdp=2. Cgdpo=5. 37 www.5V 0V V(VA) V(VB) 5. Vtpo=-0.3V. Ln=1µ.

ice77. BiCMOS has also higher power consumption than CMOS so BiCMOS is not particularly appealing when saving energy is an issue. Since BJTs are much bigger than CMOS circuits.net . 38 www.Bipolar-CMOS (BiCMOS) Bipolar-CMOS (BiCMOS) was invented in 1969. This type of technology is hybrid in nature because it combines bipolar transistors (BJTs) to field effect transistors (MOSFETs) in order to combine the advantages of both devices. The BJT has low output resistance. high switching speed and high voltage gain. The MOSFET exhibits high input impedance and low power consumption. The circuit can be divided in two stages: the input stage consists of CMOS transistors whereas the output stage is made by BJT transistors. BiCMOS has also some disadvantages that prevent this type of technology from becoming popular. it is virtually impossible to fabricate integrated circuits at competitive prices because their fabrication would require additional steps and therefore additional costs.

Cgdpo=291. Lp=45n.net .9fF Wn=1µ.156fF. Ln=45n.399m) 0V -2.8fF 39 www.5V. VCC VCC M4 OFFTIME = 100nS DSTM1 ONTIME = 100nS CLK DELAY = 0 STARTVAL = 1 V OPPVAL = 0 IRFP9140 Q1 Q2N4141 M1 IRFP462 0 VCC V M2 V1 5Vdc IRFP462 Q2 0 M3 Q2N4141 IRFP462 0 0 BiCMOS implementation of the NOT function 6.0V (45.293fF. Vtpo=-0.0V 2.-265. Cgsno=1.0V (150.038pF.947pF. Cbdp=2.0V 0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns V(DSTM1:1) V(M2:d) Time Waveforms for the NOT function The transistors are modeled with the following parameters: Wp=1µ.000n.ice77.4. Cgdno=135. Cgspo=1.000n.5V. Cbdn=5. Vtno=+0.5129) 4.

Cgsno=1.038pF.165m) 0V -2. Lp=45n.net . VCC VCC M6 IRFP9140 M7 OFFTIME = 100nS DSTM1 VA ONTIME = 100nS CLK VA DELAY = 0 STARTVAL = 1 IRFP9140 V Q1 OPPVAL = 0 Q2N4141 M1 M2 OFFTIME = 200nS DSTM2 ONTIME = 200nS CLK VB DELAY = 0 STARTVAL = 1 V OPPVAL = 0 IRFP462 IRFP462 0 0 V M3 M4 VB VA IRFP462 IRFP462 Q2 VCC M5 Q2N4141 V1 5Vdc IRFP462 0 0 0 BiCMOS implementation of the NOR function 6. Cbdn=5. Vtpo=-0.4887) 4.156fF.5V.-257.0V (320.947pF.9fF Wn=1µ. Cgdpo=291. Cgdno=135.293fF. Ln=45n. Vtno=+0.4. Cbdp=2.0V (40.8fF 40 www. Cgspo=1.000n.5V.0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(DSTM1:1) V(DSTM2:1) V(Q1:e) Time Waveforms for the NOR function The transistors are modeled with the following parameters: Wp=1µ.000n.0V 2.ice77.

4.5V.038pF.9fF Wn=1µ. Lp=45n.156fF. VCC VCC VCC M7 M6 VA VB IRFP9140 IRFP9140 M1 OFFTIME = 100nS DSTM1 VA ONTIME = 100nS CLK VA DELAY = 0 STARTVAL = 1 V IRFP462 Q1 OPPVAL = 0 M2 Q2N4141 OFFTIME = 200nS DSTM2 VB ONTIME = 200nS CLK VB DELAY = 0 STARTVAL = 1 V IRFP462 OPPVAL = 0 0 V M3 VB IRFP462 VCC M4 V1 VA 5Vdc IRFP462 Q2 0 M5 Q2N4141 IRFP462 0 0 BiCMOS implementation of the NAND function 6.0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(DSTM1:1) V(DSTM2:1) V(Q1:e) Time Waveforms for the NAND function The transistors are modeled with the following parameters: Wp=1µ.5323) 4.ice77.443m) 0V -2.-258.0V (40.8fF 41 www.0V (340. Cgspo=1. Cbdp=2. Cgsno=1.0V 2.net .947pF. Cgdpo=291. Vtno=+0. Vtpo=-0.293fF. Cgdno=135.000n. Cbdn=5. Ln=45n.000n.5V.

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