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Flat No. C-55, O.N.G.C.

Colony,
Vidyavihar(East), Rajawadi,
Mumbai- 400077.
India
Email: rohitshukla10@gmail.com
Rohit Shukla

Objective:
I am an Undergraduate student at the Indian Institute of Information Technology,
Allahabad (Centre of Excellence in IT and microelectronics under Ministry of HRD, Govt
of India) / (Deemed University under Ministry of HRD, Govt of India).

I am looking for Internship for the final semester of 2011 (mid Jan- mid July) that will
utilize my present skills and offer me the opportunity to learn new things and explore
future career possibilities.

Education:
Indian Institute of Information Technology (IIIT), Allahabad, India
Bachelor of Technology, [2007 -] (Expected Graduation Date: July 2011)
Electronics and Communication Engineering
CGPI: 9.55/10.00; Major GPI: 10.00/10.00
Ranked 2nd in the department and 4th in the institute.
Kendriya Vidyalaya, IIT Powai, Mumbai, India
AISSCE, CBSE, [2006] 88%
Ranked 3rd in school in the batch of 108 students.
Kendriya Vidyalaya, IIT Powai, Mumbai, India
AISSE, CBSE, [2004] 90.6%

Research Interests:
Digital VLSI.Design, VLSI signal processing, digital signal processing, computer architecture,
digital electronics and wireless communication

Publications:
Conference: Kailash Chandra Ray, Rohit Shukla, Anindya Sundar Dhar, “CORDIC-
based VLSI architecture for implementing Log-Polar transformation
for real time applications” IEEE international conference, ICCCNT 2010,
Chettinadtech, Karur, Tamilnadu.

Presentation:
At IEEE international conference ICCCNT 2010 on the topic, “CORDIC-based VLSI
architecture for implementing Log-Polar transformation for real time applications”. The
presentation was delivered under the session’s chairperson Dr. Bella Bose, Oregon State
University, USA and it was highly appreciated by him.
Technical Skills:
Software Packages Known: MATLAB, Xilinx ISE simulator10.1, Xilinx AccelDSP, LabView,
winAVR, KeilC compiler, g++ complier and 8086 emulator.
Hardware skills acquired: Spartan 3E and Virtex 5 FPGA system, Rhode and Schwarz VNA,
Atmega 32, 8051 microcontroller, and 8086 microprocessor.

Projects:
I. 22/5/10–19/7/10: Summer Intern
Remote sensing laboratory
Department of Electronics and Computer Engineering
Indian Institute of Technology, Roorkee

Topic: Study of GPR data and shape recognition for buried object
Mentor: Dr. Dharmendra Singh (Associate Professor)
Libraries Used: MATLAB 2008a and LabView
Hardware Used: Rhode and Schwarz Vector Network Analyzer.

We used feature extraction techniques, namely, Fourier descriptors, SIFT, moment invariants
and waveform generation on our raw C-scan image to identify the shape of our buried object.
The keypoints of our descriptors were passed through network and compared against standard
shapes, namely, square, rectangle and circle.

II. Jan 2010-June 2010: Sixth Semester Mini Project


VLSI Design Laboratory
Indian Institute of Information Technology, Allahabad

Topic: Designing a low latency Hybrid CORDIC Architecture


Mentor: Dr. Kailash Chandra Ray (Assistant Professor)
Libraries Used: Xilinx ISE simulator, Xilinx 10.1 Accel DSP and MATLAB
Hardware Used: Virtex 5 FPGA

After understanding radix-4 CORDIC algorithm and Double Step Branching CORDIC algorithm
we proposed our own architecture which brought down the computation iterations to n/4 for n bit
precision, thus, making our algorithm faster.

III. July 2009-Dec 2009: Fifth Semester Mini Project


VLSI Design Laboratory
Indian Institute of Information Technology, Allahabad
Topic: Designing a high throughput and low latency CORDIC Processor
Mentor: Dr. Kailash Chandra Ray (Assistant Professor)
Libraries Used: Xilinx ISE simulator, Xilinx 10.1 Accel DSP and MATLAB
Hardware Used: Spartan 3E FPGA

The primary purpose of my project was to understand how to work on FPGA and learning the
basics of Verilog-HDL, followed by understanding the concepts of conventional CORDIC
algorithm and comprehending the challenges associated with it and scale factor computation of
high performance radix-4 CORDIC algorithm.
IV. 12/5/09–19/7/09: Summer Intern
Appin Niche Technologies, Mumbai

Topic: Developing a prototype for automated Railway crossing line


Institute Mentor: Dr. Kailash Chandra Ray (Assistant Professor)
Libraries Used: Keil compiler and flash magic
Hardware Used: 8051 microcontroller, IR proximity sensors, a LCD display and stepper
motor.

The project aims at developing an automated railway crossing which detects the arrival and
departure of train from both the directions and as per the security measures let the drawbridge of
the railway crossing down.

Awards and Achievements:


• Selected in top 2% student in IIT-JEE 2007, IITJEE rank – 5280.
• Selected in AIEEE with an AIR – 1923 and state rank – 120(Maharashtra)
• One of the eight students selected for summer internship at IIT-Roorkee and being
awarded Microsoft scholarship of Rupees 10,000/- for being selected as a summer intern.
• Received the IIIT-Allahabad merit scholarship four times (Ist sem, IInd sem, IVth sem and
VIth sem), which is given only to top three students of ECE department.
• Received consolation prize in Burlesque the Parody mania, organized in IIIT-Allahabad
in the year 2007.

Other Technical Activities:


• Attended a short term course on Embedded Robotics at Appin Niche technologies.
• Attended workshops, eTrix and LogiTrix organized by The Robotics Institute, Thinklabs.
• Made BEAM bots like photovore, obstacle detector, line follower and clap detector out of
discrete electronic components.
• Made autonomous robot using Atmega16 for grid following; line following; and obstacle
detection. The primary purpose of attending this workshop was to implement an
autonomous micromouse using AVR microcontroller.

Personal Information:
Name: Rohit Shukla, Father’s Name: Surendra Nath Shukla, Date of Birth: 18th Oct 1988, Sex:
Male, Language: English, Hindi, Nationality: Indian
Hobbies: Swimming, listening to music, watching movies, travelling and playing PC games.

References available upon request.