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DM74LS08 Quad 2-Input AND Gates

August 1986
Revised March 2000

DM74LS08
Quad 2-Input AND Gates
General Description
This device contains four independent gates each of which
performs the logic AND function.

Ordering Code:
Order Number Package Number Package Description
DM74LS08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram Function Table


Y = AB
Inputs Output
A B Y
L L L
L H L
H L L
H H H
H = HIGH Logic Level
L = LOW Logic Level

2000 Fairchild Semiconductor Corporation DS006347 www.fairchildsemi.com


DM74LS11 Triple 3-Input AND Gate
August 1986
Revised March 2000

DM74LS11
Triple 3-Input AND Gate
General Description
This device contains three independent gates each of
which performs the logic AND function.

Ordering Code:
Order Number Package Number Package Description
DM74LS11M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS11N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram Function Table


Y = ABC
Inputs Output
A B C Y
X X L L
X L X L
L X X L
H H H H
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level

2000 Fairchild Semiconductor Corporation DS006350 www.fairchildsemi.com


SN54/74LS32
QUAD 2-INPUT OR GATE

QUAD 2-INPUT OR GATE


VCC
LOW POWER SCHOTTKY
14 13 12 11 10 9 8

J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1

N SUFFIX
PLASTIC
14 CASE 646-06
1

D SUFFIX
SOIC
14
1 CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

GUARANTEED OPERATING RANGES


Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 55 25 125 C
74 0 25 70
IOH Output Current High 54, 74 0.4 mA
IOL Output Current Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA


5-83
DM7446A, DM5447A/DM7447A BCD to 7-Segment Decoders/Drivers
June 1989

DM7446A, DM5447A/DM7447A
BCD to 7-Segment Decoders/Drivers
General Description
The 46A and 47A feature active-low outputs designed for an overriding blanking input (BI) which can be used to con-
driving common-anode LEDs or incandescent indicators di- trol the lamp intensity (by pulsing) or to inhibit the outputs.
rectly. All of the circuits have full ripple-blanking input/out-
put controls and a lamp test input. Segment identification Features
and resultant displays are shown on a following page. Dis- Y All circuit types feature lamp intensity modulation
play patterns for BCD input counts above nine are unique capability
symbols to authenticate input conditions. Y Open-collector outputs drive indicators directly
All of the circuits incorporate automatic leading and/or trail- Y Lamp-test provision
ing-edge, zero-blanking control (RBI and RBO). Lamp test Y Leading/trailing zero suppression
(LT) of these devices may be performed at any time when
the BI/RBO node is at a high logic level. All types contain

Connection Diagram
Dual-In-Line Package

TL/F/6518 1
Order Number DM5447AJ, DM7446AN or DM7447AN
See NS Package Number J16A or N16E

C1995 National Semiconductor Corporation TL/F/6518 RRD-B30M105/Printed in U. S. A.


DM74LS90 Decade and Binary Counters
August 1986
Revised March 2000

DM74LS90
Decade and Binary Counters
General Description Features
Each of these monolithic counters contains four master- Typical power dissipation 45 mW
slave flip-flops and additional gating to provide a divide-by- Count frequency 42 MHz
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nines complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetri-
cal divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the QD output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.

Ordering Code:
Order Number Package Number Package Description
DM74LS90M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS90N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram Reset/Count Truth Table


Reset Inputs Output
R0(1) R0(2) R9(1) R9(2) QD QC QB QA
H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

2000 Fairchild Semiconductor Corporation DS006381 www.fairchildsemi.com


SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

PRODUCTION DATA information is current as of publication date. Copyright 1988, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1


SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A MARCH 1974 REVISED MARCH 1988

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3