library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity lab1 is

port(

a: in unsigned (3 downto 0);

b: in unsigned (3 downto 0);

s: in unsigned (2 downto 0);

f: out unsigned (3 downto 0);

acar_pres: out std_ulogic;

resul_acarreo: out std_ulogic

);

end lab1;

architecture flujo of lab1 is

signal a1: unsigned (4 downto 0);

signal b1: unsigned (4 downto 0);

signal r: (4 downto 0);

begin

with s select

f <= (a) when "000",

(a+1) when "001",

(a+b) when "010",

(a-b) when "011",

(not a) when "100",

(a and b) when "101",

(a or b) when "110",

(a sll 1) when "111",

a1(4) <= '0'. end process. resul_acarreo <= r. r) begin IF ( a1 (3 downto 0) < b1 (3 downto 0)) THEN r <= (a1-b1). b1. acar_pres <= r(4). resul_acarreo <= r. b1 (3 downto 0) <= b. acar_pres <= r(4) when (s="0000") or (s="0001") else '0'. r <= (a1+b1) when (s="0000") else (a1-b1) when (s="0001") else "00000". "0000" when others. a1 (3 downto 0) <= a. ELSE r <= (a1+b1). acar_pres <= r(4). END IF. . end flujo. b1(4) <= '0'. process (a1.