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# Verilog Operators

Verilog operators operate on several data types to produce an output . Not all Verilog operators
are synthesible means not produce the logic gates. Some operators are similar to those in the C
language Remember, in the most cases we are making gates, not an algorithm.

## Expressions connected by && and || are evaluated from left to right

Evaluation stops as soon as the result is known.
The result is a single bit scalar value:

## x if any of the operands has x (unknown) bit.

Example:

module logical_op();

initial begin

// Logical OR

## \$display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx));

// Logical Negation

## \$display ("! 1'b0 = %b", (! 1'b0));

#10 \$finish;

end

endmodule

Simulation results :

1'b1 || 1'b0 = 1

1'b0 || 1'b0 = 0

1'b0 || 1'bx = x

! 1'b1 =0

! 1'b0 =1

## Bit wise operators :

Bitwise operators perform a bit wise operation on two operands. They take each bit in one
operand and perform the operation with the corresponding bit in the other operand. If one
operand is shorter than the other, it will be extended on the left side with zeroes to match
the length of the longer operand.

## negation (), and(&), or(|), xor(^), xnor(^- , -^)

Perform bit-by-bit operation on two operands (except )
When operands are of unequal bit length, the shorter operand is zero-filled in the
most significant bit positions.
x and z treated the same

Example :

module bitwise_operators();

initial begin

// Bit Wise OR

## \$display (" ~4'bz001 = %b", (~4'bz001));

#10 \$finish;

end

endmodule
Simulation Results :

## 4'b0001 ~^ 4'bz001 = x111

~4'b0001 = 1110

~4'bx001 = x110

~4'bz001 = x110

Reduction Operators:

## and(&), nand(&), or(|), nor(|) xor(^), xnor(^,^)

I Operates on only one operand
Performs a bitwise operation on all bits of the operand \
Returns a 1-bit result I Works from right to left, bit by bit.
Example :

module reduction_operators();

initial begin

## \$display (" ^ 4'b1001 = %b", (^ 4'b1001));

\$display (" ^ 4'bx001 = %b", (^ 4'bx001));

## \$display (" ~^ 4'bz001 = %b", (~^ 4'bz001));

#10 \$finish;

end

endmodule

Simulation Results :

& 4'b1001 = 0

& 4'bx111 = x

& 4'bz111 = x

~& 4'b1001 = 1

~& 4'bx001 = 1

~& 4'bz001 = 1

| 4'b1001 = 1

| 4'bx000 = x

| 4'bz000 = x

~| 4'b1001 = 0
~| 4'bx001 = 0

~| 4'bz001 = 0

^ 4'b1001 = 0

^ 4'bx001 = x

^ 4'bz001 = x

~^ 4'b1001 = 1

~^ 4'bx001 = x

~^ 4'bz001 = x

Shift Operators :

## right shift (>>)

left shift (<>>)
arithmetic left shift (<<<)
arithmetic right shift (>>>) \

## Arithmetic Shift Operators

Arithmetic right shift (>>>) - Shift right specified number of bits, fill with value of
sign bit if expression is signed, othewise fill with zero.

Arithmetic left shift (<<<) - Shift left specified number of bits, filling with zero.
Example :

module shift_operators();

initial begin

// Left Shift

// Right Shift

## \$display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1));

#10 \$finish;

end

endmodule

simulation results:

## 4'b10x1 >> 1 = 010x

4'b10z1 >> 1 = 010z

## It Provides a way to append busses or wires to make busses .

The operands must be sized I Expressed as operands in braces separated by commas
Replication operator is used to replicate a group of bits n times. Say you have a 4 bit
variable and you want to replicate it 4 times to get a 16 bit variable: then we can use the
replication operator.

Example :

module concat_op();

## reg a; Reg[2:0] b,c;

Reg[7:0] x,y,z;

initial begin

a=1b1,b=3b100;c=3b110;

x={a,b,c};

y={a,2b01,a};

z={x[1:0],b[2:1],c};

\$display(x=%b,y=%b,z=%b,

X,y,z);

end

endmodule
Simulation Result:

x= 1_100_110,

y=100_01_1,

z=10_10_110

Conditional Operator ?:

## The conditional expression is first evaluated

If the result is true, true expression is evaluated
If the result is false, false expression is evaluated
If the result is x: both true and false expressions are evaluated,
Their results compared bit by bit,... Returns a value of x if bits differ, OR... the value of
the bits if they are the same. This is an ideal way to model a multiplexer or tri-state
buffer.

Example :

## assign d_out = sel ? d_in1 : d_in0;

endmodule
Simulation results:

## Sel = 0 then d_out = d_in2.

Relational Operators :

greater-than (>)
less-than (=)
less-than-or-equal-to (<=)
Relational operators return logical 1 if expression is true, 0 if false.

Example :

module relational_operators();

initial begin

## \$display (" 1'bz <= 10 = %b", (1'bz <= 10));

#10 \$finish;

end

endmodule

Simulation results:

5 <= 10 = 1
5 >= 10 = 0

1'bx <= 10 = x

1'bz <= 10 = x

Equality operator :

Operands are compared bit by bit, with zero filling if the two
operands do not have the same length

## For the == and != operators, the result is x, if either operand

contains an x or a z

For the === and !== operators, bits with x and z are included
in the comparison and must match for the result to be true

## Note : The result is always 0 or

1.

Equality Operators I logical equality (== ) I logical inequality (!= ) I logical case equality (===) I
logical case inequality (!==)

Equality operators return logical 1 if expression is true, else 0 Operands are compared bit by bit
Zero filling is done if operands are of unequal length (Warning!) Logical case inequality allows
for checking of x and z values Checking for X and Z is most definitely non-synthesible!

## //let a = 4, b = 3, and... //x = 4b1010, y = 4b1101, //z = 4b1xxz, m = 4b1xxz, n = 4b1xxx a

== b //evaluates to logical 0 x != y //evaluates to logical 1 x == z //evaluates to x z === m
//evaluates to logical 1 z === n //evaluates to logical 0 m !== n //evaluates to logical 1
Simulation Results:

Arithematic :

## Integer division truncates any fractional part

The result of a modulus operation takes the sign of the first operand

If any operand bit value is the unknown value x, then the entire result value is x

Register data types are used as unsigned values (Negative numbers are stored in two's
complement form)

Unary operators I Operators + and - can act as unary operators I They indicate the sign of an
operand i.e., -4 // negative four +5 // positive five !!! Negative numbers are represented as 2s
compliment numbers !!! !!! Use negative numbers only as type integer or real !!! !!! Avoid the
use of in expressions !!! !!! These are converted to unsigned 2s compliment numbers !!! !!!
This yields unexpected results in simulation and synthesis !!!

Ex:

## //suppose that: a = 4b0011; // b = 4b0100; // d = 6; e = 4; f = 2; //then, a + b //add a and b;

evaluates to 4b0111 b - a //subtract a from b; evaluates to 4b0001 a * b //multiply a and b;
evaluates to 4b1100 d / e //divide d by e, evaluates to 4b0001. Truncates fractional part e ** f
//raises e to the power f, evaluates to 4b1111 //power operator is most likely not synthesible