c o m
ld .
o r
t u w
jn
Prof. Hai Zhou
w .
Electrical Engineering & Computer Science
w w Northwestern University
1
Logistics
c o m
.
• Instructor: Hai Zhou haizhou@ece.northwestern.edu
ld
• Office: L461
o r
• Office Hours: W 35P
t u w
. jn
• Teaching Assistant: Chuan Lin
w
• Texts:
w w
VLSI Physical Design Automation: Theory & Practice, Sait
& Youssef, World Scientific, 1999.
• Reference:
2
c o m
An Introduction to VLSI Physical Design, Sarrafzadeh &
Wong, McGraw Hill, 1996.
ld .
r
• Grading: Participation10% Project30% Midterm30%
o
Homework30%
t u w
.
late: 40% per day
w jn
• Homework must be turned in before class on each due date,
w w
• Course homepage:
www.ece.northwestern.edu/~haizhou/ece357
2
What can you expect from the course
o m
• Understand modern VLSI design flows (but not the details
c
of tools)
ld .
o r
• Understand the physical design problem
t u w
• Familiar with the stages and basic algorithms in physical
design
w . jn
w
problems
w
• Improve your capability to design algorithms to solve
3
What do I expect from you
c o m
yours
ld .
– speed me up or slow me down if my pace mismatches
o r
– “Your role is not one of sponges, but one of whetstones;
t u w
only then the spark of intellectual excitement can
. jn
continue to jump over”
w
w w
• Read the textbook
• Do your homeworks
– You can discuss homework with your classmates, but
need to write down solutions independently
4
VLSI (Very Large Scale Integrated) chips
c o m
• VLSI chips are everywhere
ld .
– computers
o r
t u w
– commercial electronics: TV sets, DVD, VCR, ...
– automobiles
w . jn
– voice and data communication networks
w w
• VLSI chips are artifacts
– they are produced according to our will ...
5
Design: the most challenging human activity
c o m
.
• Design is a process of creating a structure to fulfill a
ld
requirement
o r
t u w
• Brain power is the scarcest resource
w . jn
– Delegate as much as possible to computers–CAD
w w
– Everything manual: impossible–millions of gates
– Everything computer: impossible either
6
Design is always difficult
o m
A main task of a designer is to manage complexity
c
ld .
r
• Silicon complexity: physical effects no longer be ignored
o
t u w
– resistive and crosscoupled interconnects; signal
integrity; weak and faster gates
. jn
– reliability; manufacturability
w
w w
• System complexity: more functionality in less time
– gap between design and fabrication capabilities
– desire for systemonchip (SOC)
7
CAD: A tale of two designs
c o m
• Target–hardware design
ld .
o r
– How to create a structure on silicon to implement a
function
t u w
. jn
• Aid–software design (programming)
w
w w
– How to create an algorithm to solve a design problem
8
Emphasis of the course
• Design flow
c o m
ld .
– Understand how design process is decomposed into
many stages
o r
u w
– What are the problems need to be solved in each stage
t
• Algorithms
w . jn
w w
– Understand how an algorithm solves a design problem
– Consider the possibility to extend it
9
Basics of MOS Devices
c o m
ld .
• CMOS (Complementary MOS) dominates nMOS and
regularity, etc. o r
pMOS, due to CMOS’s lower power dissipation, high
t u w
jn
• Physical structure of MOS transistors and their schematic
.
icons: nMOS, pMOS.
w
w w
• Layout of basic devices:
– CMOS inverter
– CMOS NAND gate
– CMOS NOR gate
10
MOS Transistors gate
drain source
conductor (polysilicon)
insulator (SiO2)
gate
c o m
n n
drain
ld .
substrate
source
p−substrate
n−transistor
diffusion
o r schematic icon
u w
The nMOS switch passes "0" well.
t
jn
gate
w . drain source
conductor (polysilicon)
insulator (SiO2)
gate
w w p p
drain
substrate
source
n−substrate diffusion
schematic icon
p−transistor
The pMOS switch passes "1" well.
11
A CMOS Inverter
Metal Metal−diffusion contact
A B
VDD pMOS transistor
c o m1 0
ld
nMOS transistor
. 0 1
Polysilicon
o r VDD
A B
t u w p−channel (pMOS)
w . jn
Diffusion
A B
w
GND
w n−channel (nMOS)
GND
layout
12
A CMOS NAND Gate
A B C
VDD
Metal 0
0
c
0 1
o
1 1m
Diffusion
ld
1
1. 0 1
1 0
Polysilicon
w or VDD
tu
C
A
. j n B
A C
w w B
GND
w GND
layout
13
A CMOS NOR Gate
Metal A B C
VDD
0
0
0 1
c o
1 0 m
Polysilicon
ld .
1
1
0 0
1 0
B
w or VDD
tu
A C
w j. n A
C B
GND w w Diffusion
GND
layout
14
Current VLSI design phases
c o m
.
1. High level synthesis (459 VLSI Algorithmics)
ld
r
2. Logic synthesis (459 VLSI Algorithmics)
o
u w
3. Physical design (This course)
t
. jn
• Analysis (implementation → semantics)
w
– Verification (design verification, implementation
w w
verification)
– Analysis (timing, function, noise, etc.)
– Design rule checking, LVS (Layout Vs. Schematic)
15
Physical Design
o m
• Physical design converts a structural description into a
c
geometric description.
ld .
• Physical design cycle:
o r
1. Circuit partitioning
t u w
2. Floorplanning
w . jn
w w
3. placement, and pin assignment
4. Routing (global and detailed)
5. Compaction
16
Design Styles
Issues of
VLSI circuits
c o m
ld .
Performance Area
o r Cost Time−to−market
t u w
w . jn Different design styles
w w
Full custom Standard cell Gate array FPGA CPLD SPLD SSI
17
Full Custom Design Style
c o m
Data path
ld . over−the−cell
or
PLA routing
I/O
ROM/RAM
tu w
n
via
j
Controller (contact)
w .
w w A/D converter
Random logic
18
Standard Cell Design Style
D A B
C
c o m
B B
ld .
r
A
D C
w
D o A
t u
w . jnA B
B
w w Cell A Cell B
library cells
19
Gate Array Design Style
c o m
ld .
I/O pads
pins
o r
t u w
jn
prefabricated customized
transistor
.
wiring
array
w w
w
20
FPGA Design Style
c o m
ld .
o r
t u w
logic
blocks
w . jn routing
tracks
w w
switches
Prefabricated all chip components
21
SSI/SPLD Design Style
x1 y1 x2 y2 x3 y3 x4 y4
m
74LS86 74LS02 74LS00
o
x1 Vcc Vcc Vcc
c
y1 x3
x2
y2
y3
x4
ld .
r
y4
o
GND GND GND
4
F= i=1 xi yi
w
F
(a) 4−bit comparator. (b) SSI implementation.
t u
jn
x1
y1
x2
y2
x3
y3
w . AND array
x1 y1 x2 y2
w w x4
y4
OR array
x3
y3
x4
y4
F
(c) SPLD (PLA) implementation. (d) Gate array implementation.
22
c o m
Comparisons of Design Styles
ld .
Full Standard
o r
Gate
Cell size
Cell type
custom
variable
variable
t
cell
u
fixed height∗
variable warray
fixed
fixed
FPGA
fixed
programmable
SPLD
fixed
programmable
Cell placement
Interconnections
variable
w .
variable
jnin row
variable
fixed
variable
fixed
programmable
fixed
programmable
w
* Uneven height cells are also used.
w
23
Comparisons of Design Styles
c o m
Full
ld
Standard
. Gate
Fabrication time
Packing density
custom
− − −
+++
o r cell
− −
++
array
+
+
FPGA
+++
− −
SPLD
++
− − −
Unit cost in large quantity
Unit cost in small quantity
t u
+++
− − −w ++
− −
+
+
− −
+++
−
+
jn
Easy design and simulation − − − − − − ++ +
Easy design change
.
Accuracy of timing simulation
Chip speed
w
− − −
−
+++
− −
++
−
+
−
−
++
+
−
++
+
−−
+ desirable
− not desirable
w w
24
DesignStyle Tradeoffs
4
10
Full
c o m custom
10
3
ld . semi−
custom
o r
10
2
t u w
jn
Turnaround
Time
(Days)
10
w . SPLD’s
CPLD’s
FPGA’s
w w 1
SSI’s optimal
solution
2 3 4 5 6 7
1 10 10 10 10 10 10 10
25
Algorithms 101
c o m
ld .
• Algorithm: a finite stepbystep procedure to solve a
problem
o r
• Requirements:
t u w
. jn
– Unambiguity: can even be followed by a machine
w
w w
– Basic: each step is among a given primitives
– Finite: it will terminate for every possible input
26
A game
c o m
ld .
• An ECE major is sitting on the Northwestern beach and
r
gets thirsty, she knows that there is an icecream booth
o
t u w
along the shore of Lake Michigan but does not know
where–not even north or south. How can she find the
. jn
booth in the shortest distance?
w
w w
• Primitives: walking a distance, turning around, etc.
27
A first solution
c o m
ld .
• Select a direction, say north, and keep going until find the
booth
o r
t u w
w . jn
• Suppose the booth is to the south, she will never stop... of
w w
course, with the assumption she follows a straight line, not
lake shore or on earth
28
Another solution
o r
t u w
• Search to north 1 yard, if not find, turn to south
w . jn
• Search to south 2 yard, if not find, turn to north
w w
• ... (follow the above pattern in geometric sequence 1, 2, 4,
8, ...)
29
OR
c o m
ld .
• n = −1;
o r
• While (not find) do
t uw
– n = n + 1;
w . jn
– Search to south 2n, and turn;
w w
– Search to north 2n, and turn;
29
Correctness proof
c o m
ld .
• Each time when the while loop is finished, the range from
south 2n to north 2n is searched. Based on the fact that
o r
the booth is at a constant distance x from the origin, it will
t u w
be within a range from south 2N to north 2N for some N .
jn
With n to increment in each loop, we will find the booth in
finite time.
w .
w w
• Is this the fastest (or shortest) way to find the booth?
30
Analysis of algorithm
o
2n−1 < x
t u w
• When the algorithm stops, we should have 2n ≥ x but
w . jn
• The distance traveled is
w w
3 · 2n + 2(2 · 2n−1 + 2 · 2n−2 + · · · + 2) ≤ 7 · 2n
t u w
– Why input size: lower bound (at least read it once)
. jn
• BigOh notation: f (n) = O(g(n)) if there exist constants n0
w
w w
and c such that for all n > n0, f (n) ≤ c · g(n).
– Make our life easy: is it 13x instead of 14x in our game
– The solution is asymptotically optimal for our game
32
Time complexity of an algorithm
c o m
• Runtime comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.
ld .
Time
500
BigOh
O(1)
n = 10
5 × 10−7 sec
o r
n = 100
5 × 10−7 sec
n = 103
5 × 10−7 sec
n = 106
5 × 10−7 sec
3n
n log n
O(n)
O(n log n)
3 × 10−8 sec
t u
3 × 10−8 sec w
3 × 10−7 sec
2 × 10−7 sec
3 × 10−6 sec
3 × 10−6 sec
0.003 sec
0.006 sec
jn
n2 O(n2 ) 1 × 10−7 sec 1 × 10−5 sec 0.001 sec 16.7 min
n3
2n
n!
O(n3 )
O(2n )
O(n!)
w . 1 × 10−6 sec
1 × 10−6 sec
0.003 sec
0.001 sec
3 × 1017 cent.

1 sec


3 × 105 cent.


w w
• Polynomialtime complexity: O(p(n)), where n is the input
size and p(n) is a polynomial function of n.
33
Complexity of a problem
o r
• Lower bound: hard–every algorithm requires more time
t u w
• P: set of problems solvable in polynomial time
w . jn
• NP(Nondeterministic P): set of problems whose solution
w w
can be proved in polynomial time
c o m
ld .
• Cook 1970: If the problem of boolean satisfiability can be
o r
solved in poly. time, so can all problems in NP.
t u w
• Such a problem with this property is called NPhard.
. jn
• If a NPhard problem is in NP, it is called NPcomplete.
w
w w
• Karp 1971: Many other problems resisting poly. solutions
are NPcomplete.
35
How to deal with a hard problem
c o m
poly. time)
ld .
1. The problem is in NP (i.e. solution can be proved in
o r
2. It is NPhard (by polynomial reducing a NPcomplete
problem to it)
t u w
. jn
• Solve NPhard problems:
w
w w
– Exponential algorithm (feasible only when the problem
size is small)
∗ Pseudopolynomial time algorithms
– Restriction: work on a subset of the input space
36
c o m
ld .
– Approximation algorithms: get a provable
closetooptimal solution
o r
u w
– Heuristics: get a as good as possible solution
t
. jn
– Randomized algorithm: get the solution with high
probability
w
w w
36
Algorithmic Paradigms
c o m
solve subproblems, and combine them to construct a
solution.
ld .
o r
– Greedy algorithm: optimal solutions to subproblems will
give optimal solution to the whole problem.
t u w
– Dynamic programming: solutions to a larger problem are
. jn
constructed from a set of solutions to its subproblems.
w
• Mathematical programming: a system of optimizing an
w w
objective function under constraints functions.
w . jn
• Exhaustive search: search the entire solution space.
w w
37