A B C D E

Compal Confidential
1
Model Name : 1

File Name : LA-8671P

2

Compal Confidential 2

TN-Note Schematic Document

2012-10-04
3 3

REV:1A_1004A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
AMY WEN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
Cover Page
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8671P_SDV
Date: Thursday, October 04, 2012 Sheet 1 of 50
A B C D E

A B C D E

Compal Confidential
Model Name : TN-Note
UCPU1 UCPU1 UCPU1 UCPU1
CPU2@ SA00005L5H0 S IC AV8063801058401 SR0N9 L1 1.8G A39! Sub-board
CPU3@ SA00005K6I0 S IC AV8063801058002 SR0N8 L1 1.7G A39!
File Name : Block Diagram CPU4@ SA00005L9F0 S IC AV8063801057801 SR0N7 L1 1.8G A39!

ZZZ
CPU2@
1.8G
SA00005L5H0
CPU3@
1.7G
SA00005K6I0
CPU4@
1.8G
SA00005L9F0
CPU5@
1.9G
SA00005K5E0
CPU5@ SA00005K5E0 S IC AV8063801057605 SR0N6 L1 1.9G A39! 1. PWR Board (LS-8671P)
CPU6@ SA00005UH60 S IC AV8062701313000 SR0U3 J1 1.4G A39!

UCPU1 2. HDD Board (LS-8672P)
DAZ0RP00201
1

U5006 U5009 U5008 U5007 CPU6@
3. P-Sensor1 Board (LS-8673P) 1

1.4G
SA00005UH60
4. P-Sensor2 Board (LS-8674P)
DDR2@ DDR2@ DDR2@ DDR2@
ELIPDA 8G ELIPDA 8G ELIPDA 8G ELIPDA 8G
SA000058U20 SA000058U20 SA000058U20 SA000058U20

UD1 UD2 UD3 UD4 ZZZ1 ZZZ2 ZZZ3

Intel
Ivy Bridge Single Channel
DDR2@
ELIPDA 8G
DDR2@
ELIPDA 8G
DDR2@
ELIPDA 8G
DDR2@
ELIPDA 8G
X76E4G@
ELPIDA_4G
X76H4G@
HYNIX_4G
X76S4G@
SAMSUNG_4G DDR3-1333(1.5V)
DDR3 Chip x8
SA000058U20 SA000058U20 SA000058U20 SA000058U20 X7639839L07 X7639839L08 X7639839L09
BGA P. 10~11
R5049 R267 R1944 R5066 ZZZ4 ZZZ5

P. 04~09
DDR2@ DDR2@ DDR2@ DDR2@ X76E2G@ X76H2G@
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% ELPIDA_2G HYNIX_2G
SD028100280 SD028100280 SD028100280 SD028100280 X7639839L10 X7639839L11
FDI DMI USB 2.0
LVDS USB3.0 USB 3.0 Conn. - L
2 LVDS Conn. P. 23 P. 26 2

HDMI PWR/B
mHDMI Conn. P. 24
DP Intel USB2.0 USB 3.0 Conn. - R ALS (PWR/B Conn.)
mDP Conn. P. 25 P. 27 CM3218
HDA Panther Point P. 37

2-Ch. SPK Conn. P. 28
DMIC Audio Codec PCI-E SATA Sensor Hub Accelerometer & eCompass
ALC3202 SPI STM32F103CBU6TR LSM303DLHCTR
P. 21
P. 28 P. 21
P. 12~20
Combo Jack Conn.P. 29
LPC Gyro
1X BIOS ROM TPM L3GD20TR
P. 21
Card Reader (8M+4M) P. 12 P. 36
Touch Panel (LVDS Conn.)P. 23
RTS5229 P. 22
EC
3
LAN 1X ENE KB9012 3

RTL8111F P. 30
P. 34 Camera & DMIC
DMIC (LVDS Conn.)
P. 23

RJ45 Conn. P. 31 APS Int.KBD
P. 35
LIS34ALTR
P. 33

mini PCI-E (WLAN) 1X
Click Pad
P. 35 (WWAN) mini PCI-E
Half Card Conn.
WLAN & BT
USB(BT) Thermal Sensor Full Card Conn. SIM Conn.
(mSATA)
P. 32 Fintek 75303M
P. 33
Track Point
P. 35
WWAN/mSATA
P. 32
P. 32

HDD BTB Conn. P-Sensor1 Conn.
PCH_GPIO
P. 36
4
HDD/B 4

PCH_GPIO
P-Sensor2 Conn.
AMY WEN P-Sensor2/B (Left) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TN-Note Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8671P_SDV 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 04, 2012 Sheet 2 of 50
A B C D E

A B C D E

Voltage Rails BOARD ID Table
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Board ID PCB Revision
Full ON H H H ON ON ON
0 0.1
1
+5VS
1 0.2 1

S3 (Suspend to RAM) L H H ON ON OFF 2 0.3
Power plane +3VS
+1.8VS S4 (Suspend to Disk) L L H ON OFF OFF
3 0.4
+5VALW +3VM +1.5VS
4 0.5
S5 (Soft OFF) L L L ON OFF OFF 5
+B +3VALW +1.5V +1.05VM +1.05VS
+VCC_GFXCORE_AXG
6
+CPU_CORE
7
State +VCCSA
+0.75VS

S0
O O O O O EC SM Bus1 address EC SM Bus2 address
S3 Device Address HEX Device Address HEX
O O O O X Smart Battery 0001-011xb 16H Thermal sensor 1001-101x b 9AH
M3 Charger 0001-0010b 12H PCH (SML1DATA / GPIO75) 1001-0110 b 96H
O O O O X
2 2

S4/S5 - AC O O X X X
S4/S5 - BATT ONLY
SM Bus Controller
O X X X X Device Address HEX
S4/S5 - NO AC & BATT Security Rom 1010-100x b A8 H
X X X X X DDR DIMM0 1010-000x b A0 H

USB3.0 USB2.0 NOTE
BOM Structure
1 0
SDV FVT SIT SVT SOVP SM Bus Controller 0 2 1* USB3.0/2.0 Conn
Device Address HEX
@ : No Stuff No-use No-use No-use
3 2 USB3.0/2.0 Conn

3
4 3 3
ME@ : ME components
4 Sensor Hub
CPUx@ : CPU SKU V V V V V Sensor HUB 5 USB Camera

DDRx@ : RAM SKU V V V V V Device Address HEX 6 X
ALS 0100-100x b 48h
7 X
SBA@ : SBA APS 0011-001x b 32h
V V V V V
Gyroscope 0110-101xb 6Ah 8 Touch Panel
NOSBA@ : NO SBA e-Compass 0011-110x b 3Ch
9* WWAN

ID4@ : Intel Deep S4 V 10 WLAN

11 Finger Printer**
AOAC@ : AOAC V V V V V
12
TPM@ : TPM V V V V 13 Bluetooth**

4 4
Short@ : 0ohm short pad * Debug Port
** Not Use

Security Classification Compal Secret Data Compal Electronics, Inc.
AMY WEN Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8671P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 04, 2012 Sheet 3 of 50
A B C D E

A B C D E

+1.05VS

PEG_ICOMPI and RCOMPO signals should be shorted and routed

1
with - max length = 500 mils - typical impedance = 43 mohms
1 R6 1
PEG_ICOMPO signals should be routed with - max length = 500 mils
24.9_0402_1% UCPU1I
- typical impedance = 14.5 mohms

2
UCPU1A
G3 PEG_COMP BG17 M4
PEG_ICOMPI G1 BG21 VSS[181] VSS[250] M58
M2 PEG_ICOMPO G4 BG24 VSS[182] VSS[251] M6
[14] DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO VSS[183] VSS[252]
[14] DMI_CRX_PTX_N1 P6 BG28 N1
P1 DMI_RX#[1] BG37 VSS[184] VSS[253] N17
[14] DMI_CRX_PTX_N2 DMI_RX#[2] VSS[185] VSS[254]
[14] DMI_CRX_PTX_N3 P10 H22 BG41 N21
DMI_RX#[3] PEG_RX#[0] J21 BG45 VSS[186] VSS[255] N25
N3 PEG_RX#[1] B22 BG49 VSS[187] VSS[256] N28
[14] DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] VSS[188] VSS[257]
[14] DMI_CRX_PTX_P1 P7 D21 PEG Static Lane Reversal - CFG2 is for the 16x BG53 N33
DMI_RX[1] PEG_RX#[3] VSS[189] VSS[258]

DMI
[14] DMI_CRX_PTX_P2 P3 A19 BG9 N36
P11 DMI_RX[2] PEG_RX#[4] D17 C29 VSS[190] VSS[259] N40
[14] DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] VSS[191] VSS[260]
B14 1: Normal Operation; Lane # definition matches C35 N43
[14]
[14]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
K1
M8 DMI_TX#[0]
DMI_TX#[1]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
D13
A11
CFG2 * socket pin map definition C40
D10
VSS[192]
VSS[193]
VSS[194]
VSS[261]
VSS[262]
VSS[263]
N47
N48
N4 B10 D14 N51
[14] DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS[195] VSS[264]
R2 G8 0:Lane Reversed D18 N52
[14] DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] VSS[196] VSS[265]
A8 D22 N56
K3 PEG_RX#[11] B6 D26 VSS[197] VSS[266] N61
[14] DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] VSS[198] VSS[267]
M7 H8 D29 P14
[14] DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS[199] VSS[268]
P4 E5 D35 P16
[14] DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] VSS[200] VSS[269]
T3 K7 D4 P18
[14] DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS[201] VSS[270]
D40 P21
K22 D43 VSS[202] VSS[271] P58
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
K19
C21
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
FDI_CTX_PRX_N0 U7 D19 D54 R17
[14] FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] VSS[206] VSS[275]
FDI_CTX_PRX_N1 W11 C19 D58 R20
2 [14] FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] VSS[207] VSS[276] 2
FDI_CTX_PRX_N2 W1 D16 D6 R4
[14] FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS[208] VSS[277]
FDI_CTX_PRX_N3 AA6 C13 E25 R46
[14] FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS[209] VSS[278]
FDI_CTX_PRX_N4 W6 D12 E29 T1
[14] FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7] VSS[210] VSS[279]
FDI_CTX_PRX_N5 V4 C11 E3 T47
PCI EXPRESS -- GRAPHICS

[14] FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] VSS[211] VSS[280]
FDI_CTX_PRX_N6 Y2 C9 E35 T50
[14] FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] VSS[212] VSS[281]
FDI_CTX_PRX_N7 AC9 F8 E40 T51
[14] FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] VSS[213] VSS[282]
Intel(R) FDI

C8 F13 T52
PEG_RX[11] C5 F15 VSS[214] VSS[283] T53
FDI_CTX_PRX_P0 U6 PEG_RX[12] H6 F19 VSS[215] VSS[284] T55
[14] FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS[216] VSS[285]
FDI_CTX_PRX_P1 W10 F6 F29 T56
[14] FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] VSS[217] VSS[286]
FDI_CTX_PRX_P2 W3 K6 F35 U13
[14] FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS[218] VSS[287]
FDI_CTX_PRX_P3 AA7 F40 U8
[14] FDI_CTX_PRX_P3 FDI0_TX[3] VSS[219] VSS[288]
FDI_CTX_PRX_P4 W7 G22 F55 V20
[14] FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] VSS[220] VSS[289]
FDI_CTX_PRX_P5 T4 C23 G51 V61
[14] FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] VSS[221] VSS[290]
FDI_CTX_PRX_P6 AA3 D23 G6 W13
[14] FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] VSS[222] VSS[291]
FDI_CTX_PRX_P7 AC8 F21 G61 W15
[14] FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] VSS[223] VSS[292]
H19 H10 W18
FDI_FSYNC0 AA11 PEG_TX#[4] C17 H14 VSS[224] VSS[293] W21
[14] FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] VSS[225] VSS[294]
[14] FDI_FSYNC1 FDI_FSYNC1 AC12 K15 H17 W46
FDI1_FSYNC PEG_TX#[6] F17 H21 VSS[226] VSS[295] W8
FDI_INT U11 PEG_TX#[7] F14 H4 VSS[227] VSS[296] Y4
[14] FDI_INT FDI_INT PEG_TX#[8] VSS[228] VSS[297]
A15 H53 Y47
FDI_LSYNC0 AA10 PEG_TX#[9] J14 H58 VSS[229] VSS[298] Y58
[14] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] VSS[230] VSS[299]
[14] FDI_LSYNC1 FDI_LSYNC1 AG8 H13 J1 Y59
FDI1_LSYNC PEG_TX#[11] M10 J49 VSS[231] VSS[300] G48
PEG_TX#[12] F10 J55 VSS[232] VSS[301]
+1.05VS PEG_TX#[13] D9 K11 VSS[233]
PEG_TX#[14] J4 K21 VSS[234]
1 2 +EDP_COM AF3 PEG_TX#[15] K51 VSS[235]
R7 24.9_0402_1% AD2 eDP_COMPIO F22 K8 VSS[236] A5 T90 PAD @
AG11 eDP_ICOMPO PEG_TX[0] A23 L16 VSS[237] VSS_NCTF_1 A57 T91 PAD @
eDP_HPD# PEG_TX[1] D24 L20 VSS[238] VSS_NCTF_2 BC61
3 PEG_TX[2] E21 L22 VSS[239] VSS_NCTF_3 BD3 3
AG4 PEG_TX[3] G19 L26 VSS[240] VSS_NCTF_4 BD59
AF4 eDP_AUX# PEG_TX[4] B18 L30 VSS[241] VSS_NCTF_5 BE4

NCTF
eDP_AUX PEG_TX[5] K17 L34 VSS[242] VSS_NCTF_6 BE58
PEG_TX[6] VSS[243] VSS_NCTF_7
eDP

G17 L38 BG5 T95 PAD @
AC3 PEG_TX[7] E14 L43 VSS[244] VSS_NCTF_8 BG57 T96 PAD @
AC4 eDP_TX#[0] PEG_TX[8] C15 L48 VSS[245] VSS_NCTF_9 C3 T97 PAD @
AE11 eDP_TX#[1] PEG_TX[9] K13 L61 VSS[246] VSS_NCTF_10 C58
AE7 eDP_TX#[2] PEG_TX[10] G13 M11 VSS[247] VSS_NCTF_11 D59
eDP_TX#[3] PEG_TX[11] K10 M15 VSS[248] VSS_NCTF_12 E1 T103PAD @
AC1 PEG_TX[12] G10 VSS[249] VSS_NCTF_13 E61 T98 PAD @
AA4 eDP_TX[0] PEG_TX[13] D8 VSS_NCTF_14
AE10 eDP_TX[1] PEG_TX[14] K4
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]

IVY-BRIDGE_BGA1023 IVY-BRIDGE_BGA1023
CPU1@ CPU1@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-8671P_SDV
AMY WEN A B C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D
Date: Thursday, October 04, 2012
E
Sheet 4 of 50

5 4 3 2 1

UCPU1B

J3 CLK_CPU_DMI_R 33_0402_5% R8 1 2
BCLK H2 CLK_CPU_DMI [13]
PROC_DETECT (Processor Detect): pulled to CLK_CPU_DMI#_R 33_0402_5% R12 1 2
BCLK# CLK_CPU_DMI# [13]

MISC
ground on the processor package. There is no

CLOCKS
D D
connection to the processor silicon for this F49
signal. System board designers may use this [17] H_SNB_IVB# PROC_SELECT# AG3 2 1 1K_0402_5%
R9
signal to determine if the processor is DPLL_REF_CLK AG1 R10 2 1 1K_0402_5%
present DPLL_REF_CLK# +1.05VS
2 1 C57
R11 @ 10K_0402_5% PROC_DETECT#
+1.05VS

PAD~D T1 @ H_CATERR# C49
CATERR#

2

THERMAL
R13
62_0402_5% A48 AT30 H_DRAMRST#
[17,34] H_PECI PECI SM_DRAMRST# H_DRAMRST# [6]

1

1
R15 BF44 SM_RCOMP0 140_0402_1% 1 2 R16 @ C82
SM_RCOMP[0]

DDR3
MISC
[34] H_PROCHOT#
1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 25.5_0402_1%1 2 R17
56_0402_5% PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP2 200_0402_1% 1 2 R18 100P_0402_50V8J
SM_RCOMP[2] 2
DDR3 Compensation Signals
H_THERMTRIP# D45
[17] H_THERMTRIP# THERMTRIP#
PU/PD for JTAG signals +1.05VS
N53 XDP_PRDY#
PRDY# N55 XDP_PREQ#
PREQ# ESD XDP_TMS R20 2 1 51_0402_5%
TCK
L56
L55
XDP_TCK
XDP_TMS
C Reserve XDP_TDI
XDP_TDO
R21 2
2
1 51_0402_5%
1 51_0402_5%
R22
TMS

PWR MANAGEMENT
J58 XDP_TRST#
TRST# +3VS XDP_TCK R24 2 1 51_0402_5%

JTAG & BPM
[14] H_PM_SYNC
C48 M60 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
PM_SYNC TDI

1
L59 XDP_TDO
R14 TDO R27
0_0402_5% 1K_0402_5%
[17] H_CPUPWRGD
1 2 H_CPUPWRGD_R B46
C short@ UNCOREPWRGOOD K58 XDP_DBRESET# C
XDP_DBRESET# [12,14]

2
DBR#
2

1 R29
C5236 R28 1 2 VDDPWRGOOD_R BE45 G58 XDP_BPM#0
@ 130_0402_1% SM_DRAMPWROK BPM#[0] E55 XDP_BPM#1
10K_0402_5% BPM#[1]
100P_0402_50V8J E59 XDP_BPM#2 JDB1
2 BPM#[2] G55 XDP_BPM#3 XDP_PREQ# 1
1

BPM#[3] G59 XDP_BPM#4 XDP_PRDY# 2 1
BUF_CPU_RST# D44 BPM#[4] H60 XDP_BPM#5 3 2
RESET# BPM#[5] J59 XDP_BPM#6 4 3
BPM#[6] J61 XDP_BPM#7 5 4
BPM#[7] 6 5
ESD 7 6
7
C Reserve 8
9 8
H_CPUPWRGD R52 1 @ 2 1K_0402_1% 10 9
R531 1 @ 2 0_0402_5% 11 10
[12,14,34] PBTN_OUT# 1 @ 2 12 11
IVY-BRIDGE_BGA1023 R54 1K_0402_1%
+1.05VS [7] XDP_CFG0 12
CPU1@ R397 1 @ 2 0_0402_5% 13
[14] SYS_PWROK @ 13
[13] CLK_XDP_CLK R389 1 2 0_0402_5% CLK_XDP_CLK_R 14
R400 1 @ 2 0_0402_5% CLK_XDP_CLK#_R 15 14
[13] CLK_XDP_CLK# 15
+1.05VS 16
PCH_PLTRST# R55 1 @ 2 1K_0402_1% 17 16
XDP_DBRESET# 18 17
19 18
XDP_TDO 20 19
20

1
+3VALW C5237 XDP_TRST# 21
Buffered reset to CPU 0.1U_0402_16V4Z XDP_TDI 22 21
@ XDP_TMS 23 22

2
@ +1.5V_CPU_VDDQ 24 23
24
1

C33 +3VS 25
25
1

0.1U_0402_16V4Z XDP_TCK 26
R30 27 26
2

+3VS 200_0402_5% 28 G1
@ U1 +1.05VS ESD G2

1
B R31 @ C34 R532, ACES_88717-2601 B
2
5

10K_0402_5% 0.1U_0402_16V4Z ME@
C39 Reserve
1

1 2 1
P

2
B 4PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
[14] PM_DRAM_PWRGD A
G

1

5
74AHC1G09GW_TSSOP5 R34 U3
3

2

43_0402_5% 1

P
@ R33 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
39_0402_5% Y 2PCH_PLTRST#
A PCH_PLTRST# [16,36]

G
1 2 SN74LVC1G07DCKR_SC70-5
1 2

1

R532 0_0402_5% C38

3
0.1U_0402_16V4Z
D @
2

[9] RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3# 2
G
Q4 S
2N7002K_SOT23-3
3

@

A A

AMY WEN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/6) PM,XDP,CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8671P_SDV
Date: Thursday, October 04, 2012 Sheet 5 of 50
5 4 3 2 1

2 Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.11] SB_DQ[58] DDR_A_D61 AN52 BG35 DDR_A_MA0 AG59 DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 AM60 SB_DQ[59] DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 AL59 SB_DQ[60] BF32 SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 AF61 SB_DQ[61] SB_MA[0] BE33 SA_MA[3] AT34 DDR_A_MA4 AH60 SB_DQ[62] SB_MA[1] BD33 SA_MA[4] AU34 DDR_A_MA5 SB_DQ[63] SB_MA[2] AU30 SA_MA[5] BB32 DDR_A_MA6 SB_MA[3] BD30 B B BD37 SA_MA[6] AT32 DDR_A_MA7 SB_MA[4] AV30 [10.63] UCPU1D DDR_A_D0 AG6 DDR_A_D1 AJ6 SA_DQ[0] AU36 M_CLK_DDR0 SA_DQ[1] SA_CK[0] M_CLK_DDR0 [10] DDR_A_D2 AP11 AV36 M_CLK_DDR#0 AL4 SA_DQ[2] SA_CK#[0] M_CLK_DDR#0 [10] SB_DQ[0] DDR_A_D3 AL6 AY26 DDR_CKE0_DIMMA AL1 BA34 SA_DQ[3] SA_CKE[0] DDR_CKE0_DIMMA [10] SB_DQ[1] SB_CK[0] DDR_A_D4 AJ10 AN3 AY34 DDR_A_D5 AJ8 SA_DQ[4] AR4 SB_DQ[2] SB_CK#[0] AR22 DDR_A_D6 AL8 SA_DQ[5] AK4 SB_DQ[3] SB_CKE[0] DDR_A_D7 AL7 SA_DQ[6] AK3 SB_DQ[4] DDR_A_D8 AR11 SA_DQ[7] AN4 SB_DQ[5] DDR_A_D9 AP6 SA_DQ[8] AT40 M_CLK_DDR1 AR1 SB_DQ[6] SA_DQ[9] SA_CK[1] M_CLK_DDR1 [10.11] SB_DQ[42] DDR_A_D45 AU49 AJ11 DDR_A_DQS0 AY60 DDR_A_D46 BA53 SA_DQ[45] SA_DQS[0] AR10 DDR_A_DQS1 BE54 SB_DQ[43] DDR_A_D47 BB55 SA_DQ[46] SA_DQS[1] AY11 DDR_A_DQS2 BG54 SB_DQ[44] DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 BA58 SB_DQ[45] AM2 DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 AW59 SB_DQ[46] SB_DQS[0] AV1 DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 AW58 SB_DQ[47] SB_DQS[1] BE11 DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 AU58 SB_DQ[48] SB_DQS[2] BD18 DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 AN61 SB_DQ[49] SB_DQS[3] BE51 DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] AN59 SB_DQ[50] SB_DQS[4] BA61 DDR_A_D54 AP56 SA_DQ[53] AU59 SB_DQ[51] SB_DQS[5] AR59 DDR_A_D55 AP52 SA_DQ[54] AU61 SB_DQ[52] SB_DQS[6] AK61 DDR_A_D56 AN57 SA_DQ[55] AN58 SB_DQ[53] SB_DQS[7] DDR_A_D57 AN53 SA_DQ[56] AR58 SB_DQ[54] DDR_A_D58 AG56 SA_DQ[57] AK58 SB_DQ[55] DDR_A_D59 AG53 SA_DQ[58] AL58 SB_DQ[56] DDR_A_D60 AN55 SA_DQ[59] AG58 SB_DQ[57] SA_DQ[60] DDR_A_MA[0.11] DDR_A_CAS# SA_CAS# SA_MA[13] SB_MA[11] BD39 AY28 DDR_A_MA14 AV28 [10.047U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics.11] DDR_A_BS2 SA_BS[2] SA_MA[9] SB_BS[0] SB_MA[7] BE37 DDR_A_MA10 BD42 BE30 SA_MA[10] BA30 DDR_A_MA11 AT22 SB_BS[1] SB_MA[8] BE28 SA_MA[11] BC30 DDR_A_MA12 SB_BS[2] SB_MA[9] BD43 BE39 SA_MA[12] AW41 DDR_A_MA13 SB_MA[10] AT28 [10. AND CONTAINS CONFIDENTIAL PROCESSOR(3/6) DDRIII Size Document Number Rev AND TRADE SECRET INFORMATION.11] SB_DQ[7] DDR_A_D10 AU6 AU40 M_CLK_DDR#1 AU4 SA_DQ[10] SA_CK#[1] M_CLK_DDR#1 [10. INC..11] SB_DQ[8] DDR_A_D11 AV9 BB26 DDR_CKE1_DIMMA AT2 BA36 SA_DQ[11] SA_CKE[1] DDR_CKE1_DIMMA [10.11] 2 Q5 R39 BSS138_NL_SOT23-3 G 2 4.11] DDR_A_RAS# SA_RAS# SA_MA[14] SB_MA[12] AT41 AU26 DDR_A_MA15 AV43 BD46 [10. Inc.11] SB_DQ[9] SB_CK[1] DDR_A_D12 AR6 AV4 BB36 DDR_A_D13 AP8 SA_DQ[12] BA4 SB_DQ[10] SB_CK#[1] BF27 DDR_A_D14 AT13 SA_DQ[13] AU3 SB_DQ[11] SB_CKE[1] DDR_A_D15 AU13 SA_DQ[14] AR3 SB_DQ[12] DDR_A_D16 BC7 SA_DQ[15] AY2 SB_DQ[13] DDR_A_D17 BB7 SA_DQ[16] BB40 DDR_CS0_DIMMA# BA3 SB_DQ[14] SA_DQ[17] SA_CS#[0] DDR_CS0_DIMMA# [10] SB_DQ[15] DDR_A_D18 BA13 BC41 DDR_CS1_DIMMA# BE9 SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# [10.11] SB_DQ[16] DDR_A_D19 BB11 BD9 BE41 DDR_A_D20 BA7 SA_DQ[19] BD13 SB_DQ[17] SB_CS#[0] BE47 DDR_A_D21 BA9 SA_DQ[20] BF12 SB_DQ[18] SB_CS#[1] DDR_A_D22 BB9 SA_DQ[21] BF8 SB_DQ[19] DDR_A_D23 AY13 SA_DQ[22] BD10 SB_DQ[20] DDR_A_D24 AV14 SA_DQ[23] AY40 M_ODT0 BD14 SB_DQ[21] SA_DQ[24] SA_ODT[0] M_ODT0 [10] SB_DQ[22] DDR_A_D25 AR14 BA41 M_ODT1 BE13 SA_DQ[25] SA_ODT[1] M_ODT1 [10.5V CPU1@ @ R36 1 0_0402_5% 1 2 R37 1K_0402_5% R38 2 1K_0402_5% S D [5] H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# [10.. October 04. LA-8671P_SDV Date: Thursday.11] DDR_A_BS1 SA_BS[1] SA_MA[8] SB_MA[6] BA28 AV32 DDR_A_MA9 BG39 BD29 [10.11] DDR_A_BS0 SA_BS[0] SA_MA[7] SB_MA[5] BF36 AY32 DDR_A_MA8 BG30 [10.11] DDR_A_D[0. 5 4 3 2 1 UCPU1C D D [10..11] SB_DQ[28] DDR_A_D31 BB17 AL11 DDR_A_DQS#0 BG14 DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 BG18 SB_DQ[29] C DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 BF19 SB_DQ[30] AL3 C DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 BD50 SB_DQ[31] SB_DQS#[0] AV3 DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 BF48 SB_DQ[32] SB_DQS#[1] BG11 DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 BD53 SB_DQ[33] SB_DQS#[2] BD17 DDR_A_D37 AR45 SA_DQ[36] SA_DQS#[5] AT55 DDR_A_DQS#6 BF52 SB_DQ[34] SB_DQS#[3] BG51 SA_DQ[37] SA_DQS#[6] SB_DQ[35] SB_DQS#[4] DDR SYSTEM MEMORY A DDR_A_D38 AT48 AK55 DDR_A_DQS#7 BD49 BA59 DDR_A_D39 AY48 SA_DQ[38] SA_DQS#[7] BE49 SB_DQ[36] SB_DQS#[5] AT60 SA_DQ[39] SB_DQ[37] SB_DQS#[6] DDR SYSTEM MEMORY B DDR_A_D40 BA49 BD54 AK59 DDR_A_D41 AV49 SA_DQ[40] BE53 SB_DQ[38] SB_DQS#[7] DDR_A_D42 BB51 SA_DQ[41] BF56 SB_DQ[39] DDR_A_D43 AY53 SA_DQ[42] BE57 SB_DQ[40] DDR_A_D44 BB49 SA_DQ[43] BC59 SB_DQ[41] SA_DQ[44] DDR_A_DQS[0. 2012 Sheet 6 of 50 5 4 3 2 1 .11] DDR_A_WE# SA_WE# SA_MA[15] SB_CAS# SB_MA[13] BF40 AT26 BD45 SB_RAS# SB_MA[14] AU22 SB_WE# SB_MA[15] IVY-BRIDGE_BGA1023 CPU1@ IVY-BRIDGE_BGA1023 +1. INC. INC..7] [10.99K_0402_1% 1 A A [13.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.15] [10.7] [10. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.11] SB_DQ[23] DDR_A_D26 AY17 BF16 AT43 DDR_A_D27 AR19 SA_DQ[26] BE17 SB_DQ[24] SB_ODT[0] BG47 DDR_A_D28 BA14 SA_DQ[27] BE18 SB_DQ[25] SB_ODT[1] DDR_A_D29 AU14 SA_DQ[28] BE21 SB_DQ[26] DDR_A_D30 BB14 SA_DQ[29] BE14 SB_DQ[27] SA_DQ[30] DDR_A_DQS#[0.9] DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 1 AMY WEN C35 0. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.

AND CONTAINS CONFIDENTIAL PROCESSOR(4/6) RSVD.9_0402_1% AY22 RSVD14 DC_TEST_C61 D61 AU19 RSVD15 DC_TEST_D61 BD61 CFG6 AU21 RSVD16 DC_TEST_BD61 BE61 BD21 RSVD17 DC_TEST_BE61 BE59 CFG5 BD22 RSVD18 DC_TEST_BE59 BG61 RSVD19 DC_TEST_BG61 1 1 BD25 BG59 BD26 RSVD20 DC_TEST_BG59 BG58 @ R49 @ R50 BG22 RSVD21 DC_TEST_BG58 BG4 1K_0402_1%~D 1K_0402_1%~D BE22 RSVD22 DC_TEST_BG4 BG3 BG26 RSVD23 DC_TEST_BG3 BE3 2 2 BE26 RSVD24 DC_TEST_BE3 BG1 BF23 RSVD25 DC_TEST_BG1 BE1 BE24 RSVD26 DC_TEST_BE1 BD1 RSVD27 DC_TEST_BD1 IVY-BRIDGE_BGA1023 CPU1@ PCIE Port Bifurcation Straps * 11: (Default) x16 .CFG2 is for the 16x A55 H51 CFG[8] K49 CFG[9] M13 K53 CFG[10] RSVD34 M14 CFG2 * 1:(Default) Normal Operation. INC.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. function 2 enabled) 00: x8. An external Display Port device is @ BB21 A59 BB19 RSVD11 DC_TEST_A59 C59 connected to the Embedded Display Port 1 2 R46 1 AY21 RSVD12 DC_TEST_C59 A61 BA22 RSVD13 DC_TEST_A61 C61 49.Device 1 functions 1 and 2 enabled CFG7 1 @ R51 1K_0402_1%~D 2 PEG DEFER TRAINING CFG7 * 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A A AMY WEN Security Classification Compal Secret Data Compal Electronics. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.x4. 2012 Sheet 7 of 50 5 4 3 2 1 . Inc. Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. Lane # +CPU_CORE R43 F53 CFG[11] RSVD35 U14 definition matches socket pin map 49. October 04.9_0402_1% G53 CFG[12] RSVD36 W14 definition 2 1 L51 CFG[13] RSVD37 P13 CFG[14] RSVD38 0:Lane Reversed F51 CFG[15] 2 D52 R91 L53 CFG[16] AT49 CFG4 100_0402_1%~D CFG[17] RSVD39 K24 RSVD40 @ 1 VCC_VAL_SENSE H43 RESERVED 1 2 R44 1 VSS_VAL_SENSE K43 VCC_VAL_SENSE AH2 @ R42 VSS_VAL_SENSE RSVD41 AG13 1K_0402_1%~D 49. x8 . INC. No Physical Display Port DC_TEST_C4 attached to Embedded Display Port 2 BA19 D3 R89 AV19 RSVD8 DC_TEST_D3 D1 AT21 RSVD9 DC_TEST_D1 A58 100_0402_1%~D RSVD10 DC_TEST_A58 0 : Enabled.(Device 1 function 1 disabled . INC.x4 . 5 4 3 2 1 CFG Straps for Processor CFG2 UCPU1E 1 D D @ R41 1K_0402_1%~D XDP_CFG0 B50 N59 [5] XDP_CFG0 CFG[0] BCLK_ITP C51 N58 2 CFG2 B54 CFG[1] BCLK_ITP# D53 CFG[2] CFG4 A51 CFG[3] N42 CFG5 C53 CFG[4] RSVD30 L42 CFG6 C55 CFG[5] RSVD31 L45 CFG7 H49 CFG[6] RSVD32 L47 CFG[7] RSVD33 PEG Static Lane Reversal . function 2 B B disabled 01: Reserved .9_0402_1% RSVD7 A4 DC_TEST_A4 C4 CFG4 * 1 : Disabled.CFG Size Document Number Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.Device 1 function 1 enabled .Device 1 functions 1 and 2 disabled CFG[6:5] 10: x8.9_0402_1% RSVD42 AM14 VCC_AXG_VAL_SENSE H45 RSVD43 AM15 2 VSS_AXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44 VSSAXG_VAL_SENSE N50 T20 @ F48 RSVD45 PAD~D VCC_DIE_SENSE +VCC_GFXCORE_AXG Display Port Presence Strap H48 C R45 K48 RSVD6 C 2 1 49. LA-8671P_SDV Date: Thursday.

5 4 3 2 1 UCPU1F POWER +1. Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.05 C27 C32 VCC[9] VCC[10] VCCIO[13] VCCIO[14] AL15 AL16 C34 VCC[11] VCCIO[15] AL20 C37 VCC[12] VCCIO[16] AL22 C39 VCC[13] VCCIO[17] AL26 VGA_CORE C42 VCC[14] VCC[15] VCCIO[18] VCCIO[19] AL45 D27 AL48 D32 VCC[16] VCCIO[20] AM16 All Capacitor place on Power side.BYPASS Size Document Number Rev AND TRADE SECRET INFORMATION.05VS L40 VCC[71] +1. LA-8671P_SDV Date: Thursday. 2012 Sheet 8 of 50 5 4 3 2 1 . INC. AND CONTAINS CONFIDENTIAL PROCESSOR(5/6) PWR.05VS B B N26 VCC[72] N30 VCC[73] AM25 QUIET RAILS N34 VCC[74] VCCPQE[1] AN22 N38 VCC[75] VCCPQE[2] VCC[76] 1 1 1 2 C106 R56 R57 Place the PU 1U_0402_6.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1. D34 VCC[17] VCC[18] VCCIO[21] VCCIO[22] AM17 D37 AM21 D39 VCC[19] VCCIO[23] AM43 PEG IO AND DDR IO D42 VCC[20] VCCIO[24] AM47 E26 VCC[21] VCCIO[25] AN20 E28 VCC[22] VCCIO[26] AN42 E32 VCC[23] VCCIO[27] AN45 E34 VCC[24] VCCIO[28] AN48 E37 VCC[25] VCCIO[29] E38 VCC[26] VCC[27] CORE SUPPLY F25 F26 VCC[28] F28 VCC[29] F32 VCC[30] F34 VCC[31] F37 VCC[32] AA14 F38 VCC[33] VCCIO[30] AA15 F42 VCC[34] VCCIO[31] AB17 G42 VCC[35] VCCIO[32] AB20 C H25 VCC[36] VCCIO[33] AC13 C H26 VCC[37] VCCIO[34] AD16 H28 VCC[38] VCCIO[35] AD18 H29 VCC[39] VCCIO[36] AD21 H32 VCC[40] VCCIO[37] AE14 H34 VCC[41] VCCIO[38] AE15 H35 VCC[42] VCCIO[39] AF16 H37 VCC[43] VCCIO[40] AF18 H38 VCC[44] VCCIO[41] AF20 H40 VCC[45] VCCIO[42] AG15 J25 VCC[46] VCCIO[43] AG16 J26 VCC[47] VCCIO[44] AG17 J28 VCC[48] VCCIO[45] AG20 J29 VCC[49] VCCIO[46] AG21 J32 VCC[50] VCCIO[47] AJ14 J34 VCC[51] VCCIO[48] AJ15 Chief river VCCIO_SEL pull-H J35 VCC[52] VCCIO[49] J37 VCC[53] J38 VCC[54] J40 VCC[55] +1.3V6K 75_0402_5% 130_0402_1%~D resistors R58 close to CPU 2 2 43_0402_5% A44 H_CPU_SVIDALRT# 1 2 VIDALERT# VR_SVID_ALRT# [47] B43 H_CPU_SVIDCLK R59 2 1 0_0402_5% VIDSCLK VR_SVID_CLK [47] SVID C44 H_CPU_SVIDDAT R60 2 short@ 1 0_0402_5% VIDSOUT short@ VR_SVID_DAT [47] +CPU_CORE 1 Place the PU 1 R79 2 R61 100_0402_1%~D resistors 100_0402_1%~D close to CPU @ 2 F43 VCCSENSE_R R62 2 1 0_0402_5% VCC_SENSE VCCSENSE [47] SENSE LINES G43 VSSSENSE_R R63 2 short@ 1 0_0402_5% VSS_SENSE short@ VSSSENSE [47] 1 2 +1. INC. INC.05VS 1 R617 10_0402_1% R64 Place the PU AN16 100_0402_1%~D VCCIO_SENSE AN17 VCCIO_SENSE [46] resistors VSS_SENSE_VCCIO VSS_SENSE_VCCIO [46] close to VR 2 VSS_SENSE_VCCIO 1 2 A A R618 10_0402_1% IVY-BRIDGE_BGA1023 CPU1@ AMY WEN Security Classification Compal Secret Data Compal Electronics. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.05VS +CPU_CORE AF46 VCCIO[1] AG48 VCCIO[3] AG50 A26 VCCIO[4] AG51 D A29 VCC[1] VCCIO[5] AJ17 D A31 VCC[2] VCCIO[6] AJ21 A34 VCC[3] VCCIO[7] AJ25 A35 VCC[4] VCCIO[8] AJ43 CPU_CORE A38 VCC[5] VCC[6] VCCIO[9] VCCIO[10] AJ47 A39 AK50 GFX_CORE A42 C26 VCC[7] VCC[8] VCCIO[11] VCCIO[12] AK51 AL14 VCCP1. October 04.05VS +3VS J42 VCC[56] K26 VCC[57] W16 VCC[58] VCCIO50 1 K27 W17 K29 VCC[59] VCCIO51 R5157 K32 VCC[60] 10K_0402_5% K34 VCC[61] K35 VCC[62] 2 K37 VCC[63] K39 VCC[64] K42 VCC[66] BC22 H_VCCP_SEL L25 VCC[67] VCCIO_SEL L28 VCC[68] L33 VCC[69] L36 VCC[70] +1. Inc.

3V6M 10U_0603_6.3V6K C145 1U_0402_6.3V6K C144 1U_0402_6.3V6K V58 AF48 AU7 V59 VAXG[46] AF50 VSS[41] VSS[131] AV17 VAXG[47] VSS[42] VSS[132] 1 1 1 1 1 1 1 1 1 1 W50 AF51 AV21 W51 VAXG[48] AF52 VSS[43] VSS[133] AV22 W52 VAXG[49] AF53 VSS[44] VSS[134] AV34 2 2 2 2 2 2 2 2 2 2 W53 VAXG[50] AF55 VSS[45] VSS[135] AV40 +VCC_GFXCORE_AXG W55 VAXG[51] VAXG[52] AF56 VSS[46] VSS[47] VSS[136] VSS[137] AV48 W56 AF58 AV55 W61 VAXG[53] AF59 VSS[48] VSS[138] AW13 Y48 VAXG[54] AG10 VSS[49] VSS[139] AW43 Y61 VAXG[55] AG14 VSS[50] VSS[140] AW61 B R620 VAXG[56] AG18 VSS[51] VSS[141] AW7 B 100_0402_1%~D AG47 VSS[52] VSS[142] AY14 1 2 1 R88 2 +1.3V6K C166 1U_0402_6. LA-8671P_SDV Date: Thursday. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D Document Number Rev Custom 1.5V_CPU_VDDQ M3 Support @ J1 R86 1 @ 2 0_0402_5% 1 2 Q2204 +VREF0 PAD-OPEN 4x4m BSS138_NL_SOT23-3 1 1 1 2 3 S D R66 @ C107 +V_DDR_REFA_R 1 [39. 5 4 3 2 1 +1.047U_0603_25V7K 2 [34] CPU1.3V6K C146 1U_0402_6.90 V Yes Yes AM30 VSS[88] VSS[178] BE5 W20 VCCSA[15] 0 1 0.3V6K C165 1U_0402_6. INC.5V +1.5VS3 1 2 RUN_ON_CPU1.5V_CPU_VDDQ +1.5V_S3_GATE 2 G @ 2 Q6 S G Q8 1 @ 2 2N7002K_SOT23-3 S 2N7002K_SOT23-3 3 [34.3V6M~D N22 AL33 BD23 SA RAIL P17 VCCSA[5] AL36 VSS[79] VSS[169] BD27 VCCSA[6] VSS[80] VSS[170] 1 10U_0603_6.3V6M 10U_0603_6.3V6M~D 1U_0402_6.42.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.3V6K C148 1U_0402_6.3V6K C143 1U_0402_6.85 V Yes Yes AM34 VSS[89] VSS[179] BG13 VCCSA[16] 1 0 0.3V6M 10U_0603_6. INC.3V6M~D C158 P20 U10 AL40 BD32 VCCSA[7] VCCSA_SENSE +VCCSA_SENSE [45] VSS[81] VSS[171] 1 1 1 1 1 330U_D2_2VM_R9M~D + R16 AL43 BD36 VCCSA[8] VSS[82] VSS[172] C162 C161 C159 C160 C163 R18 AL47 BD40 VCCSA[9] VSS[83] VSS[173] 1 R21 AL61 BD44 2 2 2 2 2 2 U15 VCCSA[10] @ R78 AM13 VSS[84] VSS[174] BD48 VCCSA VID V16 VCCSA[11] AM20 VSS[85] VSS[175] BD52 VCCSA[12] 0_0402_5%~D VSS[86] VSS[176] V17 D48 VCCSA_VID0 AM22 BD56 VCCSA[13] VCCSA_VID[0] VSS[87] VSS[177] lines V18 D49 VCCSA_VID1 VID[0] VID[1] ULV 2011 2012 AM26 BD8 2 V21 VCCSA[14] VCCSA_VID[1] 0 0 0.75 V No Yes A A R99 0_0402_5% 1 2 H_VCCSA_VID0 [45] C164 1U_0402_6.3V6M P56 AR30 AB61 AR48 VAXG[31] VDDQ[17] VSS[26] VSS[116] 1 C129 C130 C131 C135 C134 C133 C137 C136 P61 AR32 AC10 AR61 T48 VAXG[32] VDDQ[18] AR34 + C132 AC14 VSS[27] VSS[117] AR7 VAXG[33] VDDQ[19] VSS[28] VSS[118] 1 1 1 1 1 1 1 1 T58 AR36 330U_D2_2VM_R9M AC46 AT14 T59 VAXG[34] VDDQ[20] AR40 AC6 VSS[29] VSS[119] AT19 2 T61 VAXG[35] VDDQ[21] AV41 AD17 VSS[30] VSS[120] AT36 2 2 2 2 2 2 2 2 U46 VAXG[36] VDDQ[22] AW26 AD20 VSS[31] VSS[121] AT4 V47 VAXG[37] VDDQ[23] BA40 AD4 VSS[32] VSS[122] AT45 V48 V50 VAXG[38] VAXG[39] VAXG[40] VDDQ[24] VDDQ[25] VDDQ[26] BB28 BG33 AD61 AE13 VSS[33] VSS[34] VSS[35] VSS VSS[123] VSS[124] VSS[125] AT52 AT58 V51 AE8 AU1 V52 VAXG[41] AF1 VSS[36] VSS[126] AU11 V53 VAXG[42] AF17 VSS[37] VSS[127] AU28 V55 VAXG[43] AF21 VSS[38] VSS[128] AU32 V56 VAXG[44] AF47 VSS[39] VSS[129] AU51 VAXG[45] VSS[40] VSS[130] C139 1U_0402_6.3V6M~D 10U_0603_6.46] SUSP 0_0402_5% R65 220_0402_5% 0.5VS3# D S 1 R68 5 4 Q7 G R67 D G 2N7002K_SOT23-3 D 82K_0402_5% S D 100K_0402_5% @ AO4430L_SO8 3 R175 2 15K_0402_1% 2 RUN_ON_CPU1.3V6K IVY-BRIDGE_BGA1023 1 short@ 2 short@ H_VCCSA_VID1 [45] IVY-BRIDGE_BGA1023 1 1 1 1 1 R100 0_0402_5% CPU1@ CPU1@ 2 2 2 2 2 AMY WEN Security Classification Compal Secret Data Compal Electronics.6] 1 8 1 7 D S 2 D D S 1 6 3 2 RUN_ON_CPU1. 2012 Sheet 9 of 50 5 4 3 2 1 .5V_CPU_VDDQ RUN_ON_CPU1.5VS3# 1 1 1 1 @ D R69 C108 R71 2 1 0_0402_5% 2 D 330K_0402_5% 0.3V6M 10U_0603_6.5VS3# [5] +1. INC.1.3V6M 10U_0603_6.1U_0402_10V7K~D AJ45 BA26 VCCPLL[3] VSS[68] VSS[158] 1 1 1 1 22U_0805_6.3V6K AJ30 BA1 1.3V6M 10U_0603_6.5V_CPU_VDDQ AG52 VSS[53] VSS[143] AY19 AG61 VSS[54] VSS[144] AY30 100_0402_1%~D +1.3V6K C140 1U_0402_6.VSS AND TRADE SECRET INFORMATION.3V6M~D 10U_0603_6.3V6M C633 AJ48 BA32 VSS[69] VSS[159] C153 C154 C155 @ AJ7 BA48 AK1 VSS[70] VSS[160] BA51 2 2 2 2 BC43 AK52 VSS[71] VSS[161] BB53 VDDQ_SENSE BA43 AL10 VSS[72] VSS[162] BC13 VSS_SENSE_VDDQ VSS[73] VSS[163] SENSE LINES AL13 BC5 L17 AL17 VSS[74] VSS[164] BC57 +VCCSA L21 VCCSA[1] AL21 VSS[75] VSS[165] BD12 N16 VCCSA[2] AL25 VSS[76] VSS[166] BD16 N20 VCCSA[3] AL28 VSS[77] VSS[167] BD19 VCCSA[4] VSS[78] VSS[168] 10U_0603_6.3V6K~D BC4 C157 2 1 0.5V +V_SM_VREF should have 20 mil trace POWER 1 1 R72 2 @ 1 0_0402_5% width UCPU1G R98 @ R73 +VCC_GFXCORE_AXG 1K_0402_1%~D 1K_0402_1%~D 2 2 AY43 3 S D +V_SM_VREF_CNT 1 +V_SM_VREF AA46 SM_VREF Q11 UCPU1H VREF VAXG[1] 1 AB47 AO3414_SOT23-3 VAXG[2] 1 AB50 BE7 +V_DDR_REFA_R C115 @ @ R75 G 2 VAXG[3] SA_DIMM_VREFDQ 1 AB51 BG7 +V_DDR_REFB_R 0. Inc.3V6K C168 1U_0402_6.3V6K C142 1U_0402_6.1U_0402_10V7K~D AJ22 VSS[61] VSS[151] AY58 +1.775 V No Yes VSS[90] VSS[180] 1 1 0. October 04. Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.5V AG7 VSS[55] VSS[145] AY36 VSS[56] VSS[146] QUIET RAILS AM28 AH4 AY4 SENSE LINES @ VCCDQ[1] VSS[57] VSS[147] VCC_AXG_SENSE F45 AN26 AH58 AY41 [47] VCC_AXG_SENSE VSS_AXG_SENSE G45 VAXG_SENSE VCCDQ[2] 2 1 0.3V6K~D 1U_0402_6.46] SUSP# 0_0402_5% R70 @ 3 Follw G-Series +1.1U_0402_10V6K 2 G 2 2 +3VALW +VSB U7 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH [13. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.5V RAILS C AD52 VAXG[15] VDDQ[1] AJ33 A53 VSS[10] VSS[100] AN33 C AD53 VAXG[16] VDDQ[2] AJ36 A9 VSS[11] VSS[101] AN36 AD55 VAXG[17] VDDQ[3] AJ40 AA1 VSS[12] VSS[102] AN40 AD56 VAXG[18] VDDQ[4] AL30 AA13 VSS[13] VSS[103] AN43 AD58 VAXG[19] VDDQ[5] AL34 AA50 VSS[14] VSS[104] AN47 AD59 VAXG[20] VDDQ[6] AL38 AA51 VSS[15] VSS[105] AN50 AE46 VAXG[21] VDDQ[7] AL42 AA52 VSS[16] VSS[106] AN54 N45 VAXG[22] VDDQ[8] AM33 AA53 VSS[17] VSS[107] AP10 P47 VAXG[23] VDDQ[9] AM36 AA55 VSS[18] VSS[108] AP51 P48 VAXG[24] VDDQ[10] AM40 AA56 VSS[19] VSS[109] AP55 P50 VAXG[25] VDDQ[11] AN30 +1.5VS3 A13 AM38 2 AB55 VAXG[6] A17 VSS[1] VSS[91] AM4 AB56 VAXG[7] A21 VSS[2] VSS[92] AM42 2 VAXG[8] VSS[3] VSS[93] 1 1 AB58 A25 AM45 AB59 VAXG[9] @ R173 @ R129 A28 VSS[4] VSS[94] AM48 AC61 VAXG[10] 1K_0402_1%~D 1K_0402_1%~D A33 VSS[5] VSS[95] AM58 AD47 VAXG[11] A37 VSS[6] VSS[96] AN1 AD48 VAXG[12] A40 VSS[7] VSS[97] AN21 2 2 AD50 VAXG[13] A45 VSS[8] VSS[98] AN25 AD51 VAXG[14] AJ28 A49 VSS[9] VSS[99] AN28 .5V_CPU_VDDQ AA8 VSS[20] VSS[110] AP7 P51 VAXG[26] VDDQ[12] AN34 AB16 VSS[21] VSS[111] AR13 P52 VAXG[27] VDDQ[13] AN38 AB18 VSS[22] VSS[112] AR17 P53 VAXG[28] VDDQ[14] AR26 AB21 VSS[23] VSS[113] AR21 DDR3 P55 VAXG[29] VDDQ[15] AR28 AB48 VSS[24] VSS[114] AR41 GRAPHICS VAXG[30] VDDQ[16] VSS[25] VSS[115] 10U_0603_6.3V6M~D 10U_0603_6.1U_0402_10V7K~D AJ13 VSS[58] VSS[148] AY45 C150 [47] VSS_AXG_SENSE VSSAXG_SENSE AJ16 VSS[59] VSS[149] AY49 1 2 AJ20 VSS[60] VSS[150] AY55 1 2 C151 2 1 0.8V RAIL C152 2 1 0.3V6M 10U_0603_6.3V6K C141 1U_0402_6. AND CONTAINS CONFIDENTIAL PROCESSOR(6/6) PWR.1U_0402_16V4Z 1K_0402_1%~D AB52 VAXG[4] SB_DIMM_VREFDQ R92 2 AB53 VAXG[5] 1K_0402_1%~D RUN_ON_CPU1.3V6K C167 1U_0402_6.44.39.1U_0402_10V7K~D AJ34 VSS[64] VSS[154] BA11 BB3 AJ38 VSS[65] VSS[155] BA17 BC1 VCCPLL[1] AJ42 VSS[66] VSS[156] BA21 VCCPLL[2] VSS[67] VSS[157] 10U_0603_6.3V6K C147 1U_0402_6.8VS AJ26 VSS[62] VSS[152] AY9 C149 VSS[63] VSS[153] R619 100_0402_1%~D 1U_0402_6.

.32. Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS..7] DDR_A_DQS[0.5V BA1 VDD BA0 VDD +1.1_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA8 R5243 1 2 36_0402_5% R5212 R5213 1 1 1 1 DDR_A_MA6 R5244 1 2 36_0402_5% 1K_0402_1% 1K_0402_1% DDR_A_MA0 R5245 1 2 36_0402_5% 2 2 DDR_A_BS1 R5246 1 2 36_0402_5% 2 2 2 2 1 1 DDR_A_MA5 R5247 1 2 36_0402_5% DDR_A_MA2 R5248 1 2 36_0402_5% C5275 C5311 0.6] M_CLK_DDR1 +1.2U_0603_6.5V DDR_A_MA14 R5235 1 2 36_0402_5% M_CLK_DDR#0 2 M_CLK_DDR#1 2 R5207 R5208 [11.3V6K C5248 1U_0402_6.1U_0402_16V4Z 0.3V6K 220U_D2_2VY_R15M DDR_A_MA7 R5240 1 2 36_0402_5% 2 2 1 1 C5271 0.2U_0603_6.3V6K C5251 @ @ CAT24C02WI-GT3A_SO8 M_ODT0 R5215 1 2 36_0402_5% DDR_A_RAS# R5216 1 2 36_0402_5% 1 1 1 1 DDR_CKE0_DIMMA R5217 1 2 36_0402_5% 2 2 DDR_CS0_DIMMA# R5218 1 2 36_0402_5% DDR_A_WE# R5219 1 2 36_0402_5% 2 2 2 2 DDR_CS1_DIMMA# R5220 1 2 36_0402_5% [11.1U_0402_16V7K 0. AND CONTAINS CONFIDENTIAL DDRIII A Chip 2Gbit X16-I AND TRADE SECRET INFORMATION.1U_0402_16V4Z 0.1U_0402_16V4Z 0.3V6M 0. October 04.3V6M 10U_0603_6.15] [11.5V DDR_CKE1_DIMMA R5231 36_0402_5% [11.3V6M 10U_0603_6.1U_0402_16V4Z C5274 DDR_A_MA4 1 2 SGA00004L00 R5242 36_0402_5% 30.6] M_CLK_DDR#1 1K_0402_1% 1K_0402_1% DDR_A_MA3 R5236 1 2 36_0402_5% +VREF0 +VREF1 1 1 DDR_A_MA1 R5237 1 2 36_0402_5% 2 2 1 1 10U_0603_6.1U_0402_16V4Z 2 2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA6 R9 A5 2 2 DDR_A_MA5 P3 A4 DQL7 2 2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA6 R9 A5 DDR_A_MA7 R3 A6 D8 DDR_A_D25 DDR_A_MA6 R9 A5 DDR_A_MA6 R9 A5 DDR_A_MA7 R3 A6 D8 DDR_A_D12 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D31 DDR_A_MA7 R3 A6 D8 DDR_A_D41 DDR_A_MA7 R3 A6 D8 DDR_A_D56 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D15 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D28 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D43 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D63 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D13 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D26 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D40 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D60 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D10 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D29 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D47 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D58 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D9 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D27 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D45 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D61 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D11 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D24 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D46 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D59 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D8 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D30 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D44 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D57 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D14 A14 DQU7 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D42 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D62 A14 DQU7 A14 DQU7 A14 DQU7 DDR_A_BS0 M3 B3 BA0 VDD +1.7] [11.6] DDR_A_DQS[0.5V BA0 VDD +1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1_0402_1% 30.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS..1U_0402_16V4Z 0.3V6K C5249 1U_0402_6..5V DDR_A_BS0 M3 B3 DDR_A_BS1 N9 D10 DDR_A_BS0 M3 B3 DDR_A_BS0 M3 B3 [11. 5 4 3 2 1 DDR_A_MA[0. Inc. 2012 Sheet 10 of 50 5 4 3 2 1 AMY WEN .6] DDR_A_DQS#[0.6] DDR_A_BS1 BA1 VDD BA2 VDD BA1 VDD BA1 VDD DDR_A_BS2 M4 G8 K3 DDR_A_BS2 M4 G8 DDR_A_BS2 M4 G8 [11.7] [11.3V6M 10U_0603_6.1U_0402_16V4Z A 2 2 A Security Classification Compal Secret Data Compal Electronics.3V6K 2.6] DDR_A_D[0.1U_0402_16V7K 1 DDR_A_BS2 R5238 1 2 36_0402_5% C5253 C5254 C5255 C5258 C5256 C5259 C5260 C5261 C5262 C5263 1 1 1 1 1 1 1 1 1 1 @ DDR_A_MA15 R5239 1 2 36_0402_5% R5209 R5230 +VREF0 +VREF1 + C5257 R5210 R5229 2.35] R5201 M_ODT1 R5214 1 2 36_0402_5% [11.6] DDR3_DRAMRST# RESET VSS VSS RESET VSS RESET VSS T2 1 2 R5196 L9 T10 T2 T2 240_0402_1% 240_0402_1%1 2 R5197 L9 VSS T10 240_0402_1% ZQ VSS 1 2 R5198 L9 VSS T10 1 2 R5199 L9 VSS T10 ZQ VSS 240_0402_1% ZQ VSS 240_0402_1% ZQ VSS J2 B2 J2 B2 L2 NC VSSQ B10 J2 B2 J2 B2 L2 NC VSSQ B10 J10 NC VSSQ D2 L2 NC VSSQ B10 L2 NC VSSQ B10 J10 NC VSSQ D2 L10 NC VSSQ D9 J10 NC VSSQ D2 J10 NC VSSQ D2 L10 NC VSSQ D9 NC VSSQ E3 L10 NC VSSQ D9 L10 NC VSSQ D9 NC VSSQ E3 DDR_A_MA15 M8 VSSQ E9 NC VSSQ E3 NC VSSQ E3 DDR_A_MA15 M8 VSSQ E9 NC VSSQ F10 DDR_A_MA15 M8 VSSQ E9 DDR_A_MA15 M8 VSSQ E9 NC VSSQ F10 VSSQ G2 NC VSSQ F10 NC VSSQ F10 VSSQ G2 VSSQ G10 VSSQ G2 VSSQ G2 VSSQ G10 VSSQ VSSQ G10 VSSQ G10 VSSQ 96-BALL VSSQ VSSQ 96-BALL SDRAM DDR3L 96-BALL 96-BALL SDRAM DDR3L H5TC4G63MFR-PBA_FBGA96 SDRAM DDR3L SDRAM DDR3L H5TC4G63MFR-PBA_FBGA96 DDR1@ H5TC4G63MFR-PBA_FBGA96 H5TC4G63MFR-PBA_FBGA96 DDR1@ DDR1@ DDR1@ B B SA00001LV10 +3VS @ C5247 @ 1 2 U5010 +0.6] M_ODT1 R5200 1U_0402_6.1_0402_1% 30.5V DDR_A_BS1 N9 D10 DDR_A_BS2 M4 G8 DDR_A_BS1 N9 D10 DDR_A_BS1 N9 D10 [11.3V6M 10U_0603_6.6] DDR_CS1_DIMMA# 1 2 DDR_A_CAS# R5221 36_0402_5% DDR_A_MA12 R5222 1 2 36_0402_5% DDR_A_BS0 R5227 1 2 36_0402_5% DDR_A_MA10 R5228 1 2 36_0402_5% M_CLK_DDR0 M_CLK_DDR1 1 2 [11.6] DDR_A_RAS# RAS VDDQ CAS VDDQ RAS VDDQ RAS VDDQ DDR_A_CAS# K4 C10 DDR_A_WE# L4 D3 DDR_A_CAS# K4 C10 DDR_A_CAS# K4 C10 [11.1U_0402_16V4Z DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D0 2 2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D33 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D52 0.63] D D +VREF0 +VREF1 +VREF0 +VREF1 +VREF0 +VREF1 +VREF0 +VREF1 U5009 U5006 U5008 U5007 M9 E4 DDR_A_D23 M9 E4 DDR_A_D6 H2 VREFCA DQL0 F8 DDR_A_D16 M9 E4 DDR_A_D38 M9 E4 DDR_A_D51 H2 VREFCA DQL0 F8 DDR_A_D1 VREFDQ DQL1 F3 DDR_A_D18 H2 VREFCA DQL0 F8 DDR_A_D32 H2 VREFCA DQL0 F8 DDR_A_D49 VREFDQ DQL1 F3 DDR_A_D2 DDR_A_MA0 N4 DQL2 F9 DDR_A_D17 VREFDQ DQL1 F3 DDR_A_D34 VREFDQ DQL1 F3 DDR_A_D50 DDR_A_MA0 N4 DQL2 F9 DDR_A_D5 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D19 DDR_A_MA0 N4 DQL2 F9 DDR_A_D37 DDR_A_MA0 N4 DQL2 F9 DDR_A_D53 A0 DQL3 1 1 A1 DQL4 A0 DQL3 A0 DQL3 1 1 DDR_A_MA1 P8 H4 DDR_A_D3 C5242 C5243 DDR_A_MA2 P4 H9 DDR_A_D20 1 1 DDR_A_MA1 P8 H4 DDR_A_D35 1 1 DDR_A_MA1 P8 H4 DDR_A_D55 C5239 C5241 DDR_A_MA2 P4 A1 DQL4 H9 DDR_A_D4 DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D22 C5244 C5240 DDR_A_MA2 P4 A1 DQL4 H9 DDR_A_D36 C5245 C5246 DDR_A_MA2 P4 A1 DQL4 H9 DDR_A_D48 0.1_0402_1% 30.1U_0402_16V4Z~D 2 A0 VCC 7 3 A1 WP 6 SMB_CLK_S3 A2 SCL SMB_CLK_S3 [13.3V6K C5250 1U_0402_6.1U_0402_16V7K 0.21.1U_0402_16V4Z C5272 C5273 0.6] DDR_A_BS2 BA2 VDD K3 VDD K9 BA2 VDD K3 BA2 VDD K3 VDD K9 VDD N2 VDD K9 VDD K9 VDD N2 M_CLK_DDR0 J8 VDD N10 VDD N2 VDD N2 M_CLK_DDR0 J8 VDD N10 M_CLK_DDR#0 K8 CK VDD R2 M_CLK_DDR0 J8 VDD N10 M_CLK_DDR0 J8 VDD N10 [6] M_CLK_DDR0 CK VDD CK VDD CK VDD CK VDD M_CLK_DDR#0 K8 R2 DDR_CKE0_DIMMA K10 R10 M_CLK_DDR#0 K8 R2 M_CLK_DDR#0 K8 R2 [6] M_CLK_DDR#0 K10 CK VDD R10 CKE VDD CK VDD CK VDD DDR_CKE0_DIMMA DDR_CKE0_DIMMA K10 R10 DDR_CKE0_DIMMA K10 R10 [6] DDR_CKE0_DIMMA CKE VDD CKE VDD CKE VDD M_ODT0 K2 A2 M_ODT0 K2 A2 DDR_CS0_DIMMA# L3 ODT VDDQ A9 M_ODT0 K2 A2 M_ODT0 K2 A2 [6] M_ODT0 ODT VDDQ CS VDDQ ODT VDDQ ODT VDDQ DDR_CS0_DIMMA# L3 A9 DDR_A_RAS# J4 C2 DDR_CS0_DIMMA# L3 A9 DDR_CS0_DIMMA# L3 A9 [6] DDR_CS0_DIMMA# J4 CS VDDQ C2 K4 RAS VDDQ C10 J4 CS VDDQ C2 J4 CS VDDQ C2 DDR_A_RAS# DDR_A_CAS# DDR_A_RAS# DDR_A_RAS# [11.21. LA-8671P_SDV Date: Thursday.1U_0402_16V7K 0.1U_0402_16V4Z 0.6] DDR_CKE1_DIMMA 1 1 DDR_A_MA11 R5232 1 2 36_0402_5% DDR_A_MA13 R5233 1 2 36_0402_5% C5252 C5288 1 1 DDR_A_MA9 R5234 1 2 36_0402_5% 2P_0402_50V8C 2P_0402_50V8C +1.32..6] DDR_A_MA[0. INC..1U_0402_16V4Z DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D7 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D21 DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D39 DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D54 0.7] DDR_A_D[0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev D 1.6] DDR_A_CAS# L4 CAS VDDQ D3 WE VDDQ E10 L4 CAS VDDQ D3 L4 CAS VDDQ D3 DDR_A_WE# DDR_A_WE# DDR_A_WE# [11..3V6M 10U_0603_6. INC..1U_0402_16V4Z 0.6] DDR_A_WE# WE VDDQ E10 VDDQ F2 WE VDDQ E10 WE VDDQ E10 C VDDQ F2 DDR_A_DQS2 F4 VDDQ H3 VDDQ F2 VDDQ F2 C DDR_A_DQS0 F4 VDDQ H3 DDR_A_DQS3 C8 DQSL VDDQ H10 DDR_A_DQS4 F4 VDDQ H3 DDR_A_DQS6 F4 VDDQ H3 DDR_A_DQS1 C8 DQSL VDDQ H10 DQSU VDDQ DDR_A_DQS5 C8 DQSL VDDQ H10 DDR_A_DQS7 C8 DQSL VDDQ H10 DQSU VDDQ DQSU VDDQ DQSU VDDQ E8 A10 E8 A10 D4 DML VSS B4 E8 A10 E8 A10 D4 DML VSS B4 DMU VSS E2 D4 DML VSS B4 D4 DML VSS B4 DMU VSS E2 VSS G9 DMU VSS E2 DMU VSS E2 VSS G9 DDR_A_DQS#2 G4 VSS J3 VSS G9 VSS G9 DDR_A_DQS#0 G4 VSS J3 DDR_A_DQS#3 B8 DQSL VSS J9 DDR_A_DQS#4 G4 VSS J3 DDR_A_DQS#6 G4 VSS J3 DDR_A_DQS#1 B8 DQSL VSS J9 DQSU VSS M2 DDR_A_DQS#5 B8 DQSL VSS J9 DDR_A_DQS#7 B8 DQSL VSS J9 DQSU VSS M2 VSS M10 DQSU VSS M2 DQSU VSS M2 VSS M10 VSS P2 VSS M10 VSS M10 VSS P2 DDR3_DRAMRST# T3 VSS P10 VSS P2 VSS P2 DDR3_DRAMRST# T3 VSS P10 RESET VSS T2 DDR3_DRAMRST# T3 VSS P10 DDR3_DRAMRST# T3 VSS P10 [11.63] [11. INC.35] 1 1 1K_0402_5%~D 1K_0402_5%~D 4 5 SMB_DATA_S3 VSS SDA SMB_DATA_S3 [13.15] DDR_A_DQS#[0.75VS 1 8 0.5V +1.6] DDR_A_BS0 BA0 VDD +1.

..6] DDR_A_MA[0.5V DDR_A_BS1 N9 D10 DDR_A_BS2 M4 G8 DDR_A_BS1 N9 D10 DDR_A_BS1 N9 D10 [10.6] DDR3_DRAMRST# RESET VSS VSS RESET VSS RESET VSS T2 1 2 R5223 L9 T10 T2 T2 240_0402_1% 240_0402_1%1 2 R5224 L9 VSS T10 240_0402_1% ZQ VSS 1 2 R5225 L9 VSS T10 1 2 R5226 L9 VSS T10 ZQ VSS 240_0402_1% ZQ VSS 240_0402_1% ZQ VSS J2 B2 J2 B2 L2 NC VSSQ B10 J2 B2 J2 B2 L2 NC VSSQ B10 J10 NC VSSQ D2 L2 NC VSSQ B10 L2 NC VSSQ B10 J10 NC VSSQ D2 L10 NC VSSQ D9 J10 NC VSSQ D2 J10 NC VSSQ D2 L10 NC VSSQ D9 NC VSSQ E3 L10 NC VSSQ D9 L10 NC VSSQ D9 NC VSSQ E3 DDR_A_MA15 M8 VSSQ E9 NC VSSQ E3 NC VSSQ E3 DDR_A_MA15 M8 VSSQ E9 NC VSSQ F10 DDR_A_MA15 M8 VSSQ E9 DDR_A_MA15 M8 VSSQ E9 NC VSSQ F10 VSSQ G2 NC VSSQ F10 NC VSSQ F10 VSSQ G2 VSSQ G10 VSSQ G2 VSSQ G2 VSSQ G10 VSSQ VSSQ G10 VSSQ G10 VSSQ 96-BALL VSSQ VSSQ 96-BALL SDRAM DDR3L 96-BALL 96-BALL SDRAM DDR3L H5TC4G63MFR-PBA_FBGA96 SDRAM DDR3L SDRAM DDR3L H5TC4G63MFR-PBA_FBGA96 DDR1@ H5TC4G63MFR-PBA_FBGA96 H5TC4G63MFR-PBA_FBGA96 DDR1@ DDR1@ DDR1@ B B CLIP1 CLIP2 1 1 P1 P1 EMIST_SUL-12A2M EMIST_SUL-12A2M CLIP5 1 ME@ ME@ P1 EMIST_SUL-12A2M CLIP3 CLIP4 ME@ 1 1 P1 P1 EMIST_SUL-12A2M EMIST_SUL-12A2M ME@ ME@ A A Security Classification Compal Secret Data Compal Electronics.6] DDR_A_DQS[0. 2012 Sheet 11 of 50 5 4 3 2 1 AMY WEN .6] DDR_A_DQS#[0.7] [10.5V BA0 VDD +1.6] DDR_A_BS2 BA2 VDD K3 VDD K9 BA2 VDD K3 BA2 VDD K3 VDD K9 VDD N2 VDD K9 VDD K9 VDD N2 M_CLK_DDR1 J8 VDD N10 VDD N2 VDD N2 M_CLK_DDR1 J8 VDD N10 M_CLK_DDR#1 K8 CK VDD R2 M_CLK_DDR1 J8 VDD N10 M_CLK_DDR1 J8 VDD N10 [10.7] DDR_A_DQS[0.1U_0402_16V4Z DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D3 2 2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D35 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D55 0.63] [10.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. October 04. Inc.6] DDR_A_WE# WE VDDQ E10 VDDQ F2 WE VDDQ E10 WE VDDQ E10 C VDDQ F2 DDR_A_DQS2 F4 VDDQ H3 VDDQ F2 VDDQ F2 C DDR_A_DQS0 F4 VDDQ H3 DDR_A_DQS3 C8 DQSL VDDQ H10 DDR_A_DQS4 F4 VDDQ H3 DDR_A_DQS6 F4 VDDQ H3 DDR_A_DQS1 C8 DQSL VDDQ H10 DQSU VDDQ DDR_A_DQS5 C8 DQSL VDDQ H10 DDR_A_DQS7 C8 DQSL VDDQ H10 DQSU VDDQ DQSU VDDQ DQSU VDDQ E8 A10 E8 A10 D4 DML VSS B4 E8 A10 E8 A10 D4 DML VSS B4 DMU VSS E2 D4 DML VSS B4 D4 DML VSS B4 DMU VSS E2 VSS G9 DMU VSS E2 DMU VSS E2 VSS G9 DDR_A_DQS#2 G4 VSS J3 VSS G9 VSS G9 DDR_A_DQS#0 G4 VSS J3 DDR_A_DQS#3 B8 DQSL VSS J9 DDR_A_DQS#4 G4 VSS J3 DDR_A_DQS#6 G4 VSS J3 DDR_A_DQS#1 B8 DQSL VSS J9 DQSU VSS M2 DDR_A_DQS#5 B8 DQSL VSS J9 DDR_A_DQS#7 B8 DQSL VSS J9 DQSU VSS M2 VSS M10 DQSU VSS M2 DQSU VSS M2 VSS M10 VSS P2 VSS M10 VSS M10 VSS P2 DDR3_DRAMRST# T3 VSS P10 VSS P2 VSS P2 DDR3_DRAMRST# T3 VSS P10 RESET VSS T2 DDR3_DRAMRST# T3 VSS P10 DDR3_DRAMRST# T3 VSS P10 [10.6] M_ODT1 ODT VDDQ CS VDDQ ODT VDDQ ODT VDDQ DDR_CS1_DIMMA# L3 A9 DDR_A_RAS# J4 C2 DDR_CS1_DIMMA# L3 A9 DDR_CS1_DIMMA# L3 A9 [10. AND CONTAINS CONFIDENTIAL DDRIII A Chip 2Gbit X16-II AND TRADE SECRET INFORMATION. INC.1U_0402_16V4Z 0. INC.1U_0402_16V4Z 0.6] DDR_CS1_DIMMA# J4 CS VDDQ C2 K4 RAS VDDQ C10 J4 CS VDDQ C2 J4 CS VDDQ C2 DDR_A_RAS# DDR_A_CAS# DDR_A_RAS# DDR_A_RAS# [10...63] D D +VREF0 +VREF1 +VREF0 +VREF1 +VREF0 +VREF1 +VREF0 +VREF1 UD2 UD1 UD3 UD4 M9 E4 DDR_A_D16 M9 E4 DDR_A_D1 H2 VREFCA DQL0 F8 DDR_A_D23 M9 E4 DDR_A_D32 M9 E4 DDR_A_D49 H2 VREFCA DQL0 F8 DDR_A_D6 VREFDQ DQL1 F3 DDR_A_D17 H2 VREFCA DQL0 F8 DDR_A_D38 H2 VREFCA DQL0 F8 DDR_A_D51 VREFDQ DQL1 F3 DDR_A_D5 DDR_A_MA0 N4 DQL2 F9 DDR_A_D18 VREFDQ DQL1 F3 DDR_A_D37 VREFDQ DQL1 F3 DDR_A_D53 DDR_A_MA0 N4 DQL2 F9 DDR_A_D2 DDR_A_MA1 P8 A0 DQL3 H4 DDR_A_D21 DDR_A_MA0 N4 DQL2 F9 DDR_A_D34 DDR_A_MA0 N4 DQL2 F9 DDR_A_D50 A0 DQL3 1 1 A1 DQL4 A0 DQL3 A0 DQL3 1 1 DDR_A_MA1 P8 H4 DDR_A_D0 C5277 C5281 DDR_A_MA2 P4 H9 DDR_A_D22 1 1 DDR_A_MA1 P8 H4 DDR_A_D33 1 1 DDR_A_MA1 P8 H4 DDR_A_D52 C5280 C5276 DDR_A_MA2 P4 A1 DQL4 H9 DDR_A_D7 DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D20 C5278 C5279 DDR_A_MA2 P4 A1 DQL4 H9 DDR_A_D39 C5282 C5283 DDR_A_MA2 P4 A1 DQL4 H9 DDR_A_D54 0.1U_0402_16V4Z 0.6] DDR_A_D[0.15] [10.. 5 4 3 2 1 DDR_A_MA[0..6] DDR_A_BS0 BA0 VDD +1.15] DDR_A_DQS#[0.7] [10...6] DDR_CKE1_DIMMA CKE VDD CKE VDD CKE VDD M_ODT1 K2 A2 M_ODT1 K2 A2 DDR_CS1_DIMMA# L3 ODT VDDQ A9 M_ODT1 K2 A2 M_ODT1 K2 A2 [10.1U_0402_16V4Z 2 2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA6 R9 A5 2 2 DDR_A_MA5 P3 A4 DQL7 2 2 DDR_A_MA5 P3 A4 DQL7 DDR_A_MA6 R9 A5 DDR_A_MA7 R3 A6 D8 DDR_A_D31 DDR_A_MA6 R9 A5 DDR_A_MA6 R9 A5 DDR_A_MA7 R3 A6 D8 DDR_A_D15 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D25 DDR_A_MA7 R3 A6 D8 DDR_A_D43 DDR_A_MA7 R3 A6 D8 DDR_A_D63 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D12 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D26 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D41 DDR_A_MA8 T9 A7 DQU0 C4 DDR_A_D56 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D10 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D28 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D47 DDR_A_MA9 R4 A8 DQU1 C9 DDR_A_D58 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D13 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D30 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D40 DDR_A_MA10 L8 A9 DQU2 C3 DDR_A_D60 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D14 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D24 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D42 DDR_A_MA11 R8 A10/AP DQU3 A8 DDR_A_D62 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D8 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D27 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D44 DDR_A_MA12 N8 A11 DQU4 A3 DDR_A_D57 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D11 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D29 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D46 DDR_A_MA13 T4 A12/BC DQU5 B9 DDR_A_D59 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D9 A14 DQU7 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D45 DDR_A_MA14 T8 A13 DQU6 A4 DDR_A_D61 A14 DQU7 A14 DQU7 A14 DQU7 DDR_A_BS0 M3 B3 BA0 VDD +1. LA-8671P_SDV Date: Thursday.1U_0402_16V4Z 0.1U_0402_16V4Z 0.5V BA1 VDD BA0 VDD +1.6] M_CLK_DDR#1 K10 CK VDD R10 CKE VDD CK VDD CK VDD DDR_CKE1_DIMMA DDR_CKE1_DIMMA K10 R10 DDR_CKE1_DIMMA K10 R10 [10. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.6] DDR_A_RAS# RAS VDDQ CAS VDDQ RAS VDDQ RAS VDDQ DDR_A_CAS# K4 C10 DDR_A_WE# L4 D3 DDR_A_CAS# K4 C10 DDR_A_CAS# K4 C10 [10.6] M_CLK_DDR1 CK VDD CK VDD CK VDD CK VDD M_CLK_DDR#1 K8 R2 DDR_CKE1_DIMMA K10 R10 M_CLK_DDR#1 K8 R2 M_CLK_DDR#1 K8 R2 [10. INC.6] DDR_A_BS1 BA1 VDD BA2 VDD BA1 VDD BA1 VDD DDR_A_BS2 M4 G8 K3 DDR_A_BS2 M4 G8 DDR_A_BS2 M4 G8 [10.7] DDR_A_D[0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev D 1.1U_0402_16V4Z DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D4 DDR_A_MA4 P9 A3 DQL6 H8 DDR_A_D19 DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D36 DDR_A_MA3 N3 A2 DQL5 G3 DDR_A_D48 0.6] DDR_A_CAS# L4 CAS VDDQ D3 WE VDDQ E10 L4 CAS VDDQ D3 L4 CAS VDDQ D3 DDR_A_WE# DDR_A_WE# DDR_A_WE# [10.5V DDR_A_BS0 M3 B3 DDR_A_BS1 N9 D10 DDR_A_BS0 M3 B3 DDR_A_BS0 M3 B3 [10. Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.

HDA.) HDA_SDIN3 SATA3RXP AF3 SATA3TXN AF1 [32] PCH_WLBT_OFF_5# SATA3TXP HDA_SDOUT A36 HDA_SDO Y7 SATA +3VS @ SATA4RXN Y5 R121 2 1 10K_0402_5% PCH_WLBT_OFF_5# C36 SATA4RXP AD3 +3VS HDA_DOCK_EN# / GPIO33 SATA4TXN R117 1 @ 2 1K_0402_5% HDA_SPKR AD1 R5018 1 2 1K_0402_5% PCH_GPIO13 N32 SATA4TXP +3V_PCH HDA_DOCK_RST# / GPIO13 HIGH= Enable ( No Reboot ) @ Y3 SATA5RXN Y1 LOW= Disable (Default) * SATA5RXP SATA5TXN AB3 Boot BIOS Strap bit1 BBS1 PCH_JTAG_TCK J3 AB1 JTAG_TCK SATA5TXP C GPIO51 GPIO19 Boot BIOS C PCH_JTAG_TMS H7 Y11 R123 JTAG_TMS SATAICOMPO 37.3K_0402_5% 11 2 +1.36.37] 1 2 Y1 1U_0603_10V4Z C37 LPC_AD3 LPC_AD3 [34. AND CONTAINS CONFIDENTIAL PCH (1/8) SATA. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 1. 2012 1 Sheet 12 of 50 .5] PBTN_OUT# 9 WP# SCLK R85 1 @ 2 1K_0402_1% 10 4 5 SPI_SI_R 1 2 SPI_SI R761 1 2 0_0402_5% 11 10 GND SI R5172 33_0402_5% SPI_HOLD# R5173 1 2 3.SPI.05VS_SATA3 SATA3RCOMPO 1 0 Reserved 49.37] 1 C216 CLRP1 18P_0402_50V8J 18P_0402_50V8J 1 2 PCH_SRTCRST# G22 1U_0603_10V4Z SHORT PADS R115 20K_0402_5% SRTCRST# E36 +3VS 2 LDRQ0# 1 1 2 2 SHORT PADS CLRP3 K22 K36 2 R116 1 10K_0402_5% RTC SM_INTRUDER# 2 12/27 C218 INTRUDER# LDRQ1# / GPIO23 D 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ SERIRQ [34.3K_0402_5% [14.36.01U_0402_16V7K 2 1 C223 SATA_ITX_DRX_N2_CONN HDA_SDIN1 SATA2TXN SATA_ITX_DRX_N2_CONN [32] Integrated VRM enable ME_FLASH 1 2 AH4 SATA_ITX_C_DRX_P2 0. 2 2 2 2 Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. October 04.4_0402_1% +1. LPC.768KHZ_12. INC.01U_0402_16V7K 2 1 C224 SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_P2_CONN [32] [34] ME_FLASH SATA2TXP VRM disable 0_0402_5% C34 HDA_SDIN2 AB8 IHDA A34 SATA3RXN AB10 (INTVRMEN should always be pull high. INC.05VS_VCC_SATA Bit11 Bit10 Destination JTAG PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2 +3V_PCH JTAG_TDI SATAICOMPI +5VS 0 1 Reserved PCH_JTAG_TDO H1 R118 2 @ 1 1K_0402_5% HDA_SDOUT JTAG_TDO AB12 R125 +1. 5 4 3 2 1 PCH_RTCX1 W=20mils W=20mils UH1A 1 2 PCH_RTCX2 +RTCVCC +RTCBATT SHORT PADS CLRP2 R109 10M_0402_5% +RTCVCC PCH_RTCX1 A20 C38 LPC_AD0 RTCX1 FWH0 / LAD0 LPC_AD0 [34.01U_0402_16V7K 2 1 C220 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 [36] HDA_SYNC SATA0TXP +RTCVCC HDA_SPKR T10 AM10 [28] HDA_SPKR SPKR SATA1RXN AM8 R112 1 2 1M_0402_5% SM_INTRUDER# HDA_RST# K34 SATA1RXP AP11 HDA_RST# SATA1TXN AP10 R113 1 2 330K_0402_5% PCH_INTVRMEN SATA1TXP [28] HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_N2 [32] HDA_SDIN0 SATA2RXN AD5 SATA_DTX_C_IRX_P2 INTVRMEN(DCP_SUS) SATA2RXP SATA_DTX_C_IRX_P2 [32] mSATA * LH::Integrated R119 G34 AH5 SATA_ITX_C_DRX_N2 0.9_0402_1% Low = Disabled (Default) AB13 SATA3_COMP 1 2 1 1 SPI (Default) * High = Enabled [Flash SATA3COMPI * Descriptor Security 0 0 LPC SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2 SPI_CLK SATA3RBIAS 2 Overide] G Q9 R127 BSS138_NL_SOT23-3 SPI_SB_CS0# Y14 750_0402_1% HDA_SYNC_R 3 1 HDA_SYNC SPI_CS0# SPI_SB_CS1# T1 S D SPI_CS1# SPI P3 PCH_SATALED# 2 R130 1 +3VS SATALED# 10K_0402_5% 1 +3V_PCH SPI_SI V4 V14 PCH_GPIO21 2 R132 1 SPI_MOSI SATA0GP / GPIO21 +3VS R5017 10K_0402_5% R120 2 1 1K_0402_5% HDA_SYNC 1M_0402_5% SPI_SO_R U3 P1 ODD_DET# 2 R133 1 +3VS SPI_MISO SATA1GP / GPIO19 10K_0402_5% This signal has a weak internal pull-down 2 PANTHER-POINT_FCBGA989 On Die PLL VR Select is supplied by * 1.1U_0402_16V4Z SBA@ 33_0402_5% 5 4 8M SPI_WP#1 R104 1 2 3.3K_0402_5% 33_0402_5% 8 7 SPI_SO_R R5169 1 2 33_0402_5% SPI_SO_L 2 CS# VCC 7 SPI_HOLD# R5170 0_0402_5% 1 2 HDA_SDOUT 9 8 SPI_WP# 3 SO HOLD# 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R SPI_WP# R5171 1 2 3.36.36] D 2 2 INTVRMEN SERIRQ AM3 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 [36] HDA_BIT_CLK N34 SATA0RXN AM1 SATA_DTX_C_IRX_P0 HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 [36] CMOS AP7 SATA_ITX_C_DRX_N0 0.5PF_CM31532768DZFT A38 LPC_AD1 FWH1 / LAD1 LPC_AD1 [34.5V when smapled high 1.37] LPC 1K_0402_5% 1 2 C217 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port RTCX2 FWH2 / LAD2 LPC_AD2 [34.8V when sampled low SA00004NQ70 Needs to be pulled High for Huron River platfrom @ C81 1 2 22P_0402_50V8J HDA_BITCLK_AUDIO 8M 1'S : SA000039A20 SPI ROM Winbond For SBA SBA: 8M +4 M @ C83 1 2 22P_0402_50V8J HDA_SDOUT_AUDIO +3VSPI +3VS +3VM NOSBA: 8M B 8M 2'S : SA000046400 E-ON Check BOM B NOSBA@ 8M 2'S : SA000039A10 WINBOND R5182 1 2 0_0402_5% R124 33_0402_5% Reserve for RF R5183 1 2 0_0402_5% 1 2 HDA_BIT_CLK JDB2 4M 1'S : SA00003K800 Winbond SBA@ [28] HDA_BITCLK_AUDIO R126 1 33_0402_5% 2 1 4M 2'S : SA00004LI00 E-ON 1 2 HDA_SYNC_R 3 2 +3VSPI [28] HDA_SYNC_AUDIO 3 R128 4 C225 1 2 0.01U_0402_16V7K 2 1 C219 SATA_ITX_DRX_N0 HDD SATA 6G SATA0TXN SATA_ITX_DRX_N0 [36] HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.5] XDP_DBRESET# 19 18 4M @ 1 +3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TDO 20 19 SBA@ U2202 20 2 21 SPI_SB_CS1# R5174 1 2 0_0402_5% CS1# 1 8 PCH_JTAG_TDI 22 21 SPI_SO_R R5191 1 2 33_0402_5% SPI_SO1 2 CS# VCC 7 SPI_HOLD#1 SBA@ R5175 C80 22 SO HOLD# 6 1 1 1 PCH_JTAG_TMS 23 SPI_WP#1 3 SPI_CLK1 1 2 0_0402_5% SPI_CLK_PCH_R 22P_0402_50V8J R134 R135 R136 24 23 SBA@ 4 WP# SCLK 5 SPI_SI1 1 2 SPI_SI 1 24 GND SI @ @ 200_0402_5% @ 200_0402_5% @ 200_0402_5% 25 2 R5176 26 25 W25Q32BVSSIG_SO8 SBA@ 33_0402_5% PCH_JTAG_TCK 26 Reserve for EMI please close to UH1 A 27 SBA@ C86 A 2 2 2 PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TCK 28 G1 G2 1 22P_0402_50V8J RF Request @ 1 1 1 1 ACES_88717-2601 R138 R139 R140 R122 ME@ @ 100_0402_1% @ 100_0402_1% @ 100_0402_1% 51_0402_5% Security Classification Compal Secret Data Compal Electronics. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8671P_SDV AMY WEN 5 4 3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.34] EC_RSMRST# 5 1 2 HDA_RST# 6 U5 [28] HDA_RST_AUDIO# 6 R131 7 SPI_SB_CS0# R5168 1 2 0_0402_5% CS0# 1 8 SPI_HOLD#1 R106 1 SBA@ 2 3.05VS_DB2 14 13 14 22P_0402_50V8J RF Request 2 15 1 15 @ 16 R143 EC_RSMRST# R84 1 @ 2 1K_0402_1% 17 16 +3VSPI 17 33_0402_5% XDP_DBRESET# 18 [14.37] 1 1 R111 32.3K_0402_5% [28] HDA_SDOUT_AUDIO [14. 2 Date: Thursday.37] 2 2 1 2 PCH_RTCRST# D20 FWH3 / LAD3 1 1 RTCRST# 1 C214 C215 R114 20K_0402_5% D36 LPC_FRAME# FWH4 / LFRAME# LPC_FRAME# [34.34.36.36.05VS @ 12 W25Q64FVSSIG_SO8 13 12 C85 SPI_CLK_PCH_R +3V_PCH R290 1 @ 2 0_0402_5% +1. Inc. INC. XDP Size Document Number Rev AND TRADE SECRET INFORMATION.

30.9] 2N7002DW-T/R7_SOT363-6 BJ36 PERN3 C8 PCH_SML0CLK 2 R152 1 PERP3 SML0CLK +3V_PCH Q2B D AV34 1K_0402_5% D AU34 PETN3 G12 PCH_SML0DATA PETP3 SML0DATA R153 10K_0402_5% Q10A PCIE_PRX_DTX_N4 BF36 2 1 2N7002DW-T/R7_SOT363-6 [30] PCIE_PRX_DTX_N4 PERN4 +3V_PCH LAN PCIE_PRX_DTX_P4 BE36 6 1 EC_SMB_CK2 [30] PCIE_PRX_DTX_P4 PERP4 EC_SMB_CK2 [33.2K_0402_5% PETP6 PCH_SML0CLK 2 R206 1 +3V_PCH Link BG40 T11 PERN7 CL_DATA1 2 BJ40 2. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev Custom 1.2K_0402_5% Security ROM C229 1 2 0. SMBUS.2K_0402_5% 2. INC.1U_0402_16V4Z [30] CLK_PCIE_LAN# short@ CLKOUT_PCIE3N CLKIN_GND1_N [16.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32 PERP2 PETN2 2.21. 5 4 3 2 1 UH1B SMB_ALERT# [21] Q2A 2N7002DW-T/R7_SOT363-6 PCIE_PRX_DTX_N1 BG34 10K_0402_5% 6 1 SMB_CLK_S3 [22] PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 [10.35] PCIE_PRX_DTX_P1 BJ34 E12 SMB_ALERT# 2 1 [22] PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH Card reader C230 1 2 0.05VS_VCCDIFFCLKN +3V_PCH PEG_B_CLKRQ# / GPIO56 90.2K_0402_5% [30] PCIE_PTX_C_DRX_P4 PETP4 E14 1 PCH_SML1CLK R154 2 EC 2 BG37 SML1CLK / GPIO58 PCI-E* PERN5 +3V_PCH +3VS BH37 M16 PCH_SML1DATA 1 2 PERP5 SML1DATA / GPIO75 Thermal Sensor 5 AY36 R155 BB36 PETN5 2.35] SMBUS DRAMRST_CNTRL_PCH BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH [6.32.22.34] BG38 PERN6 2N7002DW-T/R7_SOT363-6 AU36 PERP6 M7 Controller PETN6 CL_CLK1 Q10B AV36 +3V_PCH 2.2K_0402_5% AY40 PERP7 R156 PCH_SML0DATA 2 R250 1 PETN7 +3V_PCH BB40 P10 10K_0402_5% PETP7 CL_RST1# BE38 1 BC38 PERN8 AW38 PERP8 AY38 PETN8 PETP8 M10 PEG_CLKREQ#_R R217 1 2 0_0402_5% CLK_PCIE_CR#_R Y40 PEG_A_CLKRQ# / GPIO47 [22] CLK_PCIE_CR# short@ CLKOUT_PCIE0N R265 1 2 0_0402_5% CLK_PCIE_CR_R Y39 [22] CLK_PCIE_CR short@ CLKOUT_PCIE0P AB37 C Card reader CLKOUT_PEG_A_N C R160 2 1 10K_0402_5% CARD_CLKREQ#_R J2 AB38 CLOCKS +3V_PCH PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P R381 1 2 0_0402_5% [22] CARD_CLKREQ1# short@ R208 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI# [32] CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# [5] +3VS R212 1 short@ 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI [32] CLK_PCIE_WLAN1 short@ CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI [5] WLAN [32] WLAN_CLKREQ# R215 1 2 0_0402_5% WLAN_CLKREQ1# M1 R167 2 short@ 1 10K_0402_5% PCIECLKRQ1# / GPIO18 AM12 +3VS CLKOUT_DP_N 1 AM13 @ AA48 CLKOUT_DP_P R5019 AA47 CLKOUT_PCIE2N 10K_0402_5% +3VS CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R168 1 2 10K_0402_5% R169 2 1 10K_0402_5% PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R170 1 2 10K_0402_5% U32 +3VS 2 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P 1 8 NC VCC 1 2 7 C696 R369 1 2 0_0402_5% CLK_PCIE_LAN#_R Y37 BJ30 CLKIN_DMI2# R172 1 2 10K_0402_5% 3 NC WP 6 SMB_CLK_S3 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3 [32] PCIE_PTX_C_DRX_P2 PETP2 A12 SMB_DATA_S3 [10.2K_0402_5% 2.34] C231 1 2 0. INC.9_0402_1% Y47 XCLK_RCOMP 1 2 V40 XCLK_RCOMP XTAL25_IN V42 CLKOUT_PCIE6N CLKOUT_PCIE6P XTAL25_OUT 1 2 R190 2 1 10K_0402_5% PCH_GPIO45 T13 R187 1M_0402_5% +3V_PCH PCIECLKRQ6# / GPIO45 Y3 V38 K43 4 3 V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 NC OSC FLEX CLOCKS CLKOUT_PCIE7P F47 1 2 R193 2 1 10K_0402_5% ON_ODD_DET K12 CLKOUTFLEX1 / GPIO65 OSC NC +3V_PCH PCIECLKRQ7# / GPIO46 H47 CLK_XDP_CLK# AK14 CLKOUTFLEX2 / GPIO66 25MHZ_12PF_X3G025000DC1H~D 1 [5] CLK_XDP_CLK# CLKOUT_ITPXDP_N 1 CLK_XDP_CLK AK13 K49 DGPU_PRSNT# C236 [5] CLK_XDP_CLK CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 DGPU_PRSNT# [17] C235 15P_0402_50V8J 15P_0402_50V8J PANTHER-POINT_FCBGA989 2 2 @ R196 @ C238 33_0402_5% 22P_0402_50V8J CLK_PCI_LPBACK 2 1 1 2 A A Reserve for EMI please close to PCH AMY WEN Security Classification Compal Secret Data Compal Electronics.1U_0402_10V7K PCIE_PTX_DRX_P4 BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C232 2. 2012 Sheet 13 of 50 5 4 3 2 1 .2K_0402_5% [22] PCIE_PTX_C_DRX_N1 [22] PCIE_PTX_C_DRX_P1 C234 1 2 0.34.21. LA-8671P_SDV Date: Thursday.21. INC.A RAM 2 PETP1 SMBCLK [32] PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA +3V_PCH 1 2 +3VS 1 2 MINI CARD 5 PCIE_PRX_DTX_P2 BF34 R151 R147 WLAN [32] PCIE_PRX_DTX_P2 [32] PCIE_PTX_C_DRX_N2 C233 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK R148 1 R149 2 1 2 R150 On-board Ch.32.2K_0402_5% PETP5 3 4 EC_SMB_DA2 BJ38 EC_SMB_DA2 [33. AND CONTAINS CONFIDENTIAL PCH (2/8) PCIE.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. October 04. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT# [30] PCIE_PTX_C_DRX_N4 1 2 0. CLK AND TRADE SECRET INFORMATION. Inc.32.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 2.37] PLT_RST# PROT# SCL R370 1 2 0_0402_5% CLK_PCIE_LAN_R Y36 BG30 CLKIN_DMI2 R174 1 2 10K_0402_5% 4 5 SMB_DATA_S3 [30] CLK_PCIE_LAN short@ CLKOUT_PCIE3P CLKIN_GND1_P GND SDA 2 LAN R176 2 1 10K_0402_5% LAN_CLKREQ# A8 PCA24S08D_SO8 +3V_PCH PCIECLKRQ3# / GPIO25 R371 1 2 0_0402_5% G24 CLK_BUF_DREF_96M# R177 1 2 10K_0402_5% EEPROM SA00004MK00 [30] CLKREQ_LAN# short@ CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R178 1 2 10K_0402_5% EEPROM SA00004ML00 Y43 CLKIN_DOT_96P Y45 CLKOUT_PCIE4N CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R181 1 2 10K_0402_5% R184 2 1 10K_0402_5% PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R183 1 2 10K_0402_5% +3V_PCH PCIECLKRQ4# / GPIO26 CLKIN_SATA_P V45 K45 CLK_BUF_ICH_14M R185 1 2 10K_0402_5% V46 CLKOUT_PCIE5N REFCLK14IN CLKOUT_PCIE5P R186 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK +3V_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK [16] B B AB42 V47 XTAL25_IN AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT CLKOUT_PEG_B_P XTAL25_OUT R188 2 1 10K_0402_5% PCH_GPIO56 E6 R189 +1.

THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 1. 2012 Sheet 14 of 50 5 4 3 2 1 . AND CONTAINS CONFIDENTIAL PCH (3/8) DMI.37. INC. Size Document Number Rev AND TRADE SECRET INFORMATION.05VS_PCH BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 [4] 3 DMI_ZCOMP FDI_FSYNC0 1 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [4] R197 49. INC.5] XDP_DBRESET# PCIE_WAKE# [30] 2 SYS_RESET# WAKE# 1 2 R205 +3V_PCH 10K_0402_5% SYS_PWROK P12 N3 1 PM_CLKRUN#_R 2 R207 SYS_PWROK CLKRUN# / GPIO32 +3VS 8. 5 4 3 2 1 D D UH1C DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 [4] DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 [4] DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 [4] DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 [4] DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 [4] DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 [4] DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 [4] DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 [4] BC12 FDI_CTX_PRX_N4 FDI_RXN4 FDI_CTX_PRX_N4 [4] DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 [4] DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 [4] DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 [4] DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 [4] DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 [4] DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 [4] DMI_CTX_PRX_P3 BJ20 +3VS [4] DMI_CTX_PRX_P3 DMI3RXP BG14 FDI_CTX_PRX_P0 FDI_RXP0 FDI_CTX_PRX_P0 [4] DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 [4] DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 [4] DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 [4] DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 [4] DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 [4] DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 [4] DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 [4] DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 [4] 5 DMI FDI U2 BG12 FDI_CTX_PRX_P5 FDI_RXP5 FDI_CTX_PRX_P5 [4] DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 VCC [4] DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 [4] 1 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 [47] VGATE IN1 [4] DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 [4] 4 SYS_PWROK DMI_CRX_PTX_P2 AY18 2 OUT SYS_PWROK [5] [4] DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AU18 DMI2TXP GND [34] PCH_PWROK IN2 [4] DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT FDI_INT FDI_INT [4] +RTCVCC MC74VHC1G08DFT2G_SC70-5 +1. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. 1 T763PAD 0_0402_5% System Power Management SUSACK# C12 E22 PCH_DPWROK 2 1 PCH_RSMRST#_R R202 SUSACK# DPWROK short@ 330K_0402_5% @ K3 B9 PCIE_WAKE# [12.34.On Die DSW VR Enable PCH * H Enable L Disable SUSACK# is only used on platform A18 DSWODVREN DSWVRMEN R210 that support the Deep Sx state.FDI. Inc.PM.34] EC_RSMRST# short@ RSMRST# SLP_S4# PM_SLP_S4# [34] SUSWARN# 2 1 R214 AC_PRESENT_R SUSWARN# K16 F4 PM_SLP_S3# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# [34] 200K_0402_1% R382 0_0402_5% B R216 2 1 PCH_RSMRST#_R 2 1 PBTN_OUT#_R E20 G10 SLP_A# 2 1 B [12. Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. October 04. +3V_PCH RI# SLP_LAN# / GPIO29 @ R256 2 1 PM_DRAM_PWRGD R220 200_0402_5% 10K_0402_5% PANTHER-POINT_FCBGA989 +3VS @ R268 2 1 200_0402_5% A A AMY WEN Security Classification Compal Secret Data Compal Electronics. LA-8671P_SDV Date: Thursday.40] ACIN ACPRESENT / GPIO31 SLP_SUS# SBA@ RB751V_SOD323 2 1 PCH_GPIO72 E10 AP14 H_PM_SYNC BATLOW# / GPIO72 PMSYNCH H_PM_SYNC [5] R219 +3V_PCH 10K_0402_5% Can be left NC if no use 2 1 RI# A10 K14 PCH_GPIO29 PAD T771 integrated LAN. INC.5] PBTN_OUT# short@ PWRBTN# SLP_A# PCH_SLPA# [34] 10K_0402_5% R221 0_0402_5% 1 2 D1 AC_PRESENT_R H20 G16 PM_SLP_SUS# PAD T766 [34.9_0402_1% R198 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 330K_0402_5% C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [4] C R199 750_0402_1% R200 4mil width and place BB10 FDI_LSYNC1 :: FDI_LSYNC1 [4] 2 2 1 100K_0402_1% SYS_PWROK FDI_LSYNC1 within 500mil of the DSWODVREN .2K_0402_5% PCH_PWROK L22 G8 SUS_STAT# PAD T767 NOSBA@ PWROK SUS_STAT# / GPIO61 R5070 0_0402_5% 2 1 2 1 R209 APWROK L10 N14 SUSCLK [34] PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK [34] +3V_PCH SBA@ 0_0402_5% Can be left NC when IAMT is not PM_DRAM_PWRGD B13 D10 PM_SLP_S5# support on the [5] PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# [34] R279 0_0402_5% platfrom R213 2 1 PCH_RSMRST#_R C21 H4 PM_SLP_S4# 2 1 10K_0402_5% [12.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.

1U_0402_10V6K LVDSB_CLK DDPC_AUXN PCH_DPC_AUXN_C [25] AP49 PCH_DPC_AUXP C244 1 2 0.37K_0402_1% AF36 M39 HDMIDAT_NB LVD_VBG SDVO_CTRLDATA HDMIDAT_NB [24] AE48 AE47 LVD_VREFH AT49 LVD_VREFL DDPB_AUXN AT47 DDPB_AUXP AT40 TMDS_B_HPD Near Conn.1U_0402_10V6K R5115 R5147 [23] LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK [24] [23] LVDS_A1 LVDSA_DATA1 2.1U_0402_10V6K [23] LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH 1 2 HDMI_TX1-_CK [24] [23] LVDS_A1# LVDSA_DATA#1 DDPB_1P C538 0.2K_0402_5% CTRL_DATA P39 L_CTRL_CLK L_CTRL_DATA RF Request R227 2 1 LVDS_IBG AF37 P38 HDMICLK_NB LVD_IBG SDVO_CTRLCLK HDMICLK_NB [24] 2.1U_0402_10V6K AH49 LVDSB_DATA0 DDPC_1P BA47 1 2 PCH_DPC_DP_P1 [25] PCH_DPC_N2_C C541 0.1U_0402_10V6K LVDSB_DATA#3 DDPC_0P AY43 1 2 PCH_DPC_DP_P0 [25] PCH_DPC_N1_C C545 0.1U_0402_10V6K DDPC_3P PCH_DPC_DP_P3 [25] N48 M43 P49 CRT_BLUE DDPD_CTRLCLK M36 Near Conn. AK39 DDPB_HPD TMDS_B_HPD [24] [23] LVDS_ACLK# LVDSA_CLK# LVDS AK40 AV42 TMDS_B_DATA2#_PCH C295 1 2 0.1U_0402_10V6K AN47 DDPB_3N AV49 TMDS_B_CLK_PCH 1 2 HDMI_CLK-_CK [24] C536 0.2K_0402_5% AK49 [23] LVDS_A2 AJ47 LVDSA_DATA2 P46 PCH_DPC_CLK PCH_DPC_CLK [25] 1 1 LVDSA_DATA3 DDPC_CTRLCLK P42 PCH_DPC_DAT DDPC_CTRLDATA PCH_DPC_DAT [25] AF40 Near Q2208 PCH_DPC_CLK AF39 LVDSB_CLK# AP47 PCH_DPC_AUXN C245 1 2 0. INC.1U_0402_10V6K AF43 LVDSB_DATA2 DDPC_2P BB47 PCH_DPC_N3_C 1 2 PCH_DPC_DP_P2 [25] C543 0. 5 4 3 2 1 PORT STRAP LVDS L_DDC_DATA PORT B SDVO_CTRLDATA D PORT C DDPC_CTRLDATA D +3VS [34] ENBKL PORT D DDPD_CTRLDATA 2 R494 1 1 100K_0402_1% R5020 R5021 2.DP. T49 CRT_GREEN DDPD_CTRLDATA CRT_RED AT45 DDPD_AUXN CRT T39 AT43 M40 CRT_DDC_CLK DDPD_AUXP BH41 CRT_DDC_DATA DDPD_HPD B BB43 B M47 DDPD_0N BB45 M49 CRT_HSYNC DDPD_0P BF44 CRT_VSYNC DDPD_1N BE44 DDPD_1P BF42 CRT_IREF T43 DDPD_2N BE42 T42 DAC_IREF DDPD_2P BJ42 CRT_IRTN DDPD_3N BG42 DDPD_3P 1 PANTHER-POINT_FCBGA989 R5029 1K_0402_1% 2 A A AMY WEN Security Classification Compal Secret Data Compal Electronics.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.HDMI AND TRADE SECRET INFORMATION.1U_0402_10V6K [23] LVDS_ACLK LVDSA_CLK DDPB_0N AV40 TMDS_B_DATA2_PCH 1 2 HDMI_TX2-_CK [24] C294 0.2K_0402_5% 2.1U_0402_10V6K AF45 LVDSB_DATA#2 DDPC_0N AY49 PCH_DPC_P0_C 1 2 PCH_DPC_DP_N0 [25] C242 0.2K_0402_5% CTRL_CLK T45 SDVO_INTP +3VS 2 2 R5023 1 2 2. INC. October 04.1U_0402_10V6K LVDSB_DATA3 DDPC_3N BB49 1 2 PCH_DPC_DP_N3 [25] PCH_DPC_P3_C C542 0. Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS.1U_0402_10V6K AH43 DDPC_1N AY45 1 2 PCH_DPC_DP_N1 [25] PCH_DPC_P1_C C544 0.2K_0402_5% 2. INC. 2012 Sheet 15 of 50 5 4 3 2 1 .1U_0402_10V6K PCH_DPC_DAT DDPC_AUXP PCH_DPC_AUXP_C [25] AH45 AT38 DPC_HPD AH47 LVDSB_DATA#0 DDPC_HPD DPC_HPD [25] AF49 LVDSB_DATA#1 AY47 PCH_DPC_N0_C C243 1 2 0. LA-8671P_SDV Date: Thursday. AND CONTAINS CONFIDENTIAL PCH (4/9) LVDS.1U_0402_10V6K HDMI_TX1+_CK [24] HDMI Digital Display Interface C AK47 AU48 TMDS_B_DATA0#_PCH C535 1 2 0. Inc.2K_0402_5% [23] EDID_DATA L_DDC_DATA SDVO_INTN AP40 22P_0402_50V8J 22P_0402_50V8J 2 2 R5022 1 2 2.2K_0402_5% 1 UH1D ENBKL J47 AP43 +3VS 2 2 PCH_ENVDD M45 L_BKLTEN SDVO_TVCLKINN AP45 EDID_CLK [23] PCH_ENVDD L_VDD_EN SDVO_TVCLKINP EDID_DATA PCH_PWM P45 AM42 [23] PCH_PWM L_BKLTCTL SDVO_STALLN 1 1 1 1 AM40 @ @ EDID_CLK T40 SDVO_STALLP R5060 R5059 [23] EDID_CLK K47 L_DDC_CLK AP39 C88 C87 EDID_DATA 2. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS.1U_0402_10V6K AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCH 1 2 HDMI_TX2+_CK [24] +3VS C539 0.2K_0402_5% 2.CRT.1U_0402_10V6K C [23] LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH 1 2 HDMI_TX0-_CK [24] C534 0.1U_0402_10V6K LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK [24] 2 2 AV47 TMDS_B_CLK#_PCH C537 1 2 0. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev Custom 1.1U_0402_10V6K DP AF47 LVDSB_DATA1 DDPC_2N BA48 PCH_DPC_P2_C 1 2 PCH_DPC_DP_N2 [25] C540 0.

USB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. AMY WEN Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title PCH (5/9) PCI. INC.2K_0402_5% ODD_DA# AH12 TP12 RSVD12 AV3 R244 1 2 8.2K_0402_5% DGPU_PWR_EN_R N30 TP10 RSVD10 AY3 R242 1 2 8.0 NOTE R5067 1 2 8.0 Conn @ BE32 BF3 [27] USB3_RX3_N USB3Rn3 RSVD29 BJ32 USB DEBUG=PORT1 AND PORT9 BC28 USB3Rn4 USB3Rp1 4 3 BE30 [26] USB3_RX2_P USB3Rp2 BF32 [27] USB3_RX3_P USB3Rp3 WL_OFF# R5033 1 @ 2 1K_0402_5% BG32 C24 4 Sensor Hub AV26 USB3Rp4 USBP0N A24 BB26 USB3Tn1 USBP0P C25 USB20_N1 C [26] USB3_TX2_N AU28 USB3Tn2 USBP1N B25 USB20_P1 USB20_N1 [26] C [27] USB3_TX3_N AY30 USB3Tn3 USBP1P C26 USB20_N2 USB20_P1 [26] USB2 (USB3 COMBO) 5 USB Camera A16 swap overide Strap/Top-Block USB3Tn4 USBP2N USB20_N2 [27] Swap Override jumper AU26 A26 USB20_P2 USB2 (USB3 COMBO) AY26 USB3Tp1 USBP2P K28 USB20_P2 [27] [26] USB3_TX2_P USB3Tp2 USBP3N 6 X Low=A16 swap AV28 H28 [27] USB3_TX3_P AW30 USB3Tp3 USBP3P E28 USB20_N4 override/Top-Block USB3Tp4 USBP4N USB20_N4 [21] PCI_GNT3# Swap Override enabled D28 USB20_P4 Sensor Hub 7 High=Default * USBP4P C28 USB20_N5 USB20_P4 [21] X USBP5N A28 USB20_P5 USB20_N5 [23] USBP5P C29 USB20_P5 [23] Camera USBP6N 8 Touch Panel B29 PCI_PIRQA# K40 USBP6P N28 PIRQA# USBP7N Port6.2K_0402_5% PCI_PIRQB# BG16 TP4 RSVD5 BC8 AH38 TP5 RSVD6 AH37 TP6 AU2 AK43 TP7 RSVD7 AT4 D AK45 TP8 RSVD8 AT3 D C18 TP9 RSVD9 AT1 R240 1 2 8. October 04.37] PLT_RST# Y 1 1 2 @ @ USB_OC4# R80 10K_0402_5% A G C5115 C5116 1 12P_0402_50V8J 12P_0402_50V8J @ 3 1 C5037 R5039 1U_0402_6. 5 4 3 2 1 UH1E +3VS AY7 RSVD1 AV7 BG26 RSVD2 AU3 R236 1 2 8.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS.0/2.2K_0402_5% PCI_PIRQA# BJ26 TP1 RSVD3 BG4 R237 1 2 8. 2012 Sheet 16 of 50 5 4 3 2 1 .32.2K_0402_5% TB_Force_PWR B21 AV5 R5031 1 2 8.30.2K_0402_5% PCI_PIRQC# BJ16 TP3 AT10 R239 1 2 8. INC.21. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev Custom 1.0/2.2K_0402_5% PCH_GPIO51 BG46 AT8 TP24 RSVD25 R5072 1 2 8. Port7 HM76 doesn't support PCI_PIRQB# K38 M28 9* WWAN PIRQB# USBP7P PCI PCI_PIRQC# H38 L30 USB20_N8 PCI_PIRQD# G38 PIRQC# USBP8N K30 USB20_P8 USB20_N8 [23] PIRQD# USBP8P G30 USB20_P8 [23] Touch Panel USBP9N USB20_N9 [32] 10 WLAN DGPU_HOLD_RST#_R C46 E30 WWAN REQ1# / GPIO50 USBP9P USB20_P9 [32] USB DGPU_PWR_EN1 C44 C30 USB20_N10 E40 REQ2# / GPIO52 USBP10N A30 USB20_N10 [32] DGPU_PWR_EN_R USB20_P10 WLAN 11 Finger Printer** REQ3# / GPIO54 USBP10P L32 USB20_P10 [32] PCH_GPIO51 D47 USBP11N K32 PCH_GPIO53 E42 GNT1# / GPIO51 USBP11P G32 GNT2# / GPIO53 USBP12N 12 WL_OFF# F46 E32 GNT3# / GPIO55 USBP12P C32 USBP13N A32 USBP13P 13 Bluetooth** POUT1# G42 [36] POUT1# PIRQE# / GPIO2 ODD_DA# G40 Default: Active Low POUT2# C42 PIRQF# / GPIO3 C33 USBRBIAS 1 2 [37] POUT2# PIRQG# / GPIO4 USBRBIAS# * Debug Port TB_Force_PWR D44 R5034 22.2K_0402_5% WL_OFF# L24 TP17 RSVD17 BB3 AB46 TP18 RSVD18 BB7 AB45 TP19 RSVD19 BE8 1 2 8. LA-8671P_SDV Date: Thursday. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.2K_0402_5% POUT1# AM4 TP13 RSVD13 AV1 AM5 TP14 RSVD14 BB1 Y13 TP15 RSVD15 BA3 K24 TP16 RSVD16 BB5 R235 1 2 8.3V4Z 100K_0402_5% 2 @ MC74VHC1G08DFT2G SC70 5P 2 A A Security Classification Compal Secret Data Compal Electronics.2K_0402_5% PCI_PIRQD# BH25 TP2 RSVD4 R238 1 2 8.2K_0402_5% POUT2# H3 TP11 RSVD11 AT5 R243 1 2 8.0 USB2.2K_0402_5% DGPU_HOLD_RST#_R M20 TP21 RSVD23 AV10 AY16 TP22 RSVD24 TP23 1 0 R5064 1 2 8.6_0402_1% PIRQH# / GPIO5 ** Not Use B33 K10 USBRBIAS B [34] PCI_PME# PME# B PCH_PLTRST# C6 A14 USB_OC0# [36.22.34.5] PCH_PLTRST# PLTRST# OC0# / GPIO59 K20 USB_OC1# USB_OC0# [26] OC1# / GPIO40 B17 USB_OC2# USB_OC1# [27] R5035 1 2 22_0402_5% CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3# [13] CLK_PCI_LPBACK 1 2 CLK_PCI_EC_R H43 CLKOUT_PCI0 OC3# / GPIO42 L16 USB_OC4# R5036 22_0402_5% [34] CLK_PCI_EC 2 1 J48 CLKOUT_PCI1 OC4# / GPIO43 A16 R384 22_0402_5% CLK_PCI_DB_R USB_OC5# [37] CLK_PCI_DB 2 1 CLK_PCI_TPM_R K42 CLKOUT_PCI2 OC5# / GPIO9 D14 USB_OC6# R390 22_0402_5% [36] CLK_PCI_TPM H40 CLKOUT_PCI3 OC6# / GPIO10 C14 PCH_GPIO14 CLKOUT_PCI4 OC7# / GPIO14 +3V_PCH PANTHER-POINT_FCBGA989 USB_OC5# R35 1 2 10K_0402_5% USB_OC2# R40 1 2 10K_0402_5% PCH_GPIO14 R47 1 2 10K_0402_5% 1 2 USB_OC0# R48 1 2 10K_0402_5% R5038 RF Request 0_0402_5% +3VS CLK_PCI_EC CLK_PCI_LPBACK 5 U8 USB_OC6# R74 1 2 10K_0402_5% 2 PCH_PLTRST# USB_OC1# R76 1 2 10K_0402_5% P 4 B USB_OC3# R77 1 2 10K_0402_5% [13.0 Conn RSVD26 BA2 R5032 1 2 8.2K_0402_5% PCH_GPIO53 AY5 2 1* USB3.2K_0402_5% DGPU_HOLD_RST#_R BE28 RSVD27 BC30 USB3Rn1 AT12 [26] USB3_RX2_N USB3Rn2 RSVD28 3 2 USB3.2K_0402_5% TP20 RSVD20 BD4 RSVD R5030 DGPU_PWR_EN1 RSVD21 BF6 RSVD22 USB3. INC. Inc.

2012 Sheet 17 of 50 5 4 3 2 1 . October 04. PA0_WAKEUP R5045 1 2 10K_0402_5% PCH_GPIO37 M5 [21] PA0_WAKEUP +3VS SATA3GP / GPIO37 @ PCH_GPIO38 N2 P37 SLOAD / GPIO38 NC_1 3G_OFF# R277 1 2 10K_0402_5% 3G_OFF# M3 [32] 3G_OFF# SDATAOUT0 / GPIO39 RAM_ID3 V13 BG2 SDATAOUT1 / GPIO48 VSS_NCTF_15 RAM_ID3 RAM_ID2 RAM_ID1 RAM_ID0 R5047 1 2 10K_0402_5% PCH_GPIO49 V3 BG48 RAM SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16 GPIO48 GPIO16 GPIO70 GPIO71 R281 1 2 10K_0402_5% PCH_GPIO57 D6 BH3 +3V_PCH GPIO57 VSS_NCTF_17 @ BH47 R5050 VSS_NCTF_18 0 0 0 0 ELPIDA 4GB 10K_0402_5% T81 PAD A4 BJ4 PAD T64 1 2 mSATA_PCH VSS_NCTF_1 VSS_NCTF_19 [34] mSATA_DETEC# A44 BJ44 0 0 0 1 SAMSUNG 4GB VSS_NCTF_2 VSS_NCTF_20 R5051 T78 PAD A45 BJ45 PAD T62 0_0402_5% VSS_NCTF_3 VSS_NCTF_21 0 0 1 0 HYNIX 4GB 1 2 A46 BJ46 NCTF mSATA_PCH T79 PAD PAD T63 [32] mSATA_DET# short@ VSS_NCTF_4 VSS_NCTF_22 T84 PAD A5 BJ5 PAD T68 0 0 1 1 ELPIDA 8GB B VSS_NCTF_5 VSS_NCTF_23 B A6 BJ6 PCH_WLBT_OFF_51# VSS_NCTF_6 VSS_NCTF_24 0 1 0 0 SAMSUNG 8GB [32] PCH_WLBT_OFF_51# B3 C2 VSS_NCTF_7 VSS_NCTF_25 3G_DET# B47 C48 0 1 0 1 HYNIX 8GB [32] 3G_DET# VSS_NCTF_8 VSS_NCTF_26 BD1 D1 PAD T72 VSS_NCTF_9 VSS_NCTF_27 0 1 1 0 ELPIDA 2GB BD49 D49 PAD T73 VSS_NCTF_10 VSS_NCTF_28 R5063 T86 PAD BE1 E1 PAD T70 0 1 1 1 SAMSUNG 2GB 10K_0402_5% VSS_NCTF_11 VSS_NCTF_29 1 2 PCH_GPIO37 T116 PAD BE49 E49 PAD T71 VSS_NCTF_12 VSS_NCTF_30 1 0 0 0 HYNIX 2GB T76 PAD BF1 F1 VSS_NCTF_13 VSS_NCTF_31 T77 PAD BF49 F49 1 0 0 1 TBD VSS_NCTF_14 VSS_NCTF_32 PANTHER-POINT_FCBGA989 1 0 1 0 TBD +3VS 1 0 1 1 TBD 1 1 0 0 TBD PCH_GPIO69 PCH_GPIO38 PCH_GPIO67 Function GPU_ID 1 1 R5167 R5179 1 1 0 1 TBD 10K_0402_5% 10K_0402_5% A 0 0 0 PX4. AND CONTAINS CONFIDENTIAL PCH (6/9) GPIO. Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title 2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS. MISC Size Document Number Rev AND TRADE SECRET INFORMATION. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 1.5] 0_0402_5% R263 DDR1@ DDR1@ SATA4GP / GPIO16 P5 KB_RST# KB_RST# [34] 2 2 RAM_ID3 RAM_ID2 RCIN# GPIO R404 1 2 10K_0402_5% DGPU_PWROK D40 AY11 +3VS TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD [5] 1 1 CPU/MISC R5049 R267 R5041 1 2 10K_0402_5% PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 1 2 H_THERMTRIP# +3VS SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# [5] 10K_0402_5% 10K_0402_5% R269 390_0402_5% R5073 1 2 10K_0402_5% PCH_GPIO24 E8 T14 +3V_PCH GPIO24 INIT3_3V# DDR1@ DDR1@ INIT3_3V 2 2 R5074 1 @ 2 10K_0402_5% mSATA_PCH E16 AY1 NV_CLE C +3V_PCH GPIO27 DF_TVS C This signal has weak internal 1 R5043 2 10K_0402_5% PCH_GPIO28 P8 PU.0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS. INC.2K_0402_5% KB_RST# R266 1 2 10K_0402_5% @ DDR1@ DDR1@ R241 PCH_GPIO69 GPIO28 1 On-Die PLL Voltage Regulator NV_CLE 1 2 D H_SNB_IVB# [5] D This signal has a weak internal pull up ODD_EN# 2 1 1K_0402_5% RAM_ID1 * H L ::On-Die voltage regulator enable On-Die PLL Voltage Regulator disable R1942 10K_0402_5% CLOSE TO THE BRANCHING POINT RAM_ID0 R5042 1 @ 2 1K_0402_5% PCH_GPIO28 UH1F R253 1 2 10K_0402_5% PCH_GPIO0 T7 C40 ODD_EN# +3VS BMBUSY# / GPIO0 TACH4 / GPIO68 R1945 R1947 R5040 10K_0402_5% 10K_0402_5% 10K_0402_5% R257 1 2 10K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69 TACH1 / GPIO1 TACH5 / GPIO69 2 2 2 R258 1 2 10K_0402_5% PA0_WAKEUP H36 C41 RAM_ID1 +3VS TACH2 / GPIO6 TACH6 / GPIO70 EC_SCI# E38 A40 RAM_ID0 [34] EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71 2 1 1 1 EC_SMI# C10 R260 DDR1@ DDR1@ +3VS +3VS [34] EC_SMI# GPIO8 10K_0402_5% R261 1 2 10K_0402_5% PCH_GPIO12 C4 +3V_PCH LAN_PHY_PWR_CTRL / GPIO12 1 1 1 R262 1 2 1K_0402_5% EC_LID_OUT# G2 P4 GPIO15 A20GATE GATEA20 [34] R5046 R264 @ 10K_0402_5% 10K_0402_5% AU16 PCH_PECI_R 1 @ 2 RAM_ID2 U2 PECI H_PECI [34. CPU. can't pull low +3V_PCH GPIO28 AH8 1 R5044 2 10K_0402_5% PCH_BT_ON# K1 TS_VSS1 +3VS STP_PCI# / GPIO34 AK11 1 R273 2 10K_0402_5% 3G_DET# K4 TS_VSS2 EC_LID_OUT# GPIO35 AH10 [34] EC_LID_OUT# 1R5048 @ 2 10K_0402_5% V8 TS_VSS3 PCH_WLBT_OFF_51# SATA2GP / GPIO36 AK10 TS_VSS4 Intel schematic reviwe recommand.8VS Weak internal pull-high