# CMOS INVERTER

VINOD PATIL

VIT UNIVERSITY

VELLORE

Aim: Performing CMOS inverter using cadence simulator and observe the following plots and
interpretations

a) Variation of switching threshold VM for different strength of PMOS.

b) Variation of gain for the VTC of an inverter

CMOS Inverter:

CMOS Inverter charactristics:
Vtn Vdd/2 Vdd-|Vtp| Vdd

condition PMOS NMOS O/P
0 < Vin < Vtn resistive cutoff Vout=Vdd
Vtn ≤ Vin < Vdd/2 resistive saturation Vout>Vdd/2
Vin=Vdd/2 saturation saturation Vout drops sharply
Vdd/2<Vin≤Vdd-|Vtp| saturation resistive Vout<Vdd/2
Vin > Vdd-|Vtp| cutoff resistive Vout=0

Switching threshold: the switching threshold VM is defined as the point where Vin=Vout. its value
can be obtained graphically from the intersection of the VTC with line.in this region both nmos and
pmos are always saturated.
VM

An analytical expression for VM is obtained by equating the currents through the transisters.here we
ignore channel length modulation

kn VDSATn (VM - Vtn-VDSATn/2) + kp VDSATp( VM - Vdd- Vtp - VDSATn/2) = 0 (1)

Solving,

VM = (Vtn + Vdsatn/2)+ r(Vdd + Vtp + Vdsatp/2) (2)

1+r

Where, r = (kp.Vdsatp/Kn.Vdsatn) i.e ( Vsatp.Wp/Vsatn.Wn) For large values of Vdd eq (2)
simplified as,

VM =( rVdd/1+r) (3)

Equation 3. states that the switching threshold is set by the ratio r.

To move VM upwards,a larger value of r is required ,which means making the pmos wider.

VM2
VM3
On the other hand ,increases the strength of the nmos ,moves the VM closer to ground

1) VM is relatively insensitive to variations in the device ratio. This means that small variations of the
ratio do not disturb the transfer characteristic that much.

2)The effect of changing the Wp /Wn ratio is to shift the transient region of the VTC. Increasing the
width of the PMOS or the NMOS moves VM towards VDD or GND respectively.
b) Variation of gain for the VTC of an inverter

Scaling of supply voltage:

Reducing the Vdd improves the gain but at the same time at very low supply voltages gain
detoriates.so set the lower bound on supply scaling and lower bound is,

Vdd>2….4kT/q

Transient analysis:
Properties of CMOS inverter:

1. Voltage swing is equal to supply voltage
2. High noise margin
3. Low output impedance
4. High input resistance

Conclusion: from this experiment we studied CMOS inverter and its characteristics. We also seen
effect of changing Vdd or pmos width on characteristics. and seen important properties of CMOS
inverter