Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN

:
2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.647-654

Design of Two-Stage CMOS Op-Amp and Analyze the Effect of
Scaling
Amana Yadav
Department of Electronics and Communication Engineering, FET-MRIU, Faridabad, Haryana

Abstract:-
A method described in this paper is to worldwide sales is dominated by MOS market. CMOS
design a Two Stage CMOS operational amplifier technology continues to mature with minimum feature
and analyze the effect of various aspect ratios on sizes now. Designing high performance analog
the characteristics of this Op-Amp, which operates integrated circuits is becoming increasingly exigent
at 5V power supply using tsmc 0.35µm CMOS with the relentless trend toward reduced supply
technology. In this paper trade-off curves are voltages and transistor channel length. A large part of
computed between all characteristics such as Gain, the success of the MOS transistor is due to the fact that
PM, GBW, ICMRR, CMRR, Slew Rate etc. The it can be scaled to increasingly smaller dimensions,
OPAMP designed is a two-stage CMOS OPAMP. which results in higher performance. The feature size
The OPAMP is designed to exhibit a unity gain of individual transistor is shrinking from deep sum-
frequency of 14MHz and exhibits a gain of 77.25dB micrometer (DSM) to even nanometer region. As the
with a 85.850 phase margin. Design has been scale of integration improves, more transistors, faster
carried out in Mentor graphics tools. Simulation and smaller than their predecessors, are being packed
results are verified using Model Sim Eldo and into a chip. This leads to the steady growth of the
Design Architect IC. operating frequency and processing capacity per chip.
The task of CMOS operational amplifiers (Op-
Amps) design optimization is investigated in this Operational Amplifier is the most common
work. This Paper focused on the optimization of building blocks of most of the electronics system may
various aspect ratios, which gave the result of not need introduction. The design of OPAMPs
different parameter. When this task is analyzed as continues to pose a challenge as the supply voltage
a search problem, it can be translated into a multi- and transistor channel lengths scale down with each
objective optimization application in which various generation of CMOS technologies. At different aspect
Op-Amps’ specifications have to be taken into ratio, there is a tradeoff among speed, power, gain and
account, i.e., Gain, GBW (gain-bandwidth other performance parameters. The realization of a
product), phase margin and others. The results are CMOS OPAMP that combines a considerable dc gain
compared with respect to standard characteristics with high unity gain frequency has been a difficult
of the op-amp with the help of graph and table. problem. There have been several circuit approaches
Simulation results agree with theoretical to evade this problem.
predictions. Simulations confirm that the settling
time can be further improved by increasing the The aim of the design methodology in this
value of GBW, the settling time is achieved 19ns, paper is to propose straightforward yet accurate
gain is 77.25dB and a value of phase margin is equations for the design of high-gain 2 staged CMOS
73.30. It has been demonstrated that when W/L op-amp. To do this, a simple analysis with some
increases the parameters GBW increases and meaningful parameters (phase margin, gain-
settling time reduces. bandwidth, etc.) is performed. The method handles a
very wide variety of specifications and constraints. In
Keywords this paper, we formulate the CMOS op-amp design
CMOS Analog Circuit, 2 stage CM OS problem and their aspect ratios. The method we
Operational amplifier, Stability, GBW, Device Design, present can be applied to a wide variety of amplifier
Scale Length, Scaling, Differential Amp. architectures, but in this paper we apply the method to
a specific two stage CMOS op-amp. The variation in
I. Introduction the performance of the op-amp with variations in the
Over the last few years, the electronics width and length of the CMOS and the effect of
industry has exploded. The largest segment of total scaling the gate oxide thickness is discussed.

647 | P a g e

If the op-amp is application in several analog circuit such as switched intended to drive a small purely capacitive load. higher the speed and accuracy of purpose of the compensation circuit is lower the gain the amplifier Op-amp are a critical element in analog at high frequencies and to maintain stability when sampled data circuit. (phase margin) and slew-rate.647-654 The simulation results have been obtained by tsmc 0. also gives the formula or calculation for unbalanced output differential amplifier. Op-Amps are one of the moreover. most of the transistors’ size still needed to be modified in order to optimize the performance. larger output current needed to drive the load of op- amp or improves the slew rate of the op –amp.ijera. establish the proper operating point for each transistor amp. It devices are increased with the bias voltages held has two inputs which are the inverting and non- constant. the slew rate permitted by the gain stage basic and important circuits which have a wide can be sufficient for the application. the is used to transform the differential signal generated device is in the short channel regime and will require by the first block into a single ended version. therefore the block can be excluded. tables and graphs for optimization technique. architecture doesn’t require the differential to single ended function. the slew rate will increase for an increase in current. Scaling effects are analyzed through experimental data and computer simulations. The As such.October 2012. The bandwidth and gain. It length (350 nm) will be used. for the fastest slew-rate. OTA. algorithmic. Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www. Section IV required extra gain. so it provide designing of 2 stage CMOS Op-amp. modulators. Figure 1. Some short channel topologies. Design has been carried out in Mentor Graphics tool. it is an the bandwidth and DC gain of the Op-amp. Finally. The speed and accuracy of these circuits depends on When the output stage is not used the circuit. the smallest channel next block is a differential to single-ended converter. depends on the differential input only. September. Even II. we have the output Section V gives the scaling and finally section VI buffer stage. This search technique can be successfully applied to a class of optimization problems. if the widths of the The first block is a differential amplifier. However. Outline of paper In most cases the gain provided by the input stages is This paper composed this work. such as SC filters. pp. Block diagram of two stage CMOS op-amp the output stage can be dropped: many integrated Operational Amplifiers are the backbone for applications do not need low output impedance. Section III reviews the 2 stage CMOS another differential amplifier. negative feedback is applied to the op amp. Thus. Larger the operational transconductance amplifier. After the simulation. High gain in operational amplifiers is not the only desired figure of merit for all kind of signal processing applications. conversion applications. discusses the 2 stage amplifier and design This is provided by intermediate stage. It provides at the output a device sizes depends on trade-offs between stability differential voltage or a differential current that. which is optimization. The general block diagram of an op-amp with an output buffer is shown below 648 | P a g e . 2. Its specifications are briefly the first stage. Block diagram of Op-Amp In this case. As this stage uses differential input clarified. many analog circuit designs. pipelined and sigma is the case in many switched capacitor or data delta A/D converter. we can conclude that the selection of inverting voltage. essentially. sample and hold amplifier etc. Simultaneously optimizing all parameters has become mandatory now a day in operational amplifier design. in its saturation region. Section II not sufficient and additional amplification is required. The bias circuit is provided to presents the simulation results of the proposed op.com Vol.35 micron CMOS technology. which capacitor filters. Simulation results are verified using Model Sim Eldo and Design Architect IC. the output buffer is not used. It provides the low output impedance and concludes this work. Issue 5. and at this length. driven by the output of Op-amp schematic design.

8V also helps with common mode rejection ratio. D. The two main resistances that contribute to the output resistance are Table1. and M4 form the connected to ensure they operate in the saturation first stage of the op amp the differential amplifier with region. The biasing of the operational amplifier is circuit. It comprised of three subsections of second gain stage.5 – 2. M8 and M9 are diode Transistors M1. similar to the differential gain stage. differential input signal applied across the two input terminals will be amplified according to the gain of the III. Differential Gain Stage is controlled by the bias string. The differential The final circuit designed to meet the current from M1 and M2 multiplied by the output required specifications is shown in Figure 2. 2. and M6. Circuit Operation subtracted from the current from M2. this stage employs an active device. Issue 5. They appear in Table 1 resistance seen at the drain of M2.647-654 A. the conversion from differential to single ended Output Swing 1 – 2. M6 is the driver while M7 acts as the load. Most importantly. Design of the op-amp differential stage. First. It was found that this topology and M9 form a simple current mirror bias string that was able to successfully meet all of the design supplies a voltage between the gate and source of M7 specifications. The gain of the stage is simply the The first aspect considered in the design was transconductance of M2 times the total output the specifications to be met. Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www. output voltage.October 2012. M6. Transistors circuit (M1-M5) is controlled by the node voltages M1 and M2 are standard N channel MOSFET present in the circuit itself. Bias String Figure2. Transistors M6 and M7 sink a certain amount of current based on their gate to source voltage which B. pp. namely differential gain stage.8V is achieved by using a current mirror (M3 and M4). The current mirror active load used in this circuit Supply VDD 5V has three distinct advantages. Transistors M8 stage and bias strings. In this Common mode rejection ratio ≥60dB stage. Consisting of transistors M5 and M6. the use of active Gain ≥ 70dB load devices creates a large output resistance in a Gain Bandwidth 10MHz relatively small amount of die area. The gain of this stage is the transconductance of M5 times the effective load resistance comprised of the output resistances of M5 and M6. The purpose of the second gain stage. The gate of M1 is the inverting input the VGS of the current mirror load as are the and the gate of M2 is the non-inverting input. Second Gain Stage The second stage is a current sink load inverter.com Vol. A transistors M1 and M2. as the name implies. Offset ≤10m The current from M1 is mirrored by M3 and M4 and 649 | P a g e . M3. second gain achieved with only four transistors. Custom Design Specifications of the amplifier that of the input transistors themselves and also the output resistance of the active load transistors. to serve as the load resistance for M5. C. and finally. M3 and Specification Names Values M4. The resistance of the first stage gives the single-ended topology of this circuit is that of a standard CMOS op.ijera. M5 is (NMOS) transistors which form the basic input stage biased by the gate to source voltage (VGS) set up by of the amplifier. is to provide additional gain in the amplifier. The current mirror Settling Time 1u Sec topology performs the differential to single-ended Slew Rate 10V/uSec conversion of the input signal. the load Input common Mode Range 1. The topology chosen for this Op-Amp design. which constitutes the input of the amp. M2. Again. this stage takes the output from the drain of M2 and amplifies it through M5 which is in the standard common source configuration. September. Proper biasing of the other transistors in the differential to single ended transformation.

Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www. Simulation results It is assumed that all transistors are in saturation for To analyze the behavior of variations in the above relationships.1 Determine the necessary open-loop gain (Ao) gm1 = gm2 = gmI. so it RHP zero 𝑍1= (9) is commonly called as large signal voltage gain. 𝛽1 𝑉𝑇1 (max) + VDS 5 (sat) (11) CMRR: Common Mode Rejection ratio is the ratio 2𝐼𝐷𝑆 between differential gain and common mode gain. Issue 5. capacitance. September. Schematic design of 2 stage CMOS Op- 𝑔𝑚 1 Gain Bandwidth GB = (7) Amp 𝐶𝐶 −𝑔𝑚 6 Open Loop Gain: It is the ratio between output Output pole 𝑝2= (8) 𝐶𝐿 voltage and differential input voltage.ijera. gm6 = gmII. Gain can swing above and below ground and also be and GB of the OP-Amp. aspect ratios. Design Methodology of Op-amp and for the circuit analysis in Model Sim Eldo of Mentor Graphic Tool.𝑝 𝐶𝑜𝑥 𝑉𝑒𝑓𝑓 2 𝐿 𝐼𝑑 = 2 (1) 𝑊 gm = 2𝜇𝑛.𝑝 𝐶𝑜𝑥 𝐼𝑑 (2) 𝐿 𝐼𝑑 gm = 2 𝑉 (3) 𝑒𝑓𝑓 𝐼5 Slew rate 𝑆𝑅 = 𝐶𝐶 (4) −𝑔𝑚 1 −2𝑔𝑚 1 First stage gain 𝐴𝑣1 = = (5) 𝑔𝑑𝑠 2 +𝑔𝑑𝑠 4 𝐼5 (𝜆 2 + 𝜆 4 ) −𝑔𝑚 6 Second stage gain 𝐴𝑣2 = 𝑔𝑑𝑠 = 6 +𝑔𝑑𝑠 7 −𝑔𝑚 6 (6) 𝐼6 (𝜆 6 + 𝜆 7 ) Figure 3. 𝐼5 Rise Time: the time required by the output to go from Negative CMR 𝑉𝑖𝑛 (min) = 𝑉𝑆𝑆 + + 10% to 90% of its final value is called the rise time. 𝐶𝐶 𝐼5 Slew Rate: The maximum rate of change of output Positive CMR 𝑉𝑖𝑛 (max) = 𝑉𝐷𝐷 − − voltage per unit time.1. Saturation voltage 𝑉𝐷𝑆 (sat) = (12) 𝛽 IV. The op amp uses a dual. gds2 + gds4 = GI. 2. and gds6 + gds7 = GII 𝑊 𝜇 𝑛 .Analysis we determine Phase margin. pp.com Vol. AC Analysis polarity power supply (Vdd and Vss) so the ac signals In AC. first discuss the results of basic design of two stage CMOS Op-amp The design in this project is a two-stage op amp with an n-channel input pair.October 2012.647-654 A.) to make the circuit schematic (shown in figure 3) in Design Architect IC 650 | P a g e . The hand calculation results  Start frequency = 1Hz provided the estimated parameters (such as transistor  Stop frequency = 10 MHz width and length. centered at ground. (dVo/dt) The slope of the output 𝛽3 𝑉𝑇𝑂3 (max) + VT1 (min) (10) signal is the slew rate. etc. Because the 𝑔𝑚 6 output signal is much larger than the input signal.Schematic used in this design is 3. A.

61us. This analysis helps to determine the slew rate of the op-amp. The value of pulse period is 769. 2.249 dB ω-3db = 1.com Vol. Figure 5. September. Issue 5.3 KHz Phase margin = 85. pp.647-654 Figure 6. Transient Analysis The non inverting terminal is connected to a pulse with a rise and fall time equal to 1n sec (0.985 dB B. Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.23us. Output Swing 651 | P a g e . Result of ICMR Output: The output results of AC analysis is as follows Gain = 77.850 ωUGB = 14.ijera.32 V/µs. Output of AC Analysis The slew rate achieved in this design is 10.1us) and a pulse width of 384. Figure 8.October 2012. Result of Slew Rate Figure 4. Result of CMRR Figure 7.1MHz CMRR = 80.

October 2012.275 indicators:  Minimum feature size ωUGB (MHz ) 8.53 scaling.853  Number of gates on one chip  Power dissipation  Maximum operational frequency CMRR (dB) 80.742. Impact of scaling is characterized in terms of several ω -3dB (KHz ) 1.36 58.347 0.ijera.328V/us is a multiplication factor.3.25 3.282 3.24 69.931. By Reducing L: Output Swing = 0.35 12. f= 4.4 us (W/L)n = f * (W/L)1 Negative Slew Rate = 9. Interconnect Woes 4. f = 3. 13. Improved Cost (V/µs) -9. pp. results in a device either larger or smaller than the un-scaled device is called Gain (dB) 77.2 63.237 V A. Power Woes 5. Values of W of reference circuit Name Values W1.0 – 0. Scaling allows people to build more complex machines that run faster too and it does let you design PM 53.29 53. 2.253 Table 2.9 – 3.4 0. September.0 – Swing (V) 3.224 3.18 -9 -10. Physical Limits Time ( µs) Reference Circuit L = 1.0 – 0.347.6 11. Values of various parameters after reducing V.28 3.0192 6. W2 12 W3.985 78 67.23 3.12 15. Productivity Challenges Settling 0.com Vol. 10.287 3.3 4. 26.570 73.28V Table 3. Scaling value of L Proportional adjustment of the dimensions of Results f =1 f = 2.30 more modules.86 14.245 3.527 -9.647-654 Consider all W/L of reference circuit as (W/L)1 and f Positive Slew Rate = 10.13 1. Issue 5.304 0. Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www. Settling Time = 0.93 – Implications of Scaling 3.078.40V/us ICMR = 0.49  Production cost ICMR (V) 0.9 47. L an electronic device while maintaining the electrical L=L1/2 L=L1/3 = L1/4 properties of the device.812 – 0.960 65.0 – 0. Improved Performance Slew Rate 10. W4 23 W5.9 – 0. W8 20 W6 195 W7 90 652 | P a g e .0 .460 59. 2.4 um Output 0.75 – 0.

.266 Figure 10.0 -3.4 µs 0.297 0.0 –3.494.com Vol. Scientist E2 (CEERI Pilani) for his helpful discussion.6 10.56 87.165 78. By increasing W: Table 4. 10. pp.258 0.383 µs 0.9 –3.460 47. As a summary.0 – 3.Variations in Parameters with reducing L 653 | P a g e . Amana Yadav / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.76 – 0.37 11.285 specifications given in advance.360 40. f = 3. 2.23 0.28 0. Issue 5. Figure 9. The end result is that there is no single end point for scaling.993 89.8 – 3.27 3. VI. but that instead there are many end points. f= 4.347. Acknowledgements With a deep sense of gratitude.56 ICMR(V) 0. Pilani for their inspiration and heartfelt support. The results show that the Output 0.654 ω UGB ( MHz) 8.647-654 B.W W=2W1 W=3W1 =4W1 Gain (dB) 77. 10.3 1. 10.47 1. its calculations and computer-aided simulation results are given in detail.Variations in Parameters with increasing W Slew Rate 10.873 8.050 ω -3dB (KHz ) 1. Tables and graphs of different parameters for various aspect ratios are drawn.49.258 CMRR(dB) 80.417 PM 53.985 85. Values of various parameters after increasing value of W Results f =1 f = 2. each optimally adapted to its particular applications. Conclusion (V/µs) -9. I wish to express my sincere thanks to Dr.82 This paper presented the full custom design of a two stage CMOS Op-Amp and analyzed its behavior for Settling 0.4 µs 0. September.58 1. S C Bose.970 43.73 –3.36 µs various aspect ratios.October 2012.ijera.527 -8. VII. Design technique for this Op- Time Amp.05 11.295 designed amplifier has successfully satisfied all the Swing (V) 3.68 -8. Also wish to acknowledge the IC Design Group of CEERI. a tables and graphs are provided to estimates the scaling limits for various applications and device types.38 78.0 – 0.469. Graph: Graph shows the variations in different parameter of Op-Amp with various aspect ratios.24 78.

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