Interrupt mechanism

What is interrupt?

According to the Longman Dictionary
Interrupt – to break the flow of speech or action of (someone) by saying or doing

So how this relates to a computer system or why it is important to learn the interrupt

Let’s consider the following real-life scenarios

• When you are talking in the phone or playing on-line game and your lecturer
asks you to hang-up then you are interrupted by the lecturer.
• When your phone rings during a lecture, then your lecturer is interrupted and
he/she will ask you to leave the classroom. After that the lecturer will continue
the lecture.
• When you are studying hard preparing for your exam and your cell phone
rings – what will you do?
• Most likely you will answer the phone. When you finish talking then
you will continue with your study
• Now your phone rings again and someone also knocking at your door then
what will you do?
When being interrupted (such as your phone rings), you will perform a pre-
defined action. Such as answering the phone when it rings; or ask the student to
leave the room
Interrupt has priority – some interrupt is more important than the others. For
example you will open the door first before answering the phone, or vice versa
depending on how you assign your priority.

Traditional approach comparing to interrupt

If you want to develop a robot that can move forward and avoid obstacles using
sensors, how can you implement the software to control the robot?

In the traditional approach, you can move the robot forward, then stop and take the
sensors’ signal. If sensors’ signals imply no obstacle then move forward again. You
will repeat the above operations. This mechanism is usually called “Polling”.
Interrupt approach, now you keep running the robot forward if there are obstacles
then sensors will issue an interrupt to inform the robot so that the robot will act

Which approach is better and why?

Figure 1 Robot will sensors

Sensor active ?

No Yes
Move forward


The CPU does not need to check the keypad input periodically. Interrupt Interrupt by sensor Moving Return to normal forward program Response to interrupt Case 2 Implementation of a keypad control If you want to use a keypad to control the function of a motor. Interrupt From Check keypad keypad input Control motor Control motor Interrupt Polling Interrupt The keypad will issue an interrupt when user presses a key then the CPU will response to the interrupt and modify the motor control according to the interrupt signal. or set a timer. . such as controlling the speed. what kind of program flow will you use? Polling Your program will have a loop and every time you go through the loop you will check for the input from the keypad then control the motor according to the input in the keypad.

When an interrupt occurs. otherwise keep waiting for the key being pressed (or looping) !!! Interrupt The CPU executes other program. Applications of the interrupt mechanism How to get a key typed in the keyboard? Polling The CPU executes a program that check for the available of data. Remember that a CPU. the CPU will perform pre-defined operations according to the nature of the interrupt so the microprocessor can execute other software (doing other things) before an interrupt occurs. If a key is pressed then read the data. The keyboard will issue an interrupt to the CPU to inform the CPU that a key has been pressed. eg a keyboard. the Keyboard generates an interrupt.” Do you understand why and how? The computer system is more effective in this way. The Interrupt Mechanism Interrupt can be caused by an external device or an internal event. such as the Windows 3. The CPU will response to the interrupt – read the data. interrupt is an important feature used in the Operating System design. as soon as a key is pressed. During an interrupt. or a core. users can switch between different application programs and this makes users think that more than one program are being executed at the same time. Since the keyboard is not active all the time (even if you can type 120 words per minute comparing to the operating speed of the CPU!) so the CPU only serves the keyboard when necessary (ie when interrupted). can only do 1 thing at each time so when a CPU is busy performing some operations and if you want to attract the CPU’s attention then you must interrupt the CPU! In the old days. So by proper use of interrupt. The interrupt mechanism is a procedure (function) that interrupts whatever program is currently executing by the CPU. Do you know what technique is being used in modern OS design so that multiple applications can run in parallel? Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data-transfer rates. After that returns to the original program. Using the interrupt mechanism.The Interrupt Mechanism in a computer The interrupt mechanism implemented in a computer system is similar to our real-life examples. the CPU can serve many devices at the “same time. program control is transferred from the original program to the Interrupt .1.

Five groups: external hardware interrupt. software interrupts. The CPU remembers the location where it left off in the original program and then executes the interrupt service routine. The mechanism is similar to a subroutine call. Normal Program Flow Interrupt Request Interrupt Service Routine ISR Interrupt Return (IRET) The 8086 microprocessor can implement 256 different types of interrupts. and reset. software. internal interrupts.Service Routine (ISR). After this routine has run to completion. just like returning from a subroutine call. or written. and nonmaskable interrupts can be defined. . and internal interrupts are serviced on a priority basis. The interrupts are divided into 5 groups (or categories). Priority hierarchy groups: internal interrupt (highest priority) nonmaskable interrupt software interrupt external hardware interrupt (lowest priority) Internal interrupt group has the highest priority External hardware interrupt group has the lowest priority Within a group. nonmaskable interrupt. program control is returned to the point where the CPU originally was executing. Interrupt Priority Hardware. different interrupts have different priority levels represented by the type number (or interrupt number). software. by user. The interrupt routines for external hardware. When more than one interrupt occur then priorities of the interrupts are compared in order to determine which interrupt to serve first.

the newly occurred interrupt must wait. When a CPU is performing an interrupt service routine. divide error. The location of an interrupt service routine is stored in the interrupt address table and each location occupies 4 bytes representing the segment and offset of the ISR. Normal Program Flow Interrupt by a higher Interrupt priority Interrupt How an external device interrupt the CPU? In order to interrupt the CPU. If a lower priority occurs. is a type 0 interrupt Divide error : divide by zero An Overflow in your calculation will generate a type 4 interrupt. For 8086 the table is in location in 00H– 3FFH (a total of 1K because there are 256 interrupts and 4 bytes each. . or what is the address of the ISR?” The interrupt address table is used to link the interrupt numbers to the locations of their service routines in the memory. it can be interrupted by a higher priority interrupt.For human beings. there are also internal interrupts such as feeling hungry.) The higher address word is the base address and will be loaded into the CS register. Type 0 – highest priority Type 255 – lowest priority Example – an internal interrupt. The question is “where to find the ISR from memory. you must issue a signal and this signal must be directed to the INTR input of the CPU if it is an 8086. Interrupt address table Now you know that when an interrupt occurs then you need to execute the corresponding ISR.

Interrupt instructions in assembly language programming Mnemonic Meaning Format Operation Flags affected CLI Clear interrupt CLI IF = 0 IF (Interrupt flag Flag) STI Set interrupt flag STI IF =1 IF INT n Type n software INT n TF. In HEX.1 02 CS – 0 Int 0 Divide Error 00 IP – 0 Example At what address of the Interrupt address table should ISR for Interrupt 50 (INT 50) be stored in memory (i. Table 1 Structure of Interrupt address table Address in Hex Content Interrupt Definition (16-bit) (2 bytes) Number (or Vector) 3FE CS – 255 Int 255 External Interrupt 3FC IP .2 Int 2 Non-maskable 08 IP – 2 Interrupt 06 CS – 1 Int 1 Single Step 04 IP .255 :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: Interrupt 5 to Interrupt 31 – Internal interrupt 0A CS .e. CAH & CBH stores the CS value.The lower address word is the offset address and loaded into the IP register when an ISR is being executed. 200 is C8H to CBH and C8H & C9H stores the IP value. where is CS – 50 and IP – 50)? This represents the interrupt number 50 Starting from Type 0. type 50 should be in 50x4 = 200 since each address occupies 4 bytes. IF interrupt IRET Interrupt return IRET ALL .

The Interrupt Flag (IF) If the interrupt flag (IF) is set (=1) then external hardware can initiate an interrupt via the INTR input of the microprocessor. . During the initiation sequence of an interrupt service routine. The circuit will support interrupt type number from 32 to 255 (external interrupt). Without a proper interface circuit. The INT instruction allows a user to call the interrupt service subroutine in a program. This masks out (disable) the occurrence of any additional external hardware interrupt. Mnemonic Meaning Format Operation Flags affected INTO Interrupt on overflow INTO INT 4 if O = 1 TF. the 8086 automatically clears IF. So there is a many to one relationship (many devices generating the interrupt request but only 1 can be chosen!!!) The circuit (or the interrupt controller) must identify which of the pending active interrupt has the highest priority and then pass its type number (or interrupt number) to the 8086 The 8086 samples the INTR input during the last clock period of each instruction execution cycle.Most of the interrupt instructions do not require operand except the INT. The IF flag should be re-enabled at the end of the service routine External hardware interrupt An interrupt interface circuit is required to drive the INTR (Interrupt Request) input of the 8086 (WHY????). IF TF – trap flag HLT Halt HLT Wait for an None external interrupt or reset to occur WAIT Wait WAIT Wait for /test None input to go active Example INT 80 – calls the interrupt service procedure that begins at the address represented in vector number 80. If IF flag is clear then the external device cannot initiate an interrupt. how many external interrupt can you support? There is only 1 interrupt input in the 8086 which is the INTR (Interrupt Request).

If IF is 1 then external hardware interrupts are enabled and the service routine is to be initiated 5. INTR switches to 1 2. When the CPU is being interrupted (INTR =1) then you must tell the CPU which device is causing the interrupt so that the CPU can perform the corresponding ISR. The CPU after receiving the interrupt request will check the setting of the IF (interrupt flag) 3. 1. If IF is 0 then no interrupt action will be performed 4. otherwise. the CPU will acknowledge the interrupt and then waiting for the interrupt type number from the interrupt interface circuit. External AD0 – AD15 Hardware Interrupt Interface Devices 8086 circuit Interrupt Requests INTR INTA Figure 2 External hardware interrupt configuration INTR =1 implies an active interrupt request INTR is level-sensitive must be held at ‘1’ until it is recognized INTR must be clear before the service routine runs to completion. Therefore. Two pulses are produced at INTA during the interrupt acknowledge bus cycle The first pulse signals external circuit that the interrupt request has been acknowledged and to prepare to send the type number. The type number (an 8-bit value) is putted on the bit 0 to 7 of the address/data multiplexed bus External interrupt sequence – what will happen during an interrupt? The interrupt sequence begins when an external device requests service by activating one of the interrupt inputs. The second pulse tells the external circuit to put the type number on the data bus. the same interrupt may be acknowledged again. the external circuit must issue a request for service to the 8086. Interrupt interface circuit (interrupt controller) evaluates the priority of the input. INTA – interrupt acknowledge is sent by the CPU as a mean to inform the recognition of an interrupt. Interrupt acknowledge cycle is initiated . If there is no interrupt already in progress and this interrupt is of higher priority than any other interrupt that is simultaneously active.

During T2 and T3. Flag register is saved in the stack 9. The type number is internally multiplied by 4. address/data is put in the high-Z state and stays in this state for the rest of the cycle b. the interrupt acknowledge part of the interrupt sequence is completed and the corresponding interrupt service routine is executed 8. This must be valid during T3 and T4 6. External circuit put the type number on the data bus. Note: /INTA is issued twice . a. IF is clear to disable other hardware interrupt 10. /INTA is switched to 0. IRET at the end of the service routine causes the contents CS and IP saved in the stack to be restored so that the original program can be resumed. T1 of the first bus cycle. DT/R. and M/IO must set properly to read the type number from the data bus 7. In the second interrupt acknowledge bus cycle. Interrupt Service Routine (ISR) is initiated 14. and the result is used as the address to locate the ISR from the interrupt address table 13. Current values of CS and IP are saved in the stack 12. And the INTR can be removed c. /DEN. TF is clear to disable single-step mode if it is active 11. the /INTA tells the external circuit to put the type number of the active interrupt on the data bus d. After reading the type number.

To restore registers and parameters from POP ZZ the stack POP YY POP XX Return to main program IRET . . To save registers and parameters on the PUSH XX Stack PUSH YY PUSH ZZ . you must save all important information such as registers’ content to the stack. Main body of the service routine . you must restore the contents back the registers. At the end of the ISR. At the beginning of the ISR.Flow chart for interrupt sequence Interrupt service routine basic features If you are going to write your own ISR then you must adopt the following features.

The 8086 will then read the interrupt type number from the data bus which is connected to the 1Y1 1Y2 . The /INTA from the 8086 is connected to the “enable” of U1 (which is a latch) so the /INTA signal can control the latch. If any of the inputs is a ‘0’ then a ‘1’ will be generated by the NAND gate activating the INTR.Expanding interrupt input for 8086 There is only 1 input (the INTR) in the 8086 but many devices want to issue the interrupt request so it is necessary to expand the interrupt input.. Latch The above circuit can accept 7 interrupt inputs (the 8086 has only 1 interrupt input - the INTR) by using a multiple inputs NAND gate. When G1G2 of the latch are ‘1s’ then data available in the 1A1 1A2 etc will be passed to 1Y1 1Y2 etc. This can be achieved with a simple circuit or using a special device such as an interrupt controller. The /INTA from the 8086 will activate the latch and the input of the latch will be transferred to the data bus (D0 – D7). Input 1 Input 2 In1 NAND In2 0 0 1 0 1 1 1 0 1 1 1 0 NAND = Not AND The next stage is to supply the interrupt type number to the data bus during the acknowledge cycle. .. So when you have an active interrupt request then the INTR can be activated. The inputs are labeled /IR0 to /IR6 (active low).

8086 will visit the Interrupt Address Table and try to retrieve the address of the ISR for IR0. If the ISR for IR0 is located in memory address ABCDH then the interrupt address table will be similar to the following. That is if IR0 is active then the interrupt number is 1111 1110 and if IR1 is active then the interrupt number is 1111 1101 as shown in the circuit. IR0 has higher priority than IR5) then what should we do now? We should execute the ISR for IR0 when IR0 and IR5 are active at the same time!!!! We want to execute the ISR for IR0 (because it has a higher priority!). eg IR0 and IR5.The device U1 is a latch and its inputs come from the /IRx (where x is 0 to 6) and the latch outputs are connected to the data bus used to represent the Interrupt Type number. if IR0 is active then the interrupt type number is 1111 1110 = FEH (D7 is always 1 as shown in the circuit). Using the previous circuit. Can you support multiple interrupt requests being active at the same time with the above setup? When more than 1 interrupt requests are active then the priority issue must be considered. If we assume that interrupt request that has a smaller number has a higher priority (ie. After receiving the interrupt number DEH the CPU will go to the Interrupt Table to retrieve the address of the ISR. Note: The address in HEX is derived from the interrupt number x4 Table 2 Interrupt address table Interrupt Address Content Number in HEX Only IR0 FEH 3FA CDH active 3F8 ABH . In order to handle this. This is achieved by proper arrangement of the ISR address stored in the interrupt address table. The interrupt type number is derived from the active interrupt input. Because now the ISR of IR0 will be executed when both IR0 and IR5 are active as IR0 has a higher priority. you must first consider which interrupt request has a higher priority. The interrupt number generated from the two IRs is 1101 1110 = DEH. So if we put the address of the ISR of IR0 in the location (DEHx4) then we achieve our goal. After receiving the interrupt number. So when there is only 1 interrupt request then the system can derive the corresponding interrupt type number. For example. can you handle two interrupts activated at the same time ????? Example If now two interrupt request inputs are active at the same time.

Software Interrupt Software interrupt is to invoked (or activate) an interrupt service routine in a program. the function waits until any key is pressed. There are 256 software interrupts and the instruction for issuing a software interrupt is INT n. give one more address in the Interrupt address table that is also storing the value ABCDH. ‘a’ INT 21H . Control is passed to the start of the service routine immediately upon completion of execution of the interrupt instruction. result is stored in AL. During software interrupt. INT 21H – allow to read or write character from standard input or output If AH = 1 – read character from standard input. Character to write is stored in DL register and after execution AL = DL. 2 MOV DL. MOV AH. you can use the following statements. Software interrupts have a higher priority than external interrupts and cannot be masked out by IF. if AH =0 and AL = 13H then INT 10H will set the display to video mode. no external interrupt acknowledge bus cycles are initiated because the interrupt type number is already known. where n is the interrupt type number. Examples of software interrupt provided by x86 system INT 10H is a software interrupt that can be used to control the video mode The INT 10H software interrupt can perform different functions which are controlled by values load to different registers. If there is no character in the keyboard buffer. with echo. To display the character ‘a’. For example. If AH=2 – write character to standard output. IR5 and DEH 37A CDH IR0 378 ABH active Exercise Based on the above priority scheme.

eg detection of power failure and detection of a memory read error NMI application – the above circuit will issue an NMI when power is down The circuit in Figure 12-6 is used to detect a power failure. The NMI is type 2 (has a very priority level) and NMI is for hardware events that must be responded to immediately (major system faults). Or must remain a ‘1’ until it is recognized by the microprocessor. During an nonmaskable interrupt. Can be expanded (using more 8259) to accept up to 64 interrupt requests using master/slaves configuration . and current IP to be pushed onto the stack. NMI is also initiated from external hardware but it cannot be masked out (disabled) with the IF flag. Interrupt controller We have looked at a simple setup using a NAND gate and a latch to implement an interrupt mechanism. current CS. Can resolve interrupt priority 3. It can support up to 8 interrupts to the microprocessor. In a real computer system. NMI causes the current flags. Single-step mode of operation is disabled. The other interrupt input is INTR. NMI interrupt will send a 1 to the NMI input of the 8086 and the NMI input is positive edge triggered (low to high) and the NMI signal must be active for 2 consecutive clock cycles. The basic functions of an interrupt controller include: 1. When it happens then the NMI signal will be issued to the CPU so that important data can be saved. Support multiple inputs 2. a more complicated approach is used and this usually involves some standard interrupt controller hardware such as the 8259A. Able to issue the interrupt request 4. Able to put the interrupt type number into the data bus The 8259A is a hardware device to support the interrupt mechanism.Nonmaskable Interrupt (NMI) NMI is an input pin in the 8086 to support nonmaskable interrupt. Interrupt enable flag is cleared to disable all external hardware interrupts.

The host interface consists of: data bus. . The INTA produced by the microprocessor consists of two pulses and it signals the 8259 to put the interrupt type number on the data bus. or interrupt type numbers. The data can be command words. status information. interrupt acknowledge (INTR) and chip select. interrupt request (INT). They are used for handshaking.The 8259A is programmed via the microprocessor through the host processor interface. read. Connect to devices that can issue interrupt To master slave configuration The IR0 to IR7 are connected to the external hardware and D0-D7 are connected to the data bus of the microprocessor for supplying the interrupt type number. The CAS0 to CAS2 are the cascade connection allowing multiple 8259A to be connected together forming a system that can support a maximum of 64 interrupt requests. write. The INT and INTR are connected to the microprocessor. The INT generated by 8259 is connected to INTR of 8086 and INT becomes ‘1’ when 8259 receives a valid interrupt request from inputs IR0 to IR7.

if IRR is 00000001 then IR0 is active Priority Resolver • The priority resolver identifies which of the active interrupt inputs has the highest priority • The resolver can be configured to work using a number of different priority schemes through software and programmed by the 8086 • Example – automatic rotation • A device after being serviced receives the lowest priority . 1.Block diagram of the 8259A Full details regarding operations of the 8259A are available in the device’s data sheet.enable.mask out (disable) • The register can be read from or written into under software control (programmed via the microprocessor) • For example if the IMR is 10111101 then only interrupt IR1 and IR6 are enabled Interrupt Request Register (IRR) • IRR stores the current status of the interrupt request inputs connected to the external devices • Has one bit for each IR input • The values in the bit positions reflect whether the interrupt inputs are active or inactive • For example. Brief description for different components inside the 8259A • Interrupt mask register (IMR) can be used to enable or mask out (disable) individually the interrupt request inputs • There are 8 bits and each bit represents one interrupt input • 0.

the control logic causes the INT signal to be issued • The in-service register (ISR) stores the interrupt level that is presently being serviced. When a slave request line is activated and afterwards acknowledged. • During the first INTA pulse in an interrupt acknowledge bus cycle. This permits easy expansion of the interrupt interface using a master/slave configuration Cascade mode The 8259A can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels. Interrupt in the other microprocessor such as ADuC832 The ADuC832 provides a total of 9 interrupt sources and the control and configuration of the interrupt system is carried out through 3 interrupt related registers. . The INT outputs from the slaves are connected to the INTR input of the master. the slave interrupt outputs are connected to the master interrupt request inputs. namely the IE (Interrupt Enable Register). the master will enable the corresponding slave to release the device routine address.• It will signal the control logic that an interrupt is active and in response. and IEIP2 (Secondary Interrupt Enable Register). IP (Interrupt Priority Register). In a cascade configuration. The cascade bus acts like chip selects to the slaves during the /INTA sequence. • The ISR (in-service register) cannot be written into by the microprocessor but its contents may be read as status • The cascade buffer/comparator section provides the interface between master and slave 8259As. The master controls the slaves through the 3 line cascade bus. the level of the highest active interrupt is strobed into ISR.

“0” = Low) 5 PT2 Select Timer 2 Interrupt Priority (“1” = High. while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. the higher level interrupt will be serviced first. #0000 0001B Source Priority Description PSMI 1 (Highest) Power Supply Monitor Interrupt WDS 2 Watchdog Timer Interrupt IE0 2 External Interrupt 0 ADCI 3 ADC Interrupt TF0 4 Timer/Counter 0 Interrupt IE1 5 External Interrupt 1 TF1 6 Timer/Counter 1 Interrupt ISPI/I2CI 7 SPI Interrupt/I2C Interrupt RI + TI 8 Serial Interrupt TF2 + EXF2 9 (Lowest) Timer/Counter 2 Interrupt TII 11(Lowest) Time Interval Counter Interrupt . An interrupt of a high priority may interrupt the service routine of a low priority interrupt. Bit Name Description 7 ---- Reserved for Future Use 6 PADC Select ADC Interrupt Priority (“1” = High. “0” = Low) 3 PT1 Select Timer 1 Interrupt Priority (“1” = High. “0” = Low) 1 PT0 Select Timer 0 Interrupt Priority (“1” = High. #1000 0100B The bit 7 must be ‘1’ for all cases. For example if you want to enable an external interrupt 1 then the bit 2 of the IE must be ‘1’ so you must carry the following move operation MOV IE. “0” = Low) 4 PS Select UART Serial Port Interrupt Priority (“1” = High. If two interrupts of the same priority level occur simultaneously. and if two interrupts of different priority occur at the same time. “0” = Low) 0 PX0 Select External Interrupt 0 Priority (“1” = High. “0” = Low) The Interrupt Enable registers are written by the user to enable individual interrupt sources. An interrupt cannot be interrupted by another interrupt of the same priority level. a polling sequence is observed according to the following table So if you want to select External Interrupt 0 has a high priority then you need to carry out MOV IP. “0” = Low) 2 PX1 Select External Interrupt 1 Priority (“1” = High.Bit Name Description 7 EA Written by User to Enable “1” or Disable “0” All Interrupt Sources 6 EADC Written by User to Enable “1” or Disable “0” ADC Interrupt 5 ET2 Written by User to Enable “1” or Disable “0” Timer 2 Interrupt 4 ES Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt 3 ET1 Written by User to Enable “1” or Disable “0” Timer 1 Interrupt 2 EX1 Written by User to Enable “1” or Disable “0” External Interrupt 1 1 ET0 Written by User to Enable “1” or Disable “0” Timer 0 Interrupt 0 EX0 Written by User to Enable “1” or Disable “0” External Interrupt 0 The above table is the pin definition for the IE register.

II only C. NMI are inputs for external interrupt • INTA – output to acknowledge the interrupt and ask for the interrupt number (or vector) • Interrupt controller is to expand the interrupt interface. The ISR can be pre-empted by interrupt Type 49 III. None of the above . if you need to write the ISR for an external interrupt 1 then the ISR must be located in the address 0013H and this is achieved by using the directive ORG. Source Vector Address IE0 0003H TF0 000BH IE1 0013H TF1 001BH RI + TI 0023H TF2 + EXF2 002BH ADCI 0033H ISPI/I2CI 003BH PSMI 0043H TII 0053H WDS 005BH Based on the above. Always serve the high priority first • ISR – interrupt service routine tells the CPU what to do during an interrupt • A table stores the locations (represented by the corresponding CS and IP values) of the ISRs • INTR. which of the followings are correct? I.The location of an ISR is predefined in the ADuC832 as shown in the following table. II and III only E. The instruction for the return from interrupt is RETI. III only D. The ISR represents an external hardware interrupt II. resolve priority etc Exercises If the 8086 CPU is currently executing an Interrupt Service Routine (ISR) which is located in address CCH of the interrupt pointer table. Summary • Using interrupt allows CPU to serve many devices at the same time • There are different types of interrupt – software. The ISR can be pre-empted (interrupted) by an internal interrupt A. I only B. ORG 0013H This is followed by the source program of the ISR. hardware • Interrupt – has priority.

Give one example to illustrate why the interrupt mechanism can improve the efficiency of a computer system.Explain in details the interrupt mechanism implemented in the 8086 microprocessor for an external hardware interrupt. .