SAP-1(Simple as Possible-1) Computer Architecture

the address of the next instruction to be executed and fetched. RAM: . The instruction set is very limited and is simple.  Program counter – initializes from 0000 to 1111 during program execution. the MAR applies this 4-bit address to the RAM. Program Counter: The program/Instructions are stored at the beginning of the memory with the first instruction at binary address 0000. the second at 0001 and so on. The PC is a part of the control unit. The features in SAP-1 computer are:  W bus – A single 8 bit bus for address and data transfer. where a real read operation is performed. The PC is reset to 0000 before each computer run Input and MAR: The memory address register (MAR) is latched with the address of the pc during a computer run. A bit later. Its job is to send to the memory address register. interacts with memory and other parts of the system like input and output. The SAP-1 design contains the basic necessities for a functional Microprocessor.The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino.  16 Bytes memory (RAM)  Registers are accumulator and B-register each of 8 bits.  6 machine state reserved for each instruction  The instruction format of SAP-1 Computer is (XXXX) (XXXX) The first four bits make the Opcode while the last four bits make the operand (address).  A Control Unit  A Simple Output. It has some switch registers which helps it to do so.  Adder/ Subtracter for addition and subtraction instructions.  Memory Address Register (MAR) to store memory addresses. Its primary purpose is to develop a basic understanding of how a microprocessor works.

the sum out of the adder-subtracter is . 3) The three state output goes to the W-bus when EA is high. the instruction or data word stored in the RAM is placed on the W-bus. During a computer run. 3) At the same time. Adder-Subtractor: 1) When SU is low. 2) This resets the PC to 0000 and wipes out the last instruction in the IR. 5) The upper nibble is a two state output that goes directly to the block labeled ‘Controller-sequencer’. the IR is set up for loading on the next positive clock edge. The first one goes directly to the Adder-Subtracter. the RAM receives 4-bit addresses from the MAR and a READ operation is performed.The RAM is a 16×8 static TTL (Transistor Transistor Logic) RAM. 3) A clock signal CLK is sent to all buffer registers. 2) To fetch an instruction from the memory the computer does a memory read operation. Controller-Sequencer: 1) Before each computer run. 5) The control word has the format: This word determines how the registers will react to the next positive CLK edge. this synchronizes the operation of the computer. Instruction Register: 1) The instruction register is part of the control unit. In this way. This places the contents of the addressed memory location on the W-bus. Accumulator: 1) The accumulator is a buffer register that stores immediate answers during a computer run. (CLR’) signal is sent to the PC and CLR signal to the IR. 4) The contents of the IR are split into two nibbles. 2) It has two output. 4) The 12 bits that come out of the CS form a word controlling the rest of the computer. The 12 wires carrying the control word are called the control bus. 6) The lower nibble is a three state output that is read onto the W-bus when needed.

3) When EA is high. 3) After we have transferred an answer from the accumulator to the output port. 4) The output register is often called an output port processed data can leave the computer through these register.register. 2) Each LED connects to one flip-flop of the output port. Output Register: 1) At the end of a computer run. This is where the output register is used. this means that its contents can change as soon as the input words change. INSTRUCTION FORMAT: Instruction of SAP-1 is of 8 bit length XXXX XXXX First 4 bits are Opcode and last 4 bits are Operand Example: LDA 9H and its binary equivalent is 0000 1001 . 2) At this point. these contents appear on the W-bus. 2) A low LB‘ and positive CLK edge load the word on the W-bus into the B-register. Output Port: 1) The binary display is a row of 8 LEDs. the next positive clock edge loads the word of the accumulator into the output register. B Register: 1) The B register is also a buffer register. we can see the answer in binary form. 3) The two state output of the B register drives the B. is low. we need to transfer the answer to the outside world. the sum out of the adder-subtracter is S=A+B’ 3) The adder-subtractor is asynchronous (unlocked). 4) When EU is high. the accumulator contains the answer to the problem being solved.S=A+B 2) When SU is high.

INSTRUCTION SET: PROGRAMMING SAP-1: Example: Write a program to compute 16+20+24-32 (decimal) and display result in SAP-1 computer .

T6). but the task of each steps depends on the instruction FETCH CYCLE The control unit is the key to a computer’s automatic operation. T5. While each instruction is fetched and executed.Instruction Cycle: Fetch Cycle  T1 (Address State)  T2 (Increment State)  T3 (Memory State) Execution Cycle  3 step (T4. the computer passes through different timing states (T states). The CU generates the control words that fetch and execute each instruction. periods during which register contents modify .

Addition takes place in ALU if SU low. Execution Cycle (OUT Instruction)  For OUT instruction. Subtraction takes place if SU is high. only T4 and T5 states that will be active  T4: memory address is sent from IR to MAR  T5: data from memory is fetched and send to ACC  T6: do nothing (No Op) Execution Cycle (ADD and SUB Instruction)  For ADD instruction. Control Signal During Each T state Execution Cycle (LDA Instruction)  For LDA instruction. T4. only T4 state will be active . T5 and T6 states that will be active  T4: memory address is sent from IR to MAR  T5: data from memory is fetched and send to B register  T6: Addition/ Subtraction takes place using the values stored in accumulator and B register. Calculated value is stored in ACC when EU is high through w-bus.

Execution Cycle (HLT Instruction) There is no execution cycle for HLT Cycle. T4: EA and LO’ will be active so data stored in Accumulator is loaded into Output register and displayed in the output unit. When IR sends 1111 to the controller. it halts computer by turning off the clock .