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Datasheet

VCS
Multicore-enabled functional verification solution

Overview Multicore support


VCS®, with multicore technology, VCS multicore technology allows users to cut down verification time for long-running
delivers a 2x verification speed-up tests. VCS offers two robust use models: design-level parallelism (DLP) and
that helps users find design bugs early application-level parallelism (ALP). DLP enables users to concurrently simulate
in the product development cycle. multiple instances of a core, several partitions of a large design, or a combination
VCS multicore technology cuts down of the two. Application-level parallelism (ALP) allows users to run testbenches,
verification time by running the design, assertions, coverage and debugging concurrently on multiple cores. The
testbench, assertions, coverage and combination of DLP and ALP optimizes VCS performance over multicore CPUs.
debug in parallel on machines with VCS multicore technology also supports design-level auto-partioning, file system
multiple cores. The combination of database (FSDB) parallel dumping, and switching activity interchange format (SAIF)
performance; advanced bug-finding parallel dumping.
technologies; Echo testbench coverage
convergence for faster closure; a built-in Full-featured, native testbench and industry-leading
debug and visualization environment; SystemVerilog support
support for all popular design and VCS Native Testbench (NTB) provides built-in natively-compiled support for full-
verification languages including featured SystemVerilog and OpenVera testbenches, including object-oriented,
Verilog, VHDL, SystemVerilog, constrained-random stimulus and functional coverage capabilities. VCS’ industry
OpenVera, and SystemC™ and the leading constraint solver technology is powered by multiple solver engines that
proven VMM methodology help VCS simultaneously analyze all user specified constraints to rapidly generate high-quality
users develop high-quality designs. The random stimulus to verify the design for corner case behavior. These engines will
VCS solution’s advanced bug-finding find a solution to user constraints, if one exists, minimizing constraint conflicts and
technologies include full-featured maximizing verification productivity.
Native Testbench (NTB), complete
assertions and comprehensive code
and functional coverage to find
Multicore
more design bugs faster and easier. compiler
Additionally, the VCS Verification Design
Library provides high-quality VIP for
today’s most popular bus standards. Testbench
Multicore
The VCS solution’s powerful debug and Assertion native code
visualization environment minimizes
the turnaround time to find and fix Coverage

design bugs. VCS with MVSIM and Debug


MVRC delivers innovative voltage-
aware verification techniques to find
bugs related to modern low power Figure 1: Multicore support
designs.
VCS
Functional verification solution

Unified coverage API

Functional Code Assertion Formal


coverage coverage coverage coverage

Unified 3rd party


coverage tools
report

Coverage visualization and trend analysis

Figure 2: Unified coverage

Discovery Visualization Environment

Verilog Transaction-level
VHDL debug
SystemVerilog
SystemC Advanced
OpenVera assertion debug

Full Tcl Annotated


scripting source

Automated Powerful
driver tracing waveform
compare

Figure 3: Discovery Visualization Environment (DVE)

Complete assertion Comprehensive coverage Advanced debugging and


technologies The VCS solution provides high- visualization environment
The native assertion technology in performance, built-in coverage The VCS solution includes the Discovery
the VCS solution enables an efficient technology to measure verification Visualization Environment (DVE), a
methodology for deploying design- completeness. Echo testbench coverage next-generation, full-featured debug
for-verification (DVF) techniques. The convergence technology reduces the and visualization environment. The DVE
built-in support of SystemVerilog and time it takes to reach full stimulus has been specifically architected to
OpenVera assertions allows designers functional coverage. Comprehensive work with all of the advanced bug-
to easily adopt DFV and find more bugs coverage includes code coverage, finding technology in VCS and shares
quickly. A rich assertion-checker library functional coverage and assertion a common look and feel with other
and a unique library of Assertion IP coverage. Unified coverage aggregates Synopsys graphical-based analysis
make it even easier to deploy assertions all aspects of coverage in a common tools. DVE enables easy access to
across teams and improve their database, thereby allowing powerful design and verification data along
verification quality. The assertions serve queries and useful unified report with an intuitive drag-and-drop or
the needs of simulation as well as formal generation. The unified coverage menu-and-icon driven environment.
property verification environment. database offers 2x to 5x improvement Transaction-level debug is seamlessly
in merge times and up to 2x reduction integrated into DVE, allowing users
in disk space usage, which is useful for to analyze and debug transactions
large regression environments. in both list view and waveform view.

VCS 2
Its debug capabilities include: tracing testbench architecture that enables
drivers, waveform compare, schematic both new and experienced verification
views, path schematics and support engineers to quickly create and deploy
for the highly efficient Synopsys advanced, reusable, efficient verification
compact VCD+ binary dump format. environments. This methodology,
It also provides elegant mixed-HDL developed and used by verification
(SystemVerilog, VHDL and Verilog) and experts, helps users adopt industry-best
SystemC/C++ language debugging practices to get the best possible results
windows along with next-generation from the VCS solution. In addition, the
assertion tracing capabilities that help VMM methodology provides a number
automate the manual tracing of relevant of applications, such as Register
signals and sequences. TCL support is Abstraction Layer (RAL) and others, to
provided for interaction or batch control cut down on the time taken to set up a
and skin/menu customization. A unified powerful verification environment. All
command language is supported to the VMM applications, a detailed
provide a common set of commands for reference manual and examples are
all tools, languages and environments, provided with the VCS solution. The
making it easy to deploy new technology VCS Verification Library provides
across design teams. extensive support for the VMM
methodology, including an object
Verification methodology interface and scenario generators.
The VCS solution’s powerful testbench VCS also supports Accellera Universal
engines are complemented by the Verification Methodology (UVM)
proven VMM methodology, defined in base classes and the VMM/UVM
the popular Verification Methodology interoperability kit, which enables the
Manual for SystemVerilog, and layered use of VMM with UVM.

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06/10.CE.10-18814.