1

All these techniques

involve CPU as the

central controller which

leads to lot of slowness in

the process.

When the programme

initiated I/O is used, if

the I/O device is slow,

the CPU has to get in to

Prepared by M.Rajalakshmi no of wait states. 2

In an interrupting
One way of overcoming this
technique, the CPU has to difficulty is to isolate the
branch to a interrupt CPU and allowing the
service routine (ISR), before memory and I/O devices to
the I/O transfer takes place. perform their data transfer

If large amount of data are directly.

involved in the I/O transfer,
Such an opertion is called

these delays are going to be DIRECT MEMORY ACCESS.
large and the entire process (DMA).
is slowed down, when the

I/O transfer takes place

through the CPU.

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A DMA controller is a device, usually peripheral to a
CPU that is programmed to perform a sequence of
data transfers on behalf of the CPU.

A DMA controller can directly access memory and is
used to transfer data from one memory location to
another, or from an I/O device to memory and vice
versa.

A DMA controller manages several DMA channels, each
of which can be programmed to perform a sequence
of these DMA transfers.

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It is a device to transfer the data directly
between I/O device and memory without the
CPU.

So it performs a high-speed data transfer
between memory and I/O device.

FEATURES:

It is a 4-channel DMA. So 4 I/O devices can be

interfaced to DMA.

It is designed by Intel.

Each channel can be independently
programmable to transfer up to 64kB of data by
DMA. Prepared by M.Rajalakshmi 5
 Each channel can be independently
perform read transfer, write transfer and
verify transfer.
Each channel have 16-bit address and 14
bit counter registers.
It provides chip priority resolver that
resolves priority of channels in fixed or
rotating mode.
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Devices, usually I/O peripherals, that acquire data
that must be read (or devices that must output data
and be written to) signal the DMA controller to
perform a DMA transfer by asserting a hardware DMA
request (DRQ) signal.

A DMA request signal for each channel is routed to

the DMA controller.

This signal is monitored and responded to in much

the same way that a processor handles interrupts.
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The DMA controller is the sole master of the bus, till
the DMA operation is over.

The CPU remains in the HOLD status (all of its signals
are tristate except HOLD and HLDA), till the DMA
controller is the master of the bus.

In other words, the DMA controller interfacing circuit
implements a switching arrangement for the address,
data and control busses of the memory and
peripheral subsystem from/to the CPU to/from the
DMA controller.

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The DMA controller sends a HOLD request to the CPU
and waits for the CPU to assert the HLDA signal.

CPU relinquishes the control of the bus before

asserting the HLDA signal.

Once the HLDA signal goes high, the DMA controller

activates the DACK signal to the requesting
peripheral and gains the control of the system bus.

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It is operating in two modes.

1.Master Mode - DMA Controller connects the

memory and I/O Devices.

2.Slave Mode CPU (MPU) and DMA Controller
interact with each other.

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Prepared by M.Rajalakshmi 14
It containing Five main Blocks

1.Data bus buffer

2.Read/Control logic
3.Control logic block
4.Priority resolver
5.DMA channels

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DATA BUS BUFFER:
It contain tri state ,8 bit bi-directional buffer.
Slave mode  it transfer data between
microprocessor and internal data bus.
Master mode  outputs A8-A15 bits of memory
address on data lines (Unidirectional).

READ/CONTROL LOGIC:
It controls all internal Read/Write operation.
Slave mode it accepts address bits and control
signal from microprocessor.
Master mode  It generate IOR* & IOW* signals
to control the data flow to or from the
microprocessor.

Prepared by M.Rajalakshmi 16
CONTROL LOGIC BLOCK:
The control logic controls the sequences of operations and
generates the required control signals like AEN, ADSTB,
MEMR, MEMW, TC and MARK along with the address lines
A4-A7, in master mode.
CONTROL LOGIC:
Master mode  It control the sequence of DMA operation
during all DMA cycles.
It generates address and control signals.
It increments 16 bit address and decrement 14 bit counter
registers.
It activate a HRQ signal on DMA channel Request.
Slave mode  it Prepared
is disabled.
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Each channel of 8257 Block diagram has two
programmable 16-bit registers named as Address
register and Count register.

Each of the four channels of 8257 has a pair of two 16

bit registers.(Totally 8 regs)

There are two common registers for all channels

namely, mode set registers and status registers .

Thus there are a total of ten registers (8 + 2) the CPU

selects one of these ten registers using address lines
A0-A3 Prepared by M.Rajalakshmi 18
Prepared by M.Rajalakshmi 19

The 8257 performs the DMA operation over four
independent DMA channels. Each of the four
channels of 8257 has a pair of two 16 bit registers
viz. DMA address register and terminal count
registers. (Totally 8 regs)

There are two common registers for all channels
namely, mode set registers and status registers
.Thus there are a total of ten registers (8 + 2) the
CPU selects one of these ten registers using
address lines A0-A3

There are three main registers :

1) DMA address registers

2) Terminal count registers
3) Mode set registers
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Each DMA channel has one DMA address registers

The function of this register is to store the address

of the starting memory location which will be the
accessed by the DMA channel.

The 16 bit starting address of the memory block

is first loaded in the DMA address register of the
channel.

The address in the address register is automatically

incremented after every read/write/verify transfer.
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Each channel of 8257 Block diagram has two
programmable 16-bit registers named as
address register and count register.

The count register is used to count the number

of byte or word transferred by DMA.

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14-bits B0-B13 is used to count value and a 2-
bits is used for indicate the type of DMA transfer.

(Read/Write/Verify transfer).

In read transfer  the data is transferred from

memory to I/O device.

In write transfer  the data is transferred from

I/O device to memory.

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Prepared by M.Rajalakshmi 24
Prepared by M.Rajalakshmi 25
MODE SET REGISTERS:
It is a write only registers written by the CPU
It is used to set the operating modes.
This register is programmed after initialization of DMA
channel.

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Prepared by M.Rajalakshmi 27
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1) Rotating priority mode:

In rotating priority mode the priority of the channels has

a circular sequence .

In this channel being serviced gets the lowest priority and

the channel next to it gets highest priority

2) Fixed priority mode ; in the fixed priority mode the

channel 0 has the highest priority channel and channel 3
has lowest priority .after the recognition of any 1 channel
for service the rest are not allowed to interface with the
service
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3)TC STOP mode:

If the TC stop bit is set, a channel is disabled (I,e is

enable bit is reset)after the terminal count goes
high thus automatically preventing further DMA
operation on the channel

3)Extended write mode :Provides alternative timing

for the I/O and memory write signal which allows
the device to return to an early READY and
prevents unnecessary wait states

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4)Auto load mode :

Available only for channel 2

Count is automatically reloaded so that the DMA

Transfer takes place again for same number of
bytes once again, once this bit is set

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Tellsus the status of channels.

The bit B0, B1, B2, and B3 of status register indicates
the terminal count status of channel-0, 1,2 and 3
respectively. A one in these bit positions indicates that
the particular channel has reached terminal count.

These status bits are cleared after a read operation by
microprocessor.

The bit B4 of status register is called update flag and a
one in this bit position indicates that the channel-2
register has been reloaded from channel-3 registers in
the auto load mode of operation

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Prepared by M.Rajalakshmi 33
Prepared by M.Rajalakshmi 34
D0-D7:

It is a bidirectional ,tri state ,Buffered ,Multiplexed
data (D0-D7)and (A8-A15).

In the slave mode it is a bidirectional (Data is
moving).

In the Master mode it is a unidirectional (Address is
moving).
IOR*:

It is active low ,tristate ,buffered ,Bidirectional lines.

In the slave mode it function as a input line. IOR
signal is generated by microprocessor to read the
contents 8257 registers.

In the master mode it functions as a output line.

It is generated during write cycle.
Prepared by M.Rajalakshmi 35
IOW*:
It is active low ,tristate ,buffered
,Bidirectional control lines.
In the slave mode it function as a input
line. IOR* signal is generated by
microprocessor to write the contents 8257
registers.
In the master mode it function as a output
line. IOR* signal is generated by 8257 during
read cycle.
CLK:
It is the input line ,connected with TTL
clock generator.
This signal is ignored in slave mode.
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RESET:
Used to clear mode set registers and status
registers
A0-A3:
These are the tristate, buffer, bidirectional
address lines.
In slave mode ,these lines are used as
address input lines and internally decoded
to access the internal registers.
In master mode, these lines are used as
address outputs lines,A0-A3 bits of memory
address on the lines.
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CS*:
It is active low, Chip select input line.
In the slave mode, it is used to select the chip.
In the master mode, it is ignored.
A4-A7:
These are the tristate, buffer, output address
lines.
In slave mode ,these lines are used as address
outputs lines.
In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on
the lines.

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READY: It is a asynchronous input line.
In master mode,
 when ready is high it will receive the
signal,
 when ready is low, it adds wait state
between S1 and S3
In slave mode ,this signal is ignored.

HRQ:
It is used to receiving the hold request
signal from the output device.
Prepared by M.Rajalakshmi 39
HLDA:
It is acknowledgment signal from microprocessor.
MEMR:
It is active low ,tri state ,Buffered control output
line.
In slave mode, it is tri stated.
In master mode ,it activated during DMA read
cycle.

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MEMW:
It is active low ,tri state ,Buffered control
input line.
In slave mode, it is tri stated.
In master mode ,it activated during DMA
write cycle.

AEN (Address enable):
It is a control output line.
In master mode ,it is high
In slave mode ,it is low
Used to isolate the system address ,data ,and
control lines.

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ADSTB: (Address Strobe):
It is a control output line.
Used to split data and address line.
It is working in master mode only.
In slave mode it is ignore.
TC (Terminal Count):
It is a status of output line.
It is activated in master mode only.
It is high ,it selected the peripheral.
It is low ,it free and looking for a new peripheral.
MARK:
It is a modulo 128 MARK output line.
It is activated in master mode only.
It goes high ,after transferring every 128 bytes of data
block.
Prepared by M.Rajalakshmi 42
DRQ0-DRQ3(DMA Request):
These are the asynchronous peripheral request
input signal.
The request signals is generated by external
peripheral device.
DACK0-DACK3*:
These are the active low DMA acknowledge output
lines.
Low level indicate that ,peripheral is selected for
giving the information (DMA cycle).
In master mode
Prepared byit is used for chip select.
M.Rajalakshmi 43
Prepared by M.Rajalakshmi 44