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and ideally matched devices for differential amplifiers so that the differential

common mode output is exactly equal to zero. However (and big surprise),

even if the input average value is zero volts, the amplifier output may have

a non-zero average voltage due to biasing effects. These offsets appear as

dc voltages, usually quite small, and may be of little concern for a simple

amplifier. The problem arises when a high gain multi-stage dc amplifier,

such as an operational amplifier, encounters these offset voltages. Since the

gain of the op-amp is so high, a small offset in one of the earlier stages may

propagate through the system and saturate a later stage. This leads to all

kind of ugly things most noticeably an output that may be totally

worthless! So to solve this dilemma, we need something that will give us

unity gain for ac signals while allowing us to compensate (add or subtract) a

dc voltage to remove the unwanted offset. Note: Although your author

focuses on level shifters that have unity gain, in some configurations these

stages may contribute to the overall gain of the system.

of Figure 9.7b in your text. Transistor Q2 forms a

constant current source as well as providing an

additional resistance in the emitter circuit of Q1

(Note: any of the current sources of section G2

may be used). With this in mind, transistor Q1 is

configured as an emitter-follower amplifier stage

that acts as a level shifter. This level shifter acts as

a unity gain amplifier for ac signals while providing

an adjustable dc output.

is ignored and a KVL is written about the base-

emitter loop of Q1:

where VBB is the dc level acquired from a previous stage and RB=R1||R2.

Using the relationship IB=IC/ and assuming that IEIC, Equation 9.34 may

be solved for the dc value of the output voltage as

R

Vout = VBB I C 1 B1 + RE1 VBE . (Equation 9.36, Modified)

All the parameters in the right hand side of Equation 9.36 are fixed or

previously defined except for the value of RE1. By varying RE1, the dc level of

the output voltage may be set to any desired value less than VBB-VBE (this is

assuming that IC1RB/ is very small). The level shifter illustrated above is

used to shift the output downward to a lower value. If upward shifting is

required, the same circuit is used, but pnp transistors are substituted for the

npn transistors.

the right, is the mid-frequency small signal

model of the circuit above. Note that since

2IB2 (the collector current of the current

source) is assumed to be a constant dc

value, it is an open circuit for ac

conditions. In the following discussion, we

are going to be assuming that 1 and 2

are very large, so that

v out

i e1 i c1 = 1 i b1 i c 2 = .

ro2

the level shifter as

9.37 as follows:

v out v out

i e1 = and i b1 = .

ro2 1 ro2

KVL in terms of circuit components, physical parameters and input and

output voltages as

RB 1v out r 1v out R v

v in = + + E1 out + v out

1 ro2 1 ro2 ro2

, (Equation 9.38, Modified)

R / 1 + re1 + RE1

= v out B 1 + 1

ro2

where r1/1 has been replaced by re1. The voltage gain is the ratio of ac

output to ac input, or

v out 1

=

v in 1 + (RB1 / 1 + re1 + RE1 ) / ro2

. (Equation 9.39, Modified)

ro2

=

ro2 + (RB 1 / 1 + re1 + RE1 )

sources we discussed), the gain of Equation 9.39 approaches one and the

level shifter behaves as an emitter follower for ac signals which is what we

wanted, so this is good!

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