You are on page 1of 22

5th Semester BE (CBCS) EC Syllabus

Updated on 14-08-17 with
(i) Management and Entrepreneurship – Modification of Title, Some topics according to Text
books and Revised Module-5 and (ii) Operating Systems – with more details of Sections of
Text Book to be referred (iii) HDL Lab – with tools note

MANAGEMENT AND ENTREPRENEURSHIP DEVELOPMENT
B.E., V Semester, EC/TC/EI/BM/ML
[As per Choice Based Credit System (CBCS) scheme]
Subject Code 15ES51 IA Marks 20
Number of Lecture 04 Exam Marks 80
Hours/Week
Total Number of 50 (10 Hours / Module) Exam Hours 03
Lecture Hours
CREDITS – 04
Modules
Module-1
Management: Nature and Functions of Management – Importance, Definition,
Management Functions, Levels of Management, Roles of Manager, Managerial Skills,
Management & Administration, Management as a Science, Art & Profession (Selected
topics of Chapter 1, Text 1).
Planning: Planning-Nature, Importance, Types, Steps and Limitations of Planning;
Decision Making – Meaning, Types and Steps in Decision Making (Selected topics from
Chapters 4 & 5, Text 1).
Module-2
Organizing and Staffing: Organization-Meaning, Characteristics, Process of
Organizing, Principles of Organizing, Span of Management (meaning and importance
only), Departmentalisation, Committees–Meaning, Types of Committees; Centralization
Vs Decentralization of Authority and Responsibility; Staffing-Need and Importance,
Recruitment and Selection Process (Selected topics from Chapters 7, 8 & 11, Text 1).
Directing and Controlling: Meaning and Requirements of Effective Direction, Giving
Orders; Motivation-Nature of Motivation, Motivation Theories (Maslow’s Need-
Hierarchy Theory and Herzberg’s Two Factor Theory); Communication – Meaning,
Importance and Purposes of Communication; Leadership-Meaning, Characteristics,
Behavioural Approach of Leadership; Coordination-Meaning, Types, Techniques of
Coordination; Controlling – Meaning, Need for Control System, Benefits of Control,
Essentials of Effective Control System, Steps in Control Process (Selected topics from
Chapters 15 to 18 and 9, Text 1).
Module-3
Social Responsibilities of Business: Meaning of Social Responsibility, Social
Responsibilities of Business towards Different Groups, Social Audit, Business Ethics
and Corporate Governance (Selected topics from Chapter 3, Text 1).
Entrepreneurship: Definition of Entrepreneur, Importance of Entrepreneurship,
concepts of Entrepreneurship, Characteristics of successful Entrepreneur, Classification
of Entrepreneurs, Myths of Entrepreneurship, Entrepreneurial Development models,
Entrepreneurial development cycle, Problems faced by Entrepreneurs and capacity
building for Entrepreneurship (Selected topics from Chapter 2, Text 2).
Module-4

Product Planning and Development Process. Selection of product.N Reddy. Problems for Small Scale Industries. Project Levels. State Level Institutions (Selected topics from Chapter 4. 3. Features and Phases of Project management. ISBN. Limitations and Differences. Characteristics of a Project. Origin of PERT and CPM. McGraw Hill Education. Each full question carries 16 marks. ISBN 978-81-7758-260-4. Innovation and Leadership perspective by Harold Koontz. Steps in Project formulation. Impact of Globalization and WTO on SSIs. Project Classification. selecting one full question from each module. The project Cycle. Project Identification: Feasibility Report. Each full question will have sub questions covering all topics under a module. Aspects of a Project. Growth and Performance of Small Scale Industries in India. ISBN: 978-81-8488-801-2. Question paper pattern The question paper will have TEN questions. Principles of Management – P. 2017.C Tripathi. Policies & Schemes of Central Level Institutions. (Selected topics from Chapters 16 to 20 of Unit 3. Network. ISBN-13:978-93-5260-535-4. Product Innovation. Search for a Business idea: Introduction. Ancillary Industry and Tiny Industry (Definition only) (Selected topics from Chapter1. Text 2). Advantages. Network Techniques. The Adoption process. Product Planning and Development Strategy. Project Management Processes. Need for Network Techniques. Sickness in SSI sector. Project Feasibility Analysis. Government policy and development of the Small Scale sector in India. .Modern Small Business Enterprises: Role of Small Scale Industries. Text Books: 1. Text 3). Module-5 Projects Management: A Project. Heinz Weihrich McGraw Hill Education. The students will have to answer 5 full questions.978-93-392-2286-4. Concepts of Projects and Classification: Introduction. Meaning of Projects. Dynamics of Entrepreneurial Development and Management by Vasant Desai. Institutional Support for Business Enterprises: Introduction. Project Evaluation. There will be two full questions (with a maximum of Three sub questions) from each module. Project Formulation: Meaning. Text 2). Importance of Network Analysis. Sequential Stages of Project Formulation. Choosing an Idea. Essentials of Management: An International. 6th Edition. Entrepreneurship Development Small Business Enterprises. 2. P. Pearson Education 2008. HPH 2007. Concepts and definitions of SSI Enterprises. CPM. Project Design and Network Analysis: Introduction. Steps in PERT. 10th Edition 2016.Poornima M Charantimath. Reference Book: 4.

design of FIR filters using . Frequency sampling structure. and chirp-z transform. Properties of DFT. Module-5 Structure for FIR Systems: Direct form. Cascade form. Hanning and Bartlett windows. Module-3 Radix-2 FFT algorithm for the computation of DFT and IDFT–decimation-in-time and decimation-in-frequency algorithms. analog to analog frequency transformations. Bilinear transformation. V Semester. Module-4 Structure for IIR Systems: Direct form. There will be 2 full questions (with a maximum of four sub questions) from each . its relationship with other transforms. Module-2 Additional DFT properties.E. DIGITAL SIGNAL PROCESSING B.Rectangular.the circular convolution. Fast-Fourier-Transform (FFT) algorithms: Direct computation of DFT. overlap-save and overlap-add method. Goertzel algorithm. DFT as a linear transformation. Lattice structure. Parallel form structures. multiplication of two DFTs. need for efficient computation of the DFT (FFT algorithms). IIR filter design: Characteristics of commonly used analog filter – Butterworth and Chebyshev filters.. FIR filter design: Introduction to FIR filters. Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. Electronics & Communication Engineering / Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC52 IA Marks 20 Number of Lecture 04 Exam Marks 80 Hours/Week Total Number of 50 (10 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 04 Modules Module-1 Discrete Fourier Transforms (DFT): Frequency domain sampling and reconstruction of discrete time signals. Hamming. Linear Phase. use of DFT in linear filtering. Design of IIR Filters from analog filter using Butterworth filter: Impulse invariance.

Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. 3. Reference Books: 1. K. Tata Mc-Graw Hill. 2007. New Delhi. Digital Signal Processing. 2007. Proakis & Monalakis. Discrete Time Signal Processing. 2. PHI. Digital signal processing – Principles Algorithms & Applications. Pearson education. module. selecting one full question from each module Text Book: 1. Lee Tan: Elsevier publications. Oppenheim & Schaffer. 3rd Edition. Mitra. S. . 2003. 2010. Digital Signal Processing. 4th Edition.

(Text1) Module-3 Gate-Level Modeling Modeling using basic Verilog gate primitives. sequential and parallel blocks. data types. Font conventions. initial and always.. parts of a simulation. operator types. event control. (Text1) Module-4 Behavioral Modeling Structured procedures. emergence of HDLs. stimulus block. Electronics & Communication Engineering/ Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC53 IA Marks 20 Number of Lecture 04 Exam Marks 80 Hours/Week Total Number of 50 (10 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 04 Modules Module-1 Overview of Digital Design with Verilog HDL Evolution of CAD. description of and/or and buf/not type gates. trends in HDLs. typical HDL-flow. min. hierarchical name referencing. Design tool flow. delay specification. (Text1) Module-2 Basic Concepts Lexical conventions. blocking and non-blocking statements. Verilog HDL B. rise. expressions. loops. why Verilog HDL?. Using VHDL for Design Synthesis. Multiway branching. operators. system tasks. operands. connecting ports. differences between modules and module instances. and typical delays. design block. Shortcomings. max. (Text1) Modules and Ports Module definition. conditional statements. port declaration. generate statement.E. V Semester. (Text1) Module-5 Introduction to VHDL Introduction: Why use VHDL?. . (Text1) Dataflow Modeling Continuous assignments. (Text1) Hierarchical Modeling Concepts Top-down and bottom-up design methodology. delay control. compiler directives. fall and turn-off delays.

Design entities. There will be 2 full questions (with a maximum of four sub questions) from each module. Philip R. Identifiers. A simple design. “VHDL for Programmable Logic”. Pearson Education. 2. “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall). Second edition. Wiley. Data types. “The Verilog Hardware Description Language”. Data objects. “Verilog HDL: A Guide to Digital Design and Synthesis”.Entities and Architectures: Introduction. Thomas. Tripura Sundari. selecting one full question from each module Text Books: 1. 2. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. . Ciletti. Samir Palnitkar. 2006. Springer Science+Business Media. Reference Books: 1. PHI/Pearson education. (Text 2) Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. and Attributes. “Design through Verilog HDL”. 2016 or earlier. Moorby. Fifth edition. Second Edition. Padmanabhan. Donald E. Kevin Skahill. LLC. 3. Michael D.

Muroga.3.2 of Text 1). Measure of information.6. BCH Codes ( Section 8.3. Huffman codes. Types of Errors.s Theorem.3.4.9.1. Module-4 Error Control Coding: Introduction. System Entropies. Channel Models.4.4.3.4. Lempel – Ziv Algorithm (Sections 3. Mutual Information. Encoding of the Source Output.2 of Text 2).1.4 of Text 1).8. Module-2 Source Coding: Source coding theorem. Channel Matrix. Single Error Correcting hamming Codes. 4. methods of Controlling Errors.1 of Text 1). Shannon Fano Encoding Algorithm. Extended Huffman coding.1.. Information content of message. Joint probabilty Matrix.3. Binary Symmetric Channel. Module-3 Information Channels: Communication Channels ( Section 4. Examples of Error control coding.4 – Article 5 of .9. Error Detection and Correction (Sections 9. Table lookup Decoding using Standard Array.2.3 of Text 1).3.3. Error Detection and Error Correction Capabilities of Linear Block Codes. Prefix Codes.2.2.9.E. Channel Capacity. Channel Capacity of : Binary Symmetric Channel.3. V Semester. types of Codes. Binary Cyclic Codes: Algebraic Structure of Cyclic Codes.7. Contineuos Channels (Sections 4.10 of Text 3). Syndrome Calculation. 9. Module-5 Some Important Cyclic Codes: Golay Codes. Encoding using an (n-k) Bit Shift register. Binary Erasure Channel. Electronics & Communication Engineering / Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC54 IA Marks 20 Number of Lecture 04 Exam Marks 80 Hours/Week Total Number of 50 (10 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 04 Modules Module-1 Information Theory: Introduction. Average Information content of symbols in Long dependent sequences. 4.3. Average Information content of symbols in Long Independent sequences. Markov Statistical Model of Information Sources.4. INFORMATION THEORY AND CODING B.6. Kraft McMillan Inequality property – KMI (Section 2. Shannon’s Encoding Algorithm (Sections 4. Linear Block Codes: matrix description of Linear Block Codes.7 of Text 3).9. Entropy and Information rate of Markoff Sources (Section 4.3. Arithmetic Coding.

Transform domain approach. There will be 2 full questions (with a maximum of four sub questions) from each module. 1986 . Reference Books: 1. Information Theory and Coding. TMH. Digital and analog communication systems. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. P.Ganesh Rao. Ltd. The Viterbi Algorithm) (Section 8. Mullick. Trellis and State Diagram. II edition. 2016. Cengage Learning. Digital communication. ISBN: 9780134724058. Digital Communications – Fundamentals and Applications.S. 3.Article 1 of Text 2). 2007 2. 8. 2017. Bernard Sklar. Das. .5 – Articles 1. Question paper pattern: The question paper will have ten questions Each full question consists of 16marks. Wiley India Pvt. Information Theory and Coding. ITC and Cryptography.N. 2015. Shivaprakasha.Text 2). J. Wiley. Convolution Codes: Convolution Encoder.6. John Wiley India Pvt. K. Pearson Education. Sam Shanmugam.Technology & Engineering 3. John Wiley India Pvt. K. ISBN:978-81-265-5305-1. 2. Code Tree. Principles of digital communication. D. Muralidhar Kulkarni . K. Chatterjee. S. 2008. 4. Ltd. K. Ltd. Simon Haykin. Time domain approach. Second Edition. selecting one full question from each module Text Book: 1. 1996.2 and 3. K. Ranjan Bose.Hari bhat.

ballistic carrier transport. Module-4 Carbon Nanostructures: Carbon molecules. Electronic conduction. coherence and dephasing. Classification of Nanostructures. growth of vicinal substrates. quantum hall effect. lithography and etching. crystalline solids. Quantum well width fluctuations. Giant molecular solids. characterization of semiconductor nanostructures: optical electrical and structural (Text 1). electrostatically induced dots and wires. quantum confined stark effect. effects of nanometerlength scale. ordering of nanosystems (Text 1). (Text 2) . electronic density of states (Text 1).. self-assembly techniques. NANOELECTRONICS B. nonlinear effects. Microscopic techniques. quantum wires. Field ion microscopy. diffraction techniques: bulk and surface diffraction techniques (Text 1). Electronic properties of atoms and solids: Isolated atom. band offsets. Free electron models and energy bands. (Text 1). charging effects. V Semester. super-lattices. scanning probe techniques. intraband absorption. collidal quantum dots. cleaved-edge over growth. epitaxial growth of quantum wells. quantum dots. Development milestones in microfabrication and electronic industry.E. semiconductor nanocrystals. Carbon Nanotubes. Inorganic semiconductor nanostructures: overview of semiconductor physics. Electronics & Communication Engineering / Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC551 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of 40 (8 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 03 Modules Module-1 Introduction: Overview of nanoscience and engineering. Physical processes: modulation doping. Module-2 Characterization: Classification. Carbon Clusters. Quantum confinement in semiconductor nanostructures: quantum wells. resonant tunneling. Periodicity of crystal lattices. Fabrication methods: Top down processes. phonon bottleneck. Inter band absorption. application of Carbon Nanotubes. Light emission processes. strain induced dots and wires. thermally annealed quantum wells. Bottom up processes methods for templating the growth of nanomaterials. Bonding between atoms. Module-3 Fabrication techniques: requirements of ideal semiconductor. Moore’s law and continued miniaturization.

photonic structures. MEMS (Text 1). Donald W Brenner. QWIP’s. Sensors Based On Physical Properties. Characterization. What is Sensor and Nanosensors?. Reference Books: 1. 2. . Sergey E. Frank J Owens. What makes them Possible?. selecting one full question from each module Text Books: 1. Smartdust-Sensor for the future. Ed Robert Kelsall. quantum cascade lasers. 2003. Charles P Poole. Order From Chaos. Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. Nanosensors Based On Quantum Size Effects. Perception. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. Module-5 Nanosensors: Introduction. (Text 3) Applications: Injection lasers. TMH. Gerald J Iafrate. 2007. “Nanoscale Science and Technology”. Ed William A Goddard III. John Wiley. coulomb blockade devices. Nanobiosensors. Jr. John Wiley. “Nano: The essentials-Understanding Nanoscience and Nanotechnology”. NEMS. 3. Electrochemical Sensors. Copyright 2006. “Introduction to Nanotechnology”. Mark Geoghegan. optical memories. There will be 2 full questions (with a maximum of four sub questions) from each module. biological tagging. CRC press. Ian Hamley. Lyshevski. Reprint 2011. “Hand Book of Nanoscience Engineering and Technology”. single-photon sources. T Pradeep.

5.4. capabilities and limitations of finite state machines. 10. 10. (Sections 13.4. 13. 12. Fault location experiments: Preset experiments. Synthesis of Threshold networks: Unate functions. Machine identification.2 of Text) Module-2 Reliable Design and Fault Diagnosis: Hazards. The lattice of closed partitions. 7. (Section 10. (Section 12. Boolean differences. The Fault Table. 13.. 8. 13. Fault detection in combinational circuits. An application of state splitting to parallel decomposition. (Sections 7.6.1. 8. 10.7 of Text) Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. 8. Simplification of incompletely specified machines.1.2. Distinguishing experiments. Fault detection experiments.4. 12. Fault detection by path sensitizing. 13. Covers and generation of closed partitions by state splitting: Covers. The implication graph.E. static hazards. State assignment using partitions: closed partitions. Input dependence and autonomous clocks.3. Fault detection in combinational circuits: The faults. 12.1. V Semester. Machine equivalence. The map as a tool in synthesizing threshold networks. .2. 12. Adaptive experiments. Second algorithm for the design of fault detection experiments. (Sections 8.2.6 of Text) Module-5 State–Identification and Fault Detection Experiments: Experiments. 13. Electronics & Communication Engineering / Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC552 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of 40 (8 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 03 Modules Module-1 Threshold Logic: Introductory Concepts: Threshold element. The minimization Procedure. Design of Hazard-free Switching Circuits. Reduction of output dependency. 8. 13. 12.3.5 of Text) Module-3 Sequential Machines: Capabilities. SWITCHING & FINITE AUTOMATA THEORY B.2. Covering the fault table. State equivalence and machine minimization: k-equivalence.3. Identification and realization of threshold functions. Homing experiments.1. Design of diagnosable machines.3.5.4 of Text) Module-4 Structure of Sequential Machines: Introductory example. Minimization and Transformation The Finite state model and definitions. Elementary Properties. capabilities and limitations of threshold logic.1.

Larry L. Reference Books: 1. selecting one full question from each module Text Book: Switching and Finite Automata Theory . Fault Tolerant And Fault Testable Hardware Design. Cengage Learning. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. 2010 ISBN: 0070993874. 2014. ISBN: 978-1-133-62847-7. There will be 2 full questions (with a maximum of four sub questions) from each module.Parag K Lala.Zvi Kohavi. McGraw Hill. 1985. Prentice Hall Inc. . 2. Digital Circuits and Logic Design.-Charles Roth Jr. 2nd edition. Kinney.

Multi programming. Virtual Memory Management. Operation of an OS. FIFO.1 of Text).1 to 10. Threads. . V Semester. Module-4 File Systems: File systems and IOCS.E.2 to 2. 4. Time Sharing Systems. Demand Paging. Mailboxes. Deadlocks in resource allocation. Kernel and User level Threads.3. 3. Non-Contiguos Memory Allocation. Segmentation with paging. 3. 4.1 to 3.3. Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. Deadlocks. Electronics & Communication Engineering / Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC553 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of 40 (8 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 03 Module-1 Introduction to Operating Systems OS. Module-2 Process Management: OS View of Processes. Interface between File system and IOCS. Segmentation.5 to 5.3.4. LRU page replacement policies (Topics from Sections 5. 6. Batch processing. Allocation of disk space. Module-5 Message Passing and Deadlocks: Overview of Message Passing. 1. Resource allocation techniques. OPERATING SYSTEM B.4. Deadlock Prevention (Topics from Sections 10.3. Efficiency. Module-3 Memory Management: Contiguous Memory allocation.8 of Text).8 of Text). except Optimal policy and 6.3. Non-preemptive scheduling.2 .3.1 to 7.4.2. Resource state modelling.9. Computational Structures.3.1 to 11. Goals of an OS. Classes operating System. Preemptive Scheduling. Implementing file access (Topics from Sections 7.RR and LCN. 11. Implementing message passing. Real Time and distributed Operating Systems (Topics from Sections 1. File Operations. Paging Hardware. Paging. 2. 3.FCFS and SRN. File Organizations. Fundamental State Transitions. Directory structures. medium term and short term scheduling in a time sharing system (Topics from Sections 3.4. File Protection.4. System Performance and User Convenience. Long term.1 to 6.5 of Text). Deadlock detection algorithm. PCB. 4. VM handler.2.3.1 of Text).1.. 3.

Design of operating systems. Reference Books: 1. selecting one full question from each module Text Book: Operating Systems – A concept based approach. John Wiley India Pvt. Operating systems concepts. by Dhamdare. 5th edition. There will be 2 full questions (with a maximum of four sub questions) from each module. 2nd edition.2001. Operating system–internals and design system. Pearson Education. 3. Ltd. 2001. 2006. . Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. 2. Tannanbhaum. William Stalling. Silberschatz and Galvin. 4th ed. TMH. TMH.

Langevin’s Theory of paramagnetism. Electronics & Communication Engineering/ Telecommunication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC554 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of 40 (8 Hours/Module) Exam Hours 03 Lecture Hours CREDITS – 03 Modules Module-1 Band Theory of Solids: Introduction to free electron theory. Kinds of Polarizations. Non-polar Dielectric Materials. Paramagnetic Materials. ELECTRICAL ENGINEERING MATERIALS B. Ampere’s Lam in Dia. Para and Ferromagnetism. Formation of Solid Material. Ferrimagnetic Materials. Explanation for Discontinuities in E vs.. Formation of Band in Metals. Relation between Magnetic Permeability and Susceptibility. Origin of Magnetism. Classification of Materials on the Basis of Band Structure. Concept of Hole. Para and Ferromagnetism. Hard and Soft Ferromagnetic Materials and their Applications. Ferrimagnetic Materials. Kroning-Penney Model. Three electric Vectors.E. Explanation for Insulating and Metallic Behavior of Materials. Explanation for differences in the Electrical properties of different Materials. Polar Dielectric Materials. Properties of some important Magnetic Materials. Explanation of Dia. Magentostriction and Magnetostrictive Materials. Electric Susceptibility and Static Dielectric constant. polar dielectric in ac and dc fields. temperature dependence of dielectric constant. Modification in the Langevin’s Theory. Classification of magnetic Materials. Effect of Dielectric medium upon capacitance. Basic Terms in Magnetism. Various kinds of Dielectric Materials. behavior of dielectric materials. V Semester. Number of energy states per band. behavior of polar dielectric at high frequencies. Ferromagnetic Materials. Hysteresis in Ferroelectric Materials. Module-4 . Gauss’s Law in a Dielectric. Langevin’s Theory of Diamagnetism. Applications of Ferroelectric Materials in Devices. Module-2 Magnetic Properties of Materials: Introduction. Formation of Bands in Semiconductors and Insulating Materials. Dielectric loss. macroscopic electric field. Important Characteristics of a Band Electron. Classification of Dielectric Materials at Microscopic level. Microscopic Electric field. Dielectric strength and Dielectric Breakdown. Module-3 Behavior of Dielectric Materials in AC and DC Fields: Introduction. Hystersis and Hystersis loss. Characteristics of Diamagnetic Materials. K curve. Anti-Ferromagnetism and Neel Temperature.

“An Introduction to Electrical Engineering Materials”. 2014. Resistivity Ratio. Question paper pattern: The question paper will have ten questions Each full question consists of 16marks. Low- Resistivity Copper Alloys. Reference Books: 1. 2012. S. Classification of conducting materials. frequency dependence of superconductivity. characteristics of superconductors. standard conductors. ISBN-9788121906661. Thiruvengadam.Indulkar and S. Electrical contact materials and their selection. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. Selection of the insulating material.Conductivity of Metals and Superconductivity: Introduction. current status of high temperature superconductors. classification of Insulating materials on the basis of structure. Thermal Conductivity of Materials. practical applications of superconductors. Thermal characteristics . Application of Lorentz-Drude free-electron theory. classification of contact materials. KASAP. selecting one full question from each module Text Book: 1. Insulating gases. explanation of superconductivity phenomenon. 2. There will be 2 full questions (with a maximum of four sub questions) from each module. chemical properties of Insulating materials. difference in properties of Hard-Drawn and Annealed copper. Variation of resistivity of alloys with temperature. Ohm’s law. Preparation of Tungsten Filaments. Discovery of superconductivity. R K Shukla and Archana Singh. Materials for Lamp Filaments. McGraw Hill.O. Seebeck’s Experiment.S. “Electrical Engineering Materials” McGraw Hill. Free-electron theory of metals. . Liquids and solids and their characteristics.. Explanation for the dependence of electrical resistivity upon temperature. C. superconductivity and transition temperature. Thermoelectric Series. Module-5 Electrical Conducting and Insulating materials: Introduction. “Electronic Materials and Devices” 3rd edition. S. ISBN: 978-1-25-90062-03. comparison between some popular Low-Resistivity Materials. ISBN-978-0-07-064820-3. other important properties of Insulating materials. Heat produced in Current Carrying Conductor. change in thermodynamic parameters in superconducting state. Effect of various parameters on Electrical Conductivity. superconducting materials. Thermoelectric Effect.

(Text: Ch5.1.12) .6.5. DAC. Serial Peripheral Interface. 8.Clock System. (Text: Selected topics from Ch4 & Ch7 and Ch7.1.7. MSP430 MICROCONTROLLER B. Asynchronous Serial Communication. LCD interfacing.4. Memory. (Text: Ch9 – 9.5.6. 8.12 (without 9.1 upto 9. 9. Program Examples.7.Comparator-A. 9. Basic Timer1.2. Low Power Modes of Operation.1. Memory Mapped Input and Output.3 to 1. Timer-A: Timer Block.5.1) Module-2 Addressing Modes & Instruction Set. 9.4) Module-5 Digital Input-Output and Serial Communication: Parallel Ports. Peripherals in MSP430.8. Edge Aligned PWM. Internal Operational Amplifiers. Ch5.5) Module-3 Clock System. (Text: Ch5 . 10.4. V Semester.1. Simple PWM.1. and 10. Central Processing Unit. 5.8 upto 5. LCD interfacing.2 to 8. Interrupt Service Routines.2.7. 8. Ch10 – 10. Toggle the LED state by pressing the push button. Real Time Clock. Exceptions: Interrupts and Resets.3) Module-4 Analog Input-Output and PWM . MSP430 family. Electronics & Communication Engineering [As per Choice Based Credit System (CBCS) scheme] Subject Code 15EC555 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of 40 (8 Hours / Module) Exam Hours 03 Lecture Hours CREDITS – 03 Modules Module-1 MSP430 Architecture: Introduction – Where does the MSP430 fit. Instruction set. 9.5. Read Input from a Switch. Ch 6-6.10. Ch8 -8.1.1 to 2.7. Ch2.. Design of PWM. Watchdog Timer. Interrupts and Operating Modes. Capture/Compare Channels.5 upto 9.1.E. Lighting LEDs. ADC12.7 upto 5. ADC10.Addressing Modes. The outside view. Interrupts from Timer-A. (Text: Ch1.2. Constant Generator and Emulated Instructions.1.8.8 upto 9.5. Asynchronous Communication with USCI_A.12. Communications. Clock Generator. 6. The inside view-Functional block diagram.2.7. Flashing LEDs. Sigma-Delta ADC.8. 9.2 to 5.6 to 6. Interrupts. What happens when an interrupted is requested.1).11. 9.

References: 1. selecting one full question from each module Text Book: John H Davies. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions. 2003. Newnes Publications. User Guide from Texas Instruments. Newnes Publications. There will be 2 full questions (with a maximum of four sub questions) from each module. This activity can be considered for the evaluation of 5 marks out of 20 Internal assessment marks. reserved for the other activities. . 2. Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. Elsevier. Elsevier.Evaluation of Internal Assessment Marks: It is suggested that at least a few simple programs to be executed by students using any evaluation board of MSP430 for better understanding of the course. Chris Nagy. Embedded Systems Design using TI MSP430 Series. MSP430 Microcontroller Basics. 2008.

Auto and cross correlation of two sequences and verification of their properties 4. Verification of sampling theorem. 2. V Semester.) (ii) DFT computation of square pulse and Sinc function etc. Linear convolution of two sequences 10. 2. (i) Verification of DFT properties (like Linearity and Parsevals theorem. 5. Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.E. Circular convolution of two sequences 11. All laboratory experiments are to be included for practical examination.. Linear and circular convolution of two given sequences. distributive and associative property of convolution. EC/TC [As per Choice Based Credit System (CBCS) scheme] Subject Code 15ECL57 IA Marks 20 Number of Lecture 01Hr Tutorial (Instructions) Exam Marks 80 Hours/Week + 02 Hours Laboratory=03 Exam Hours 03 CREDITS – 02 Laboratory Experiments Following Experiments to be done using MATLAB / SCILAB / OCTAVE or equivalent: 1. 8. Design and implementation of FIR filter to meet given specifications (using different window techniques). Commutative. 7. Design and implementation of IIR filter to meet given specifications. 6. N-point DFT of a given sequence 12. Solving a given difference equation. 3. Impulse response of first order and second order system 13. Computation of N point DFT of a given sequence and to plot magnitude and phase spectrum (using DFT equation and verify it by built-in routine). Implementation of FIR filter Conduct of Practical Examination: 1. DSP Lab B. Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero. Following Experiments to be done using DSP kit 9. etc. . 3.

EC/TC [As per Choice Based Credit System (CBCS) scheme] Subject Code 15ECL58 IA Marks 20 Number of Lecture 01 Hr Tutorial (Instructions) Exam Marks 80 Hours/Week + 02 Hours Laboratory = 03 Exam Hours 03 CREDITS – 02 Note: Programming can be done using any compiler. Write Verilog code to realize all the logic gates 2. comparator. 4 bit binary to gray converter e. 4. Download the programs on a FPGA/CPLD boards such as Apex/Acex/Max/Spartan/Sinfi/TK Base or equivalent and performance testing may be done using 32 channel pattern generator and logic analyzer apart from verification by simulation with tools such as Altera/Modelsim or equivalent. 2 to 4 decoder b. Write a Verilog program for the following combinational designs a.. and tri-state the out bus when the enable line is low. de-multiplexer. . 8 to 3 (encoder without priority & with priority) c. HDL Lab B. Write a Verilog code to model 32 bit ALU using the schematic diagram shown below ALU should use combinational logic to calculate an output based on the four bit op-code input. d. ALU should decode the 4 bit op-code according to the example given below. Laboratory Experiments Part–A: PROGRAMMING 1. 8 to 1 multiplexer. ALU should pass the result to the out bus when enable line in high. Write a VHDL and Verilog code to describe the functions of a Full Adder using three modeling styles.E. V Semester. Multiplexer. 3.

A NAND B 8. 2.change the frequency. Design a 4 bit binary. using Verilog code. Write HDL code to interface Hex key pad and display the key code on seven segment display. 6. OPCODE ALU Operation 1. 3. direction of DC and Stepper motor. Write HDL code to control speed.) using DAC . A-B 3. Strictly follow the instructions as printed on the cover page of answer script for breakup of marks. Square.. Write HDL code to accept Analog signal. Temperature sensor and display the data on LCD or Seven segment display. . Ramp etc. Write HDL code to generate different waveforms (Sine. A*B 5. A+B 2. Write HDL code to simulate Elevator operation. Develop the Verilog code for the following flip-flops. 2. Part–B: INTERFACING (at least four of the following must be covered using VHDL/Verilog) 1. Write HDL code to display messages on an alpha numeric LCD display. A Complement 4. 4. A AND B 6. BCD counters (Synchronous reset and Asynchronous reset) and “any sequence” counters. 3. A XOR B 5. 5. Conduct of Practical Examination: 1. A OR B 7. Triangle. 6. D. All laboratory experiments are to be included for practical examination. SR. JK and T. Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.