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Most realistic decision-making processes make use of prior information stored in memory, apart
from the input information fed from outside at the time of making the decision. Moreover
information generated during a decision-making process is often considered to be useful for future,
and is as such stored in memory concurrently with the decision-making. Clearly, a digital circuit
must incorporate the same features also. Such digital circuits, incorporating memory, are called
sequential circuits, as the operating has to be in repetitive sequence of the following two steps:

(i) Generate the output variables from the input variables and the contents of the memory
in accordance with the truth table and/or Boolean functions.

(ii) Alter the contents of the memory according to the prescribed logic for memory update.

14.1 Asynchronous vs Synchronous Memory

The general structure of a sequential circuit is shown in Fig, 14.1.1 The variables X1, X2 ....Xm are
the external inputs to the whole circuit. These, along with the variables Q1, Q2 ....Qn stored in the n
memory elements, form the inputs to the combinatorial circuit. Some of the outputs of the
combinatorial circuits Z1, Z2 ....Zp act as the inputs to the memory elements, while the rest Y1,
Y2 ....Yk form outputs. Let us now visualise the situation that would arise if the memory is
asynchronous, i.e. Q1, Q2....Qn instantaneously respond to any change in Z1, Z2 ....Zp. The
combinatorial circuit would immediately produce output corresponding to the new values of Q1,
Q2 ....Qn in accordance with its truth table. The resulting values of Z1, Z2 ....Zp would again modify
Q1, Q2 ....Qn and the circuit will never attain a steady state. Such a situation, know as the Race
condition, can be avoided by using synchronous memory, which incorporates a Clock (generally
abbreviated as CK) input besides the input variables comprising the truth table. New output
corresponding to the current values of input is loaded into a synchronous memory only at a
specific transition (0 1 or 1 0) of the voltage applied to the CK terminal. Let us next
consider the two types of memory elements used for obtaining asynchronous memory and
synchronous memory respectively.

14.2 Latch AN Asynchronous Memory Element

The simplest memory element consists of two NOR gates or two NAND gates connected in a loop,
as shown in Fig. 14.2.1. The inputs of the NOR latch are denoted by S (Set) and R (cleaR), while
those of the NAND latch is denoted by S , R so that both the circuits have the same truth table.
The truth table is easily verified from an inspection of the circuits. Inputs S = 0 and R = 0
maintain the past values of Q and Q with Q = Q and hence this mode is said to be the HOLD
mode. The input combination S = 0, R = 1, forces Q = 0 and Q = 1; and the input combination S =
1, R = 0 forces Q = 1 and Q = 0. These two options are accordingly referred to as the CLEAR and
SET modes respectively. Note that S = 1, R = 1 is the only input combination resulting in Q' Q
and the truth table is different for the two circuits. As a result, return to the HOLD mode either
from the SET mode or from the CLEAR mode presents no ambiguity in the value of Q, but a
return to the HOLD mode from the combination S = 1, R = 1 makes the values of Q and Q totally
unpredictable. Latches are therefore never used with S = 1, R = 1. One normally maintains the
latch in the HOLD mode with S = 0, R = 0. Momentary activation of the S input by making S = 1
and then reverting back to S = 0, with R maintained at level 0, sets the latch; this state (Q =1 and
Q = 0) is maintained indefinitely as long as S = 0, R = 0. Similarly, momentary activation of the
R input, with S maintained at level 0, clears the latch, and this state (with Q = 0 and Q = 1) is
maintained thereafter as long as S = 0, R = 0.
14.3 Flip-Flop Synchronous Memory Element

A synchronous memory element can be obtained simply by adding a clocking provision to a latch
so that the inputs of the latch are allowed to change only at a specific transition of the applied
clock input. One could try the simple circuit shown in Fig. 14.3.1 (a), which gives the latch inputs
in terms of the inputs S and R as
SL = SCK and RL = RCK (14.3.1)
This circuit does ensure that the output Q remains unaffected by the S and R inputs as long as CK
= 0 and responds to the existing values of S and R according to the latch truth tables at the CK
makes the transition from 0 to 1. But any further change in S and R will continue to affect S and R
as long as CK = 1, and hence Q may change any time when CK = 1. This circuit is thus not a fully
synchronous memory element.
One way of achieving a proper synchronous operation is to add one more latch, leading to the
Master-Slave configuration shown in Fig. 14.3.1 (b). The master latch, having output QM has the
SM = SCK and RM = RCK. (14.3.2)
While the slave latch, having output Q, has inputs
___ __ ___
SS = QMCK and RS = QMCK. (14.3.2)

Thus with CK = 1, QM responds to the current values of S and R, but as SS = RS = 0, Q remains in
the HOLD state. On the other hand, with CK = 0, Q responds to the current value of QM, which in
turn remains in the HOLD state as SM = RM = 0. The only time Q can change is therefore at the
10 transition of CK, when the value of QM, acquired in response to the values of S and R during
the previous half-cycle of the clock, is transferred to Q. The memory element thus developed is a
Master-Slave S-R flip-flop having a negative-logic clock. If CK and CK are interchanged in Fig.
14.3.1(b), Q would get its new value at each 01 transition of CK, and the flip-flop would be said
to have a positive-logic clock.
The master-slave structure is not the only way to obtain a synchronous memory element. In fact,
one sometimes desires to eliminate the effect of the inputs during the half-cycle preceding the
active edge of the clock. This is achieved in the so-called Edge-Triggered Flip-flop by
incorporating some more circuitry (usually a third latch), which ensures that the values of the
synchronous inputs (S and R) are allowed to only of the clock determine the output only during the
active edge. Irrespective of whether a flip-flop is designed for master-slave operation or for edge-
triggered operation, asynchronous inputs allowing the flip-flop to be directly set or directly cleared
without having to wait for the active edge of he clock are generally provided in a flip-flop for the
sake of initialisation (after switching on the d-c power supply) and for other asynchronous
requirements. A given flip-flop may have one or both of these asynchronous inputs, which are
labelled either as S and R, as in a latch, or as SD (Set Direct) and RD (cleaR Direct). The positive-
logic and negative-logic conventions are followed for these inputs also as for the clock input, a
negative-logic input being indicated by a small circle at the respective input(s) in the flip-flop
The circuit symbols and the truth table of an S-R flip-flop are shown in Fig. 14.3.1(c), where Qn
denotes the value of the output Q after the nth active edge of the clock, and Qn+1, the value of Q
after one more active edge. Note that the combination S = 1, R = 1 is illegal just as in case of the
latch and, as such, this input combination has to be carefully excluded in any circuit employing an
S-R flip-flop. Naturally, this constraint is quite troublesome, and circuit designers attempted to
incorporate provisions so that all the possible input combinations are acceptable. The fruit of these
efforts is the J-K flip-flop, which retains the two unconditional (i.e. independent of Qn) actions
SET and CLEAR of an S-R flip-flop, and adds one more conditional (i.e. Qn-dependent) action
the TOGGLE besides the HOLD available in an S-R flip-flop. The circuit symbols and the truth
table of J-K flip-flop are given in Fig. 14.3.2(a).

For many applications, e.g. data storage, one needs only the unconditional (SET and CLEAR)
modes of operation, while for many others, e.g. counters, the actions dependent on Qn are
sufficient. Two more types of flip-flops, each having a truth table, which is a subset of the
complete J-K truth table, are therefore defined.
The D flip-flop shown in Fig. 14.3.2(b), utilises half of the capability of a J-K flip-flop, operating
only either in the SET mode or in the CLEAR mode. The other two modes HOLD and TOGGLE
available in J-K flip-flop are the only modes of operation of a T-flip-flop, shown in Fig. 14.3.2(c).
Of the four kinds of flip-flops, the J-K flip-flop is obviously the most versatile and is as such most
widely used in a variety of applications. The S-R flip-flop finds limited use as it can always be
replaced by a J-K flip-flop. The D flip-flop is extensively used for data storage (hence the name
D), as the data applied at D is directly stored at every clock pulse. The T flip-flop is convenient for
making simple counters, as its output can toggle for every clock pulse, thus keeping track of the
number of clock pulses received, as will be seen in following sections. J-K and D flip-flops are the
commonly available commercial ICs. It is, of course al ways possible to obtain any of the four
kinds of flip-flops by using one given flip-flop and gates, if necessary. Fig. 14.3.3 shows the
configurations necessary for obtaining the J-K, D and T flip-flops using an S-R flip-flop and gates.
14.4 Ripple Counters Using T Flip-Flop

The simplest way of obtaining a counter is to cascade T flip-flops in the manner shown in Fig.
14.4.1 with the output Q of each flip-flop acting as the clock of the next. Such a counter is called
Ripple counter, and counts the clock pulses applied to the first flip-flop in the binary code as
indicated by the truth table. As the flip-flops have all been assumed to use a positive-logic clock,
and since all of them are in the TOGGLE mode (T = 1), every 10 transition of Q0 causes Q1 to
toggle, every 10 transition of Q1 causes Q2 to toggle and so on, resulting in a straight binary
counter, whose output Qn Qn-1..Q2 Q1 Q0 represents, in the binary code, the number of input
pulses received since the initial state where all the flip-flops were cleared. The counter recycles
after 2n pulses have been received. The number of different states that any counter has in one
complete cycle is called its CYCLE LENGTH. Thus for an n-bit ripple counter, the cycle length is
given by
N = 2n (14.4.1)
Let us next explore the possibility of obtaining a cycle length other than a power of 2. It is obvious
that if the required cycle length N is such that
2n > N > 2n-1 (14.4.1)
then the counter has to consist of n flip-flops, for an n-bit counter can at most have 2n different
states representing as many different counts. The simplest way to achieve any specified cycle
length N is to allow the counter to count 0 to N-1 in the usual fashion using the ripple counter
configuration, and force the counter to go back to the all-zero state corresponding to zero count as

soon as the Nth input pulse is received. This is illustrated in Fig. 14.4.2 where a 3-bit ripple counter
has been modified by this technique to give N = 6, The output of the AND gate remains 0 for all
states of the counter except the one representing count 6, and as such the CLEAR inputs of the
flip-flops, assumed to be positive-logic, remain disabled. The counter thus counts from 0 to 5 in
the binary code regardless of the additional AND gate. As soon as the sixth pulse arrives, the AND
gate output goes to 1, thereby forcing Q0, Q1 and Q2 to go immediately to 0 and thus returning the
counter to the initial all-zero state. The counter therefore has only six states, the state
corresponding to count 6 being just momentary, and a cycle length N = 6 has been obtained.
14.5 Synchronous Counters Using J=K Flip-Flops

Ripple counters suffer from a speed limitation due to the fact that the new value of output is
established with a cumulative delay as one goes from the first flip-flop to the second, from the
second to the third and so on. Thus, when eighth pulse arrives, the count registered by a 4-bit
counter having outputs Q0, Q1, Q2 and Q3 changes in the following sequence:

Q3 Q2 Q1 Q0

0 1 1 1

0 1 1 0

0 1 0 0

0 0 0 0

1 0 0 0

Clearly, for a large value of n, there can be quite a significant delay between the instant when Q0
attains a new value in response to an input pulse rippling through the entire chain of flip-flops.
Moreover, if any decoder is used to sense the occurrence of a particular state (i.e. a combination of
the flip-flop outputs), there may be a number of false alarms raised by the decoder as sharp
spikes will appear at the decoder output every time the desired state comes momentarily during
transitions: e.g. a 4-bit ripple counter will give decoder spikes for count 8 at each of the
transitions 910, 1112 and 150. For high-speed counting where the clock frequency may be
of the order of 100 MHz or more, therefore, all the flip-flops comprising the counter are clocked
simultaneously by the same input clock pulse, and the count sequence is obtained by controlling
the J-K inputs by the values of Q0, Q1, Q2 , Qn. Such counters are called Synchronous Counters.
Unlike a ripple counter, a synchronous counter does not have any natural sequence, and can
therefore be designed for any prescribed sequence. One merely has to obtain the required values of
the J-K inputs of each flip-flop at each, state, and design a combinational circuit for generating the
J-K inputs from the flips-flop outputs according to the resulting truth table. It is convenient, at this
stage, to express the truth table of a J-K flip-flop in the form of an excitation table as given below.

Table 14.5.1 Excitation Table of J-K Flip-Flop

Existing Value Next Value of Mode of Required Required

of Q (Qn) Q (Qn+1) transition J K
0 0 Hold/Clear 0

0 1 Set/Toggle 1

1 0 Clear/Toggle 1

1 1 Hold/Set 0

Let us illustrate the procedure for the design of synchronous counters by two examples. The first
example is a 3-bit counter with the sequence 100, 010, 001 100, .. for its output QA, QB QC. The
required values of JA, KA, JB, KB, JC, KC, can be obtained by using Table 14.5.1 and can be directly
written in the form of K-maps, as given in Fig. 14.5.1. Note that all states not included in the
desired sequence are DONT CARE states, as the counter will never enter one of these states after
being properly initialised to one of the states forming part of the desired sequence. Exploiting these
DONT CARE states, the following simple expressions for the J-K inputs are obtained by the usual
K-map technique.
JA = QC, JB = QA, JC = QB, KA = KB = KC = 1. (14.5.1)
The design of an UP/DOWN decade counter is taken up as the other example. The K-map the up
counting sequence 0000, 0001 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 0000.... and the
down-counting sequence 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000, 1001.....
are separately shown in Fig. 14.5.2. The states 1010, 1011, 1100, 1101, 1110 and 1111 are DONT
CARE states. The design expression for the J-K inputs are given in Table 14.5.2.
Table 14.5.2 Design Expressions for UP/DOWN Decade Counter.



Down 1 1 (D+C) A A DA BA CBA A

For any of the J-K inputs, the final design expression is of the form
Y = MYUP + MYDN, (14.5.2)
where M is the mode control (M=0 for up counting and M=1 for down counting), YUP is the
expression for UP counting and YDN, the expression for DOWN counting.

14.6 Shift Register Counters

A synchronous counter can also be built with D-flip-flops. Such counters are known as shift
register counters, as a shift register is nothing but a number of D- flip-flops connected in tandem,
as shown in Fig. 14.6.1. Shift registers of various lengths (i.e. with different numbers of flip-flops)
are commercially available as ICs. Long shift registers generally have only the D-input to the first
flip-flop and Q-output of the last flip-flop available at accessible terminals, besides the clock and
power supply terminals. Shift register counters will also therefore be only with configurations
using a single serial input and a single serial output. The two choices for generating the input D1
from the output Qn are:
D1 = Qn (14.6.1)
D1 = Qn (14.6.2)
These two configurations, shown in Fig. 14.6.2 are called the RING COUNTER and the
JOHNSON (or MOBIUS) COUNTER respectively. It is easy to see that an n-bit ring counter can
have a maximum cycle length of n, while an n-bit Johnson counter has maximum cycle length of
2n. Let us illustrate this by considering 3-bit and 4-bit Ring as well as Johnson counters.
Depending on the initial state, the counters go into different sequences as given in Fig. 14.6.2.