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VLSI LAB-1 REPORT

LAB: VLSI Name: M.B.Vinay

Date: 09-Aug-2017 Id no: N130492

Day: Wednesday Class: ss-04

Roll no: 33

Basic Gates
And Gate

Code

Simulation

Elaborated Design
OR GATE
Code

Simulation

Elaborated Design
XOR-Gate
Code

Simulation

Elaborated Design
XNOR-GATE
Code

Simulation

Elaborated Design
NAND GATE
Code

Simulation

Elaborated Design
NOR-GATE
Code

Simulation

Elaborated Design
Half adder
Code

Simulation

Elaborated Design
Full adder
Code

Simulation

Elaborated Design
Two by one mux
Code

Simulation

Elaborated Design
Four by one mux
Code

Simulation
Elaborated Design