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You are on page 1of 33

WEAK INVERSION IN

ANALOG AND DIGITAL CIRCUITS

Eric A.Vittoz

CSEM, Centre Suisse d'Electronique et de Microtechnique SA

Jaquet-Droz 1, CH 2007 Neuchtel, Switzerland

eric.vittoz@csem.ch

Examples of analog circuits.

Exploratory analysis of weak inversion logic [4,5].

Weak inversion page 2

n-channel symbols:

VD B

D VS

B VG G VD

ID

VS S S D ID

n+ n+ p-channel VG

p local substrate G

n-channel VG

W,L width, length of the channel S D ID

Cox gate capacitance per unit area VS VD

UT = kT/q ( = 26 mV at 300K) B

V = local non-equilibrium voltage in channel : channel voltage

(quasi-Fermi potential of electrons)

at source end of channel: V = VS

at drain end of channel: V = VD

Qi local mobile inversion charge in channel (electrons)

VT0 gate threshold voltage for V=0.

CSEM, E. Vittoz, 2003

Weak inversion page 3

DRAIN CURRENT

VD

ID =

Qi with = Cox W (=mobility)

Given by: - dV

C ox L

VS

- Qi /Cox

VG-VT0 V G const.

strong inversion, slope factor n =1.2 to 1.6

slo

-Qi VP -V

exponential

pe

ox UT

-n

V

0 VS VD

VG - VT0

Pinch-off voltage VP

n

Weak inversion already possible for VS=0 if VG<VT0 ("subthreshold")

CSEM, E. Vittoz, 2003

Weak inversion page 4

(vertical axis magnified)

VG-VT0>0

slope

slope

-n

ID/ ID/

-n

0 V 0

VS VD VD V

VP<0 VS

VP>0 VG-VT0<0

Weak inversion page 5

current IF current IR

=

ID IF

IR

V V V

VS VD VS VD

Drain current is the superposition of independent and symmetrical

effects of source and drain voltages.

basic property of long-channel transistors, independent of current [6].

Transistor saturated if IRIF, then ID=IF.

CSEM, E. Vittoz, 2003

Weak inversion page 6

VP-V VP -VS,D

-Qi/Cox = 2nUT e UT 2nUT thus: IF,R = IS e UT

2

Definition: specific current of the transistor: IS = 2nUT

Introducing VP (VG-VT0)/n and ID =IF - IR, this yields:

VG-VT0 V V

- S - D

ID = IS e nUT (e UT - e UT ) for IF and IR IS

IF IR

Weak inversion page 7

VG VS VD VT0

- -

ID = ID0 e nUT ( e T - e UT

U ) where ID0=IS e- nUT

VG,VS = const. VS, VD const. VG, VD const.

ID

ID /IF log ID

ID0 log

1 ID0

5% saturation

1/n

1

VD-VS pe VG

e

VS

slo

op

UT U T -

sl

0 UT

0 1 2 3 4 5 6

VD-VS VG VS

ID ~ 1-e - U ID ~ e nUT -

T

ID~ e UT

CSEM, E. Vittoz, 2003

Weak inversion page 8

a. From charge analysis [7,8]: IF,R

IF,R 1+4 I -1

VP -VS,D S

= 1+4 I -1 +ln

UT S 2

cannot be inverted to express IF,R(VP,VS,D)

IF,R VP -VS,D

b. Interpolation formula: = ln2 (1 + e ) [9]

IS 2U T

IF,R VP -VS,D

IS = e U T for VP -VS,D UT (weak inversion)

IF,R VP -VS,D 2 for VP -VS,D UT (strong inversion)

IS = 2UT

Only 3 parameters: VT0, n (inside VP) and IS (or ) to model the current

from weak to strong inversion.

CSEM, E. Vittoz, 2003

Weak inversion page 9

IF,R b with:

IS 102 strong

a VP =(VG-VT0)/n

current

1

ID = IF - IR

weak

10-2

10-4 VP -VS,D

-20 0 20 40 60 UT

voltage

Definition: Inversion coefficient: IC = the larger of IF/IS and IR/IS

weak inversion: IC 1

moderate inversion: IC 1

VDSsat 2

strong inversion: IC = 2U 1

T

Weak inversion page 10

model a

1.0

gm strong inv.asymptote: gm= 2ID/n

nUT 0.8

ID model b

0.6

0.4

0.2

weak moderate strong inv.

0 IC=ID/IS

0.01 0.1 1 10 100

gm/ID is maximum in weak inversion.

CSEM, E. Vittoz, 2003

Weak inversion page 11

ID = IS e nUT ( e - UT - e - UT )

+ translinear circuits and log domain filters

+ exponential : + max. Ion/Ioff for given voltage swing

intermodulation in RF front ends

+ min. VDSsat

+ max. intrinsic voltage gain

+ min. gate voltage

+ min. input noise density for given ID

+ min. gate capacitance + max. bandwidth for given kT/C and ID

+ max. gm/ID : + min. input offset voltage

+ gm(ID) linear max. output noise current for given ID

max. current mismatch : ID VT0

+ gm independent of

dominated by VT -mismatch: =

ID nUT

UT

Low speed: fT

2L2

CSEM, E. Vittoz, 2003

Weak inversion page 12

Scaling-down of process:

dimension scaling by factor k

all voltages decreased by k, except U T:

- analog circuits: VDSsat must be decreased by k, thus

VDSsat 2

decreased by k2

2U

IC =

T

- digital circuits: VB decreased by k, thus

VB -VT0 2 2

ICon = decreased by k

2nUT

Weak inversion approached for constant temperature T.

VDSsat

Transition frequency: fT = 2 increased by k

2L

- weak inversion with L=100nm : fT >4 GHz

CSEM, E. Vittoz, 2003

Weak inversion page 13

I I

VDS2 T2 All transistors in weak inversion with:

T3 T4

2 4

VD2 = P and =M

3 5

T1 V T5

DS1 VR

substrate

for P = M = 8 : VDS1=5UT,

Weak inversion page 14

V+ I2 mirror T1-T2

T3

K

slope

T6 T4T3

I2 P(stable)

source I1

4

3 -T

T

sink T2KT1

or

irr

T5

m

T1 R VR I1

Q (unstable)

V-

Weak inversion page 15

Resistor replaced by transistor T8 in conduction [10]:

T6 =T3 =T4 =T7 and T5 = T1 V+

T6 T3 T4

T7

T8 and T9 in strong inversion with I

I I

8 =A9 (A1 to have T8 in conduction) I

T2

T2 and T1 in weak inversion with T5 T1 V R T9

2 = K1

V-

T8

yields: 2

I = 2n8UT.Aln2K = IS8.Aln2K

Useful to bias transistors at inversion coef.IC independently of process.

If mobility ~ T -2, then compensation by UT2 : I ~ IS independent of T

CSEM, E. Vittoz, 2003

Weak inversion page 16

[11,12,13,6]

Consequence of basic property ID = F(VS) - F(VD):

linear with respect to currents

thus equiv. for currents to a resistive prototype, with Gi=1/Ri~ISi

ground in res. prototype correspond to saturated transistors.

example of application: current-mode linear attenuator (e.g. R-2R).

In weak inversion:

linearity of currents even for different gate voltages

VGi

with Gi = 1/Ri ~ ISi exp

nUT

Weak inversion page 17

CALCULATION OF HARMONIC MEAN [14,13]

ground 0 IN I

0* 0*

GN GN GN* GN*

I Ik

IN Ik

Gk 0*

Gk G Gk* Gk*

I1 I1

0*

G1 G1 G1* G1*

V- V-

resistive prototype pseudo-resistive version

(0*=pseudo-ground)

1

Series combination of Gi : G =

1/Gi harmonic mean

1 Ihm

Same voltage across G and Gi, thus I = =

1/Ii N

Can be used as a fuzzy AND gate.

CSEM, E. Vittoz, 2003

Weak inversion page 18

TRANSLINEAR CIRCUITS

With bipolar transistors: With MOS transistors in weak inversion: [16,17]

Ii [15]

+ (VGi - VSi) = (VGi - VSi) VGi

+ +

VBEi VSi

+ Ii -1

with: Ii

+ VGi Ii

+ common substrate

n -VSi = UT ln ID0i

+ and - directions of BEi If + and - are alternated then: pairs of equal

(any sequence) VGi both sides of equation:

VBEi = VBEi VGi VGi /n for each pair,

+ and then

Ii

with: VBEi= UT ln I

si

Otherwise: separate wells connected to

Ii Isi sources to impose VSi = 0

+ + =

=

Ii Isi Precision degraded by VT0 mismatch

CSEM, E. Vittoz, 2003

Weak inversion page 19

supply voltage

Dynamic power consumption: Pdyn = f C V VB

logic swing

Weak inversion model can be rewritten as

VGS VDS

ID = I0 e nUT 1 - e- nU

T

- minimum swing V for given Ion/off, hence

- minimum Pdyn for given Ioff

VT0+(n-1)VS

- with: I0 = IS e- adjustable by VS.

nU T

Assumptions on process:

1. Threshold VT0 close to 0 (VS cannot be too negative).

2. Triple well (true twin well): separate local p and n substrates

- adjustment of I0 by VS for n- and p-channel.

CSEM, E. Vittoz, 2003

Weak inversion page 20

inverter

Normalized voltages vk=Vk /UT

Ip

8 VB

In

high and low logic states

Vi Vo

C

le

n=1.6

ab

6

st

vH (high) V-

4 ble

sta

ta

vB me

swing

2

bistable for VB > 1.91UT

stable vL (low) 95% swing for VB = 4UT

0 2 4 6 8

normalized supply voltage vB

Weak inversion page 21

Since VL=VB-VH >0, static current Istat at each state is larger than I0

1.2

I0

1.0

0.9

0.8

1 2 4 6 8

normalized supply voltage vB

Weak inversion page 22

Chain of inverters 2Td

VH Vo2 Vo4 Vo6 Vo8

VL

4 vH

von=vin+1

2Td/T0 n = 1.6

2 vB = 4

vo2 vo4 vo6 vo8

1

0 vL

0 1 2 3

normalized time t /T0

Characteristic time : T0=CUT/I0

Transitions become standard after a few stages

Normalized delay time Td/T0 only depends on VB and n.

CSEM, E. Vittoz, 2003

Weak inversion page 23

Td n = 1.6

T0 Approximation:

0.1 CVB CVB

Td

Ion I0eVB/nUT

CVB -V /nU

or I0 e B T

0.01 Td

3 4 5 6 7 8 9 10 11 (for calcul. of Pstat)

normalized supply voltage vB

Weak inversion page 24

FOR STANDARD TRANSITIONS

10-2 n = 1.6

Qsc

QC

0

3 4 5 6 7 8 9 10

normalized supply voltage vB

dynamic power Pdyn fQCVB fCVB2

with static power Pstat = IstatVB I0VB

Weak inversion page 25

POWER-DELAY PRODUCT

proportion of time during which the gate is in transition.

CUT2 2

Then, total power P = Pdyn + Pstat P = vB(/2 + e-vB/n)

Td

PTd 10 =1 0.5

CUT2

power-delay product

0.2

8 n =1.6

0.1

normalized

6

4 0.05

2 0.03

0.01

0 0.003

2 4 6 8 10 12

normalized supply voltage vB

Pdyn dominates for large min. VB for min. PTd

Pstat dominates for small increase VB to increase Ion/Ioff

CSEM, E. Vittoz, 2003

Weak inversion page 26

POWER/FREQUENCY RATIO

-v /n

By re-using =2f Td : P/f = C(nUT)2 (vB/n)2(1+

2

e B )

C(nUT)2

10-4

normalized total power

10-3

100 10-2

e-3 parameter

10-4

10 1 Pstat

10-3

Pdyn e-3 10-2

1

1

4 6 8 2 10 12 14

normalized supply/slope factor vB/n

VBopt and Pmin increase for decreasing

At Pmin : PdynPstat

Increasing I0 does not allow to reduce VB significantly for Td const.

For > 5%, power reduction by >20 compared to Pdyn at 1V.

CSEM, E. Vittoz, 2003

Weak inversion page 27

MAXIMUM SPEED

CVB

Since Td and Ionmax ICon IS (inv. coeff* spec. current), thus:

Ion

VB C

Tdmin

ICon IS

Tdmin(weak) VB C

IS

Weak inversion page 28

60

(using continuous model of ID) VGS 105

nUT

40 103

More voltage swing needed param.

VGS swing

to obtain Ion/Ioff Ion/Ioff

20 10

from continuous current model:

0

10-1 1 101 102 103

"on" inv. coeff. ICon

Degeneration of logic states:

4 vH vB=4

3 n=1.6

reduction of logic swing logic

large increase of static current Istat 2 swing

loss of bistability vL

1 Istat

more supply voltage needed. IS

0

0 1 2 3 4 ICon

CSEM, E. Vittoz, 2003

Weak inversion page 29

NUMERICAL RESULTS

Simple inverter replaced by 3-input NAND-gate:

approx. equivalent to inverter with

L = 3-time that of n-ch transistor

C VB

C = 6-time that of min. inverter

(includes Cinterconnect=C/2).

parameter process A process B unit

min. channel length Lmin 500 180 nm

equiv. spec. current IS 200 400 nA

equiv. load capac. C 20 4 fF

specific energy C(nUT)2 28 4.2 aJ

P/f for =1 VB=4UT 228 44 aJ

(P/f)min for =0.01 and VBopt=6nUT 1.46 0.22 fJ

Pdyn/f at VB=1V 20 4 fJ

fmax1 for =1 and VB=4UT 50 500 MHz

fmax2 for =0.01 and VB=VBopt 0.22 2.56 MHz

Pmin at fmax2 32.5 56.3 nW

CSEM, E. Vittoz, 2003

Weak inversion page 30

should be proportional to UT (PTAT)

need for power-efficient adapter from higher supply voltage.

Asymmetry

p/n asymmetry may result in speed reduction.

Mismatch

dominated by threshold mismatch VT

may result in speed reduction proportional to VT /VB.

Short channel effects: should not drastically degrade the results.

Gate leakage current : should be alleviated by very low VB.

Adjustment of I0 orTd to required value

control by VS with charge pump in loop [18]; n>1 needed (no SOI!)

corresponds to threshold adjustment unavoidable at very low VB.

System architectures and applications.

Weak inversion page 31

(where f is the average transition frequency), thus

avoid idling gates (contrary to traditional CMOS culture)

new architectures needed:

- maximally active gates of minimum speed (max. delay time Td)

- particular problem with RAMs (short Td but sparse activity)

- how? new constraints should result in novel solutions.

partition the system in blocks of comparable and Td

- optimum VB and I0 for each block (separate I0 control).

Maximum frequency much lower than for strong inversion:

best applicable when no high local speed is required

m-parallelize: mTd but same power if same (m units with P/m)

- digital image processing ?

Weak inversion page 32

CONCLUSION

2

approached with scaled-down VB: IC ~ VB

limit for scaled-down VB.

provides maximum gm/ID

bipolar-like behaviour can be exploited in new schemes.

transistor not a switch but a current modulator (Ion/Ioff)

new architectural approaches for max. duty factor .

ultimum (asymptotic) limit for low power*delay.

Low speed, but keeps increasing with 1/L2 in scaled down processes.

Weak inversion page 33

REFERENCES

[1] E.Vittoz and J.Fellrath, "CMOS analog integrated circuits based on weak inversion operation", IEEE J.Solid-State Circuits, vol.SC-12, pp.224-231, June 1977.

[2] E.Vittoz, "Micropower techniques", in Design of VLSI Circuits for Telecommunications and Signal Processing, J.E.Franca and Y.P.Tsividis Editors, Prentice

Hall, 1991

[3]. C.Enz, F.Krummenacher and E.Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current

applications", Analog Integrated Circuits and Signal Processing, Vol.8, pp.83-114, 1995.

[4] R.M Swanson and J.D.Meindl,"Ion-implanted complementary MOS transistors in low-voltage circuits", IEEE J.Solid-State Circuits, vol.SC-7, pp.146-153, April

1972.

[5] E. Vittoz, "Weak inversion for ultimate low-power logic", to be published in Low-Power Electronic Design, ed. C. Piguet, CRC Press LLC (2003?), Chapter 16.

[6] E. Vittoz, C. Enz and F. Krummenacher, "A basic property pf MOS transistors and its circuit implications", Workshop on Compact Modeling, WCM

MSM.2003, Febr. 23-27, San F.rancisco, pp. 246-249. Slide of presentation can be downloaded at www.nanotech2003.com/WCM2003.html#Slides.

[7] M.A. Maher and C. Mead, "A physical charge-controlled model for the MOS transistors", Advanced research in VLSI, Proc. of the 1987 Stanford Conference,

MIT Press, Cambridge MA, 1987.

[8] A. Cunha et al., "An MOS transistor model for analog circuit design", IEEE J.Solid-State Circuits, vol.33, pp.1510-1519, Oct. 1998.

[9] H. Oguey and S. Cserveny, "MOS modelling at low current density", Summer Course on "Process and Device Modelling", ESAT Leuven-Heverlee, Belgium,

June 1983.

[10] H.J.Oguey and D.Aebischer. "CMOS current without resistance."IEEE Journal of Solid-State Circuits, vol 32, pp.1132-1135 July 1997.

[11] K.Bult and G.Geelen, "A inherently linear and compact MOST-only current division technique", Dig. ISSCC Tech. Papers, February 1992, pp.198-199.

[12] E.Vittoz and X.Arreguit,"Linear networks based on transistors", Electronics Letters, vol.29, pp.297-299, 4th Febr. 1993.

[13] E.Vittoz, Pseudo-resistive networks and their applications to analog collective computation, Proc. MicroNeuro97, Dresden

, pp.163-173.

[14] T. Delbrck, "Bump circuit for computing similarity and dissimilarity of analog voltages", Proc. of International Joint Conf. on Neural Networks, vol.1, pp. I -

475-479. 1991.

[15] B. Gilbert, "Translinear circuits: a proposed classification", Electron. Letters, vol.11, p.14, 1975.

[16] A. Andreou and K. Boahen, "Neural information processing II" in Analog VLSI Signal and Information Processing, M. Ismail and T. Fiez, editors, pp.358-409,

McGraw-Hill, 1994.

[17] E.Vittoz, "Analog VLSI implementation of neural networks", published in the Handbook of Neural Computation, Institute of Physics Publishing and Oxford

University Press, USA, 1996.

[18] V. von Kaenel et al. "Automatic adjustment of threshold and supply voltage for minimum power consumption in CMOS digital circuits'', Proc. IEEE Symposium

on Low Power Electronics, San Diego, 1994, pp.78-79.

CSEM, E. Vittoz, 2003

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