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Digital Electronics

Cairo University Faculty of Engineering


Department of Electronics and Electrical Communications
Dr. Karim Ossama Abbas
Fall 2010
Revising CMOS
CMOS has many advantages:
Rail (supply)-to-rail (ground) logic
Good noise performance
Zero static power dissipation
Sharp transition
Major issues with CMOS:
Sat-Sat region is a hidden problem that causes delay
Each output goes to TWO transistors increasing C and delay
The number of transistors is high (2N) leading to high area)
What happens?
What happens to a capacitor with one plate on ground that is
charged and then all connections to it are open circuited?
High impedance nodes

High impedance node Low impedance node

A node with NO connection to A node with a low impedance


supply or ground except through a connection to supply or
very high impedance ground
What we often call floating In practice an ON transistor
with low resistance
In practice related to capacitor
plates after switches are opened Extremely resistant to noise,
active device always pulls
Very noise prone, depends on
node where it wants it to be
charge, no restoration
The dynamic principle
A dynamic gate depends on charge being
kept on a capacitor Clk Mp
A dynamic gate depends on a clock signal Out
that introduces two phases:
Precharge, output set to a high level A
regardless of input C
B
Evaluate, output is evaluated from input
logic
Clk Me
Output is valid logic ONLY IN
EVALUATE
Dynamic gate precharge phase clk is
low
Clk is zero
Mp is ON
Clk Mp
Me is OFF
Out
The output node cannot be pulled
down because there is no path to A
gnd C
Mp pulls Out up B
The capacitor on the output node is
charged Clk Me

Regardless of logic input,


output C is precharged to Vdd
Dynamic gate Evaluate phase clk is
high
Clk is ONE
Mp is OFF
Clk
Me is ON Mp

Only the PDN is in play Out


We have two cases:
A
The inputs cause logic to evaluate to
C
zero (11X, 011, 101) in this case
B
the branches open a path to GND,
the output cap discharges and Out is
ZERO Clk Me

The inputs open no path (010, 100,


000) The output node keeps its
charge
Dynamic gate Evaluate phase clk is
high
The charge from the precharge
phase is kept IF the inputs should
evaluate to a logic ONE Clk Mp
The charge from precharge is lost if Out
the inputs evaluate to logic ZERO
Thus: A
When Clk is low there is no C
logic, Out always goes up in B
preparation
When Clk is high, Out either Clk Me
stays at high or discharges, but this
happens so that the correct logic
value is evaluated
Properties of dynamic logic
Smaller number of transistors (N+2)
High speed
Only 1 Tr gate fanout
Very noise prone
Note if charge on capacitor is lost in evaluate due to noise it
does not regenerate unlike static CMOS
Suffers from severe signal integrity issues
Charge leakage
Charge sharing
Cascading issues
Designing dynamic logic
The PDN is identical to that of static CMOS
There is no PUN
One PMOS and one NMOS surround the PDN and have
clock inputs
Leakage

When transistors are OFF we assume zero current flows


This is not very accurate
Reverse diodes between drain, source, and substrate have a
VERY small current flowing
This is called leakage current
Leakage

Assuming in evaluate we need to evaluate 1


Leakage current in the OFF NMOS transistors slowly leaks
the stored charge to ground
This imposes an upper bound on evaluate time
Solving leakage
The keeper acts in
positive feedback
With 1 output, keeper
is ON
Keeper pumps charge to
preserve the 1 level
Should the keeper be
strong or weak? Wide or
narrow relative to the
NMOS?
Charge sharing
The situation shown requires a 1 output
If Ca is initially at 0 logic level
Once A turns ON the charge on Cl is
shared with Ca and the output voltage
degrades
For F=ABCDE, what input sequence
over two full cycles leads to worst case
charge sharing?

V DDC L + 0.C A = V X (C L + C A )
Solving charge sharing

If all internal nodes are precharged


to the same level as the output
node there will be no charge
sharing
Cascading

Note that only one transition is allowed in evaluate and only 1 to


zero (at output) otherwise charge is lost and cant be replaced
Even in 1 to zero transition, delay in Out1 leads to some charge loss
in Out2 as it sees an illegal 1 to 0 input transition during part of
evaluate
Comparison of logic families

Category/Family Ratioed Static CMOS Dynamic CMOS


Number of Tr. N+1 2N N+2
Loading in gates 1 2 1
Delay Low High Lowest
Logic values Ratioed Rail-to-rail Rail-to-rail
Signal integrity High Highest Low
Static power Non-zero Zero Zero