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4, July 2010

**Fault Diagnosis Algorithm for Analog Electronic Circuits based on Node-Frequency Approach
**

S.P. Venu Madhava Rao madhavaraosp@gmail.com Dr. N. Sarat Chandra Babu & Dr. K. Lal Kishore Abstract: In this paper we present a novel approach to analog electronic circuits fault diagnosis based on selection of both nodes and frequency for the first time as far as we know. Two fault isolation and localization algorithms are presented in this paper. The first algorithm selects nodes and frequencies which isolate all or desired number of faults. The second algorithm presented converts the fault dictionary contents into binary form. Importantly this helps in the automation of the fault diagnosis process. Keywords: Fault Dictionary, Fault Isolation Table, Binary dictionary, singletons. I. Introduction Analog Fault Diagnosis has been of immense research interest for the past three decades and continues to sustain the same zeal even today. The main challenges today in analog fault diagnosis are to design universally accepted fault models, cost effective, faster and accurate diagnosis of faults. Importantly all this is desired even in the presence of inherent characteristics of analog circuits like tolerances, non linearity, in accessible test nodes etc. There are two categories of analog circuit fault diagnosis: Simulation before test (SBT) and Simulation after test (SAT) [1]. The SBT approach involves the generation of fault dictionary by simulating the circuit and then using pattern recognition to identify the faults. This is the most popular method adopted. In SAT approach sufficient measurements are needed to identify faulty parameters. In the SBT approach construction of fault dictionary is an efficient method. Different test measurements like node voltages, current sources, branch currents, frequency measurements etc are used in the construction of fault dictionaries [2]. There are some algorithms developed to find out testable measurements using numerical approach in [3] and [4]. In [5] a new method in the construction of fault dictionary is proposed where a combination of sensitivity based and information channel based approaches are used. Also the construction of integer coded fault dictionary using Quasi-Hamming distance is proposed in this paper. Heuristic methods using evolutionary computation in combination with the Fuzzy logic is presented in [6], the main purpose of such a combination is to generate an optimized frequency test set and also ambiguity sets are provided to avoid take care of tolerance effects. An SBT based approach is proposed in [7] where the fault dictionary is constructed using test node voltages and the method used to approximate is Section wise piecewise linear (SPLF) method. A procedure for the selection of test frequencies is presented in [8]. This is based on the evaluation of algebraic indices and the inverse norm of a sensitivity matrix of the circuit under test. In [9], [10] and [11], fault diagnosis based on different types of neural networks has been proposed. In [12] knowledge base and fuzzy logic have been used in fault diagnosis. The knowledge base is developed in two ways, one by simulations and the second is based on heuristic symptoms observed by the operator. In [13] the ambiguity sets are divided based on the lowest error probability in the construction of fault dictionaries is proposed. This paper used Monte Carlo techniques for sensitivity analysis. In [14] a fault threshold function and a fault criterion have been proposed for the fault diagnosis of circuits with tolerance. An algorithm is proposed in [15], which aims to reduce the size of the fault dictionary. In [16] and [17] different methods and algorithms are used to reduce the size of the fault dictionaries. In [18] time slot specification based approach is used in analog fault diagnosis. For this built in current sensors and test point insertion is used. A sensitivity based approach using randomized algorithms is used to diagnose soft faults in [19].In [20] the algorithm proposed tries to find the minimum number of test point for maximum fault isolation. This approach is based on information measure of the test

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(IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 4, July 2010

points. The diagnosis proposed in this paper [21] is based on global sensitivity analysis method. Also fuzzy logic is used to obtain the sensitivity curves. In [22] an efficient method is applied in the selection of test nodes. This is done by searching for the minimum entropy index based on the available test points. An efficient graph based method is proposed in [23].This method can be used to select optimum test point selection and also can be sued to build DFT. Efficient Inclusion methods and Exclusion methods are proposed in [24] to select or de select test nodes, in other words the faster selection of optimum test points. A novel multi frequency approach is proposed in [25] which drastically reduce the number of test frequencies needed to achieve maximum fault diagnosis. The reduction achieved is better than any known methods. The method proposed in [26] consists of two parts. One is the creation of fault dictionary consisting of nominal and faulty states of the components and second is a novel fault detection and localization algorithm. This paper proposes a novel approach where both test node and multi frequency techniques are used. This approach is used to diagnose all the faults or the desired number of faults. II Node-Frequency Approach In the analog fault diagnosis the prominent methods used are multi node or multi frequency measurements. The research so far has been on developing methods to find out optimum number of test nodes or test frequencies that can identify the desired faults. This in some cases leads to more number of measurements being made thus drastically increasing the size of the dictionary. In this paper we have taken basically nodal analysis and then a choice of test frequencies is made based on [27]. The proposed algorithm selects the nodes and frequencies which isolate all or desired faults. In this paper two algorithms are presented. The first algorithm is for fault isolation and localization. The second algorithm converts the integer coded fault dictionary into a binary dictionary which helps in faster fault isolation. The actual measurements of the CUT are noted down and these values are normalized if necessary. From these values we form ambiguity sets. Now we construct another table called integer coded table using

ambiguity sets. Then the original readings are replaced by integer numbers indicative of the ambiguity set to which these values belong. The test frequency set is represented by f1 to fM, where N is the number of frequencies chosen. The nodes are represented by n1 to nP, where P represents the total number of nodes. The faults are represented by F0(nominal value) to FN, where N represents the total number of faults. Algorithm 1: Step 1: Select the test frequency set (f1 to fM). Step 2: Select the test nodes (n1 to nP) which are accessible for each frequency. Step 3: Note the actual readings of the circuit for the test frequency set and nodes chosen in steps 1 and 2. Step 4: Form the integer coded dictionary using the ambiguity sets. Step 5: Identify unique integer codes called singletons for each row i.e. for each of the nodes selected. Step 6: Identify the node (nK) which has maximum number of singletons for a frequency fJ., where 1<K≤P and 1<J≤M. Select this node-frequency (nK, fJ) pair. If more than one node satisfies this condition, then go to step 9. Step 7: If the number of singletons is equal to N+1, then go to step 12. If else go to next step 8. Step 8: Call Algorithm 2, to form binary dictionary which helps in identifying other nodes from the remaining (P-1) nodes belonging to the frequency fJ, which can identify different faults. If all faults are isolated then go to step 12. Step 9: Find the total number of singletons for each test frequency. Then choose the node belonging to the frequency which has the maximum number of singletons. If more than one frequency satisfies this condition choose any one of the nodes randomly. Step 11: If all the faults or desired number of faults are not isolated, then repeat steps from 6 with the next highest number of singletons. Step 12: Stop

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Algorithm 2: Step 1: Replace all the singletons by the value ‘1’ and others by ‘0’ in the integer coded table, resulting in a binary table. Step 2: If nK is the node chosen, then calculate (nMnK), where 1<M≤P, thus forming another table called Node-Wise Fault Isolation table. This results in three values 0,-1 or 1. The value ‘0’ indicates that the fault has been identified by both nM and nK or both the nodes did not isolate the fault, whereas ‘-1’ indicates that the fault has been isolated by only nK and ‘1’ is an indication that the fault has been identified by the node of interest i.e. nM. Therefore choose the node nM which has maximum number of 1’s. Step 3: Check the total number of faults isolated by the nodes nk and nM. If this sum is equal to P, then Stop, otherwise choose the node which has the next highest number of 1’s. Step 4: Repeat step 3 till the desired fault isolation is achieved or no further isolation is possible. Step 5: Return to Algorithm 1 III. Integer coded dictionary based on ambiguity sets The formation of the Integer coded dictionary based on ambiguity sets is illustrated by an example in this section. Assume that the actual readings of an imaginary circuit under test are given in Table 1 below.

Table 1: Actual readings of the imaginary CUT Node Node-1 Node-2 Node-3 Nominal Fault-1 Fault-2 Fault-3 1.22 1.33 1.45 0.33 0 0 0.78 0.09 0.99 0.34 2.1 2.5

As seen from the Table 1 above, we see that for node -1 measurement, fault-1 and fault -3 have almost the same value and thus belong to the same ambiguity group. Also these two values are the least among all and are assigned values ‘1’. The other values do not belong to any ambiguity group and are assigned values 2 for fault-2 and 3 for nominal, based on the ascending range of the values. Using the same procedure for all the remaining nodes, integer coded fault dictionary is formed and is shown in Table 2. Table 2: Integer Coded Fault Dictionary Node Node-1 Node-2 Node-3 Nominal Fault-1 Fault-2 Fault-3 3 2 3 1 1 1 2 1 2 1 3 4

In the Table 2, we see that node-1 has 2 singletons, node-2 has 2 singletons and node 3 has 4 singletons. IV Illustration The circuit used here is a 2nd order Butterworth High Pass Filter as shown in Fig. 1. The circuit has been simulated using Tina Spice software. The faults chosen are taken as 50% increase or decrease in the component values. Thus CUT has been simulated for these faults by changing the component values by ±50%.

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(IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 4, July 2010

**Figure 1: Second Order Butterworth-High Pass Filter
**

R2 R3

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C1 C2

6

V1 15

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+

Using the Step1 from the Algorithm 1, we have chosen the test frequency fT= {500Hz, 800 Hz, 1000Hz, 1200Hz, and 1500Hz}. From Step 2, we have chosen four nodes with the assumption

that all these nodes are accessible. Using Step3 and 4, the CUT has been simulated and the integer coded dictionary as shown in Table 3 is formed based on the actual readings.

Table 3: Integer coded Dictionary for the HP Filter Frequency=500Hz Nodes/Faults N1 N2 N3 N4 F0 5 2 2 5 F1 7 3 3 6 F2 2 1 1 2 F3 4 2 2 4 F4 7 3 3 9 F5 6 2 2 7 F6 4 2 2 3 F7 8 5 5 10 F8 3 6 6 1 F9 8 4 4 7 F10 1 1 1 1 F11 6 4 4 8 F12 4 1 1 1

Frequency =800 Hz N1 N2 N3 7 6 6 6 5 5 3 4 4 5 5 5 11 9 9 10 7 7 4 5 5 12 10 10 2 1 1 9 7 7 1 3 3 8 8 8 4 2 2

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R5 10k

VG1 R1 R4

N4

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5

12

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11

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Frequency=1000Hz N1 N2 N3 N4 4 6 6 6 3 5 5 5 5 7 7 7 3 5 5 4 8 9 9 12 6 8 8 10 3 4 4 3 7 10 10 11 1 1 1 1 5 7 7 8 2 3 3 3 5 8 8 9 3 2 2 2

Frequency= 1200 Hz N1 N2 N3 N4 5 6 6 6 3 4 4 5 9 9 9 9 4 5 5 4 10 11 11 11 7 8 8 9 3 4 4 3 8 10 10 10 1 1 1 1 6 6 6 7 2 3 3 4 6 7 7 8 4 2 2 2

Frequency=1500Hz N1 N2 N3 N4 5 4 4 7 2 3 3 5 8 9 9 11 3 3 3 4 7 8 8 11 6 6 6 10 2 3 3 3 6 7 7 9 1 1 1 1 5 4 4 7 3 3 3 6 5 5 5 8 4 2 2 2

The number of singletons for each node for the whole frequency set is calculated (Step 5) and tabulated in Table 4. Here the frequencies are f1=500Hz, f2=800Hz, f3=1000Hz, f4=1200Hz and f5=1500Hz. Table 4: Total number of singletons Node/Freq N1 N2 N3 N4 Total f1 4 2 2 8 16 f2 11 8 8 11 38 f3 6 7 7 11 31 f4 7 9 9 9 34 f5 4 7 7 9 27

As seen from the Table 4, node1 and node 4 of frequency set f2, and node 4 of frequency set f3 have maximum number of singletons equal to 11, i.e. these nodes can isolate 11 of the total thirteen faults. We have chosen node 1(or even node 4 can be chosen) of the frequency set f2 i.e. 800Hz as it has maximum number of total singletons (step 9). As the condition mentioned in step 7 is not satisfied, binary table is formed as per step 8. The binary table is formed replacing Table 3 contents by either ‘0’ or ‘1’. All the singletons are replaced by ‘1’and ambiguity sets by ‘0’ (step 1 of Algorithm 2). The binary fault dictionary is shown in Table 5. After the execution of the step 2(Algorithm 2), the results are shown in the Node-wise Fault isolation Table 6.

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Table 5: Binary Dictionary Frequency: 800Hz Nodes F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 N1 N2 N3 N4 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1

Table 6: Node-Wise Fault Isolation Table Frequency: 800Hz Nodes N1 N2-N1 N3- N1 N4- N1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 1 0 0 0 1 -1 -1 0 1 0 0 -1 1 -1 -1 -1 1 0 0 0 1 -1 -1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 -1 -1 0 1 0 0 0 1 0 0 0 0 1 1 1

From the Binary dictionary of Table 5, we can see that the faults isolated are F0, F1, F2, F3, F4, F5, F7, F8, F9, F10, and F11, where as faults F6 and F12 are not isolated. The faults not isolated is deduced from the ‘0’ entry in the corresponding columns. As seen from the Table 6, the total number of 1’s is two for (N4-N1), one for (N3N1) and (N2-N1). So we choose the (N4-N1) column, i.e. node 4 is chosen. The faults isolated by this node 4 are F6 and F12. As seen these are the faults which are not isolated by node 1. In the example discussed in this paper we have been able to achieve 100% fault diagnosis. This

is achieved by a single test frequency of 800Hz and nodes 1 and 4. V. Conclusions In this paper we have presented a novel method using node-frequency approach in analog fault diagnosis. We have presented two algorithms, the first one for choosing the frequencies and nodes for the desired fault isolation and the second is for the generation of binary dictionaries. The effectiveness of these two algorithms was demonstrated using a HP filter circuit.

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References [1] Tsung-Chih Lin, “Analog circuit fault diagnosis under parameter variations based on Type-2 Fuzzy logic systems”, International Journal of Innovative Computing, Information and Control, Vol. 6, No. 5, pp. 2137, May 2010. [2] Jansuz A. Starzyk, Jing Pang, Stefano Manetti and Maria Cristina Piccirilli and Giulio Fedi, “ Finding ambiguity groups in low testability analog circuits”, IEEE Transactions on circuits and systems-I: Fundamental theory and applications, vol. 47, NO.8, August 2000.pp.1125-1137. [3] G.Luculano,A.Liberatore,S.Manetti and M.Marini, “Multi frequency measurement of testability with application to large linear analog systems”, IEEE Transactions on Circuits and Systems, Vol. CAS-23, pp. 644-648, June 1986. [4] M.Catelani, G.Luculano, A.Liberatore, S.Manetti and M.Marini, “Improvements to numerical testability evaluation”, IEEE Transactions on Instrumentation and Measurements, Vol. IM-36, pp. 902-907, December 1987. [5] Jerzy Rutkowski and Jan Machniewski, “ Integer code DC fault dictionary”, ISCAS 2000- IEEE International Symposium on Circuits and Systems, May 28-31.pp 713-716 [6] P.Jantos, D.Grzechca, T.Golenek and J.Rutkowski, “Heuristic methods to test frequencies optimization for analogue circuit diagnosis”, Bulletin of the Polish Academy of Sciences, Technical Sciences, Vol. 56, No. 1, pp. 29-38, 2008. [7] S.Halgas, “Multiple fault diagnosis of non linear circuits using the fault dictionary approach”, Bulletin of the Polish Academy of Sciences, Technical Sciences, Vol. 56, No. 1, 2008. [8] Franseco Grasso, Antonio Luchetto, Stefano Manetti and Maria Cristina Piccirilli, “A method for the automatic selection of test frequencies in analog fault diagnosis”, IEEE Transactions on Instrumentation and Measurement, Vol. 56, No. 6, December 2007

[9] Wei- Qiang Zhang and Chen Xu, “Improved algorithms for circuit fault diagnosis based on wavelet packet and neural network”, International Symposium on Non linear dynamics, Journal of Physics: Conference series 96, pp. 1-7, 2008. [10] Farzan Aminian Mehran Aminian and H.W.Collins, “Analog fault diagnosis of actual circuits using Neural networks”, IEEE Transactions on Instrumentation and Measurements, Vol. 51, No.3, pp. 544-549, June 2002. [11] K.Mohammadi, A.R. Mohseni Monfarad and A.Molaei Nejad, “Fault diagnosis of analog circuits with tolerances by using RBF and BP Neural Networks”, Student Conference on Research Development Proceedings, IEEE, pp. 317321, 2002. [12] Lamiaa Mohamed and A.S. Ibrahim, “Model based Fault diagnosis via parameter estimation using knowledge base and Fuzzy logic approach”, IEEE MELECON, pp. 505-509, May 2002. [13] Jinyan Cai and M.S.Alam, “An algorithm dividing ambiguity sets for analog fault dictionary”, IEEE, 2002.pp8992 [14] Peng Minfing and He Yigang, “Fault dictionary diagnosis based on branch screening for tolerance circuits”, ICSP’04 proceedings, pp. 1488-1491. [15] P.Bernardi, M.Grosso, M.Rabaudengo and M.Sonza Reorda, “A pattern ordering algorithm fro reducing the size of fault dictionaries”, Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06), 2006. [16] David B.Lavo and Tracy Larrabee, “Making cause-effect cost effective: LowResolution fault dictionaries”, ITC

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International Test Conference, IEEE, pp. 278-286, 2001. [17] Baris Arslan and Alex Orailoglu, “Fault dictionary size reduction through test response superposition”, IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE, 2002. [18] Shambhu Upadhyaya, Jae Min Lee and Padmanabhan Nair, “Tie slot specification based approach to analog fault diagnosis using built-in current sensors and test point insertion”, Proceedings of the 11th Asian Test symposium (ATS’02), 2002. [19] Cesare Alippi, Marcantonio Catelani, Ada Fort and Marco Mugnaini, “SBT Fault Diagnosis in analog electronic circuits: A sensitivity-based approach by randomized algorithms”, IEEE Transactions on Instrumentation and measurement, Vol. 51, No. 5, pp. 1116-1124, October 2002. [20] Kranthi K.Pinjala and Bruce C.Kim, “An approach for selection of test points for analog fault diagnosis”, Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI systems (DFT’03), 2003. [21] C.Alippi, M.Catelani, A Fort, M.Mugnaini, “Automatic selection of test frequencies for the diagnosis of soft faults in Analog circuits”, IEEE Instrumentation and Measurement Technology conference, May 2002. pp 1503-1508 [22] Jansuz A. Starzyk, Dong Liu, Zhi-Hong Liu, Dale E. Nelson and Jerzy O. Rutkowski, “Entropy based optimum test points selection for analog fault dictionary techniques”, IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 3, pp. 754-761, June 2004. [23] Jiun-Lang Huang and Kwang-Ting Cheng, “Test point selection for analog

fault diagnosis of unpowered circuit boards”, IEEE transactions on circuits and systems-II: Analog and Digital signal processing, vol.47, No. 10, October 2000. pp 977-987. [24] V.C.Prasad and N.Sarat Chandra Babu, “Selection of Test nodes for analog fault diagnosis in dictionary approach”, IEEE transactions on Instrumentation and measurements, vol. 49, NO.6, pp.12891297, December 2000. [25] N.Sarat Chandra Babu, V.C.Prasad, S.P. Venu Madhava Rao and K.L.Kishore, “Multi-Frequency approach to fault dictionary of linear analog fault diagnosis”, Journal of Circuits, Systems and Computers, Vol. 17, No. 5, pp. 905-928, October 2008. [26] Zbigniew Czaja, “A fault diagnosis algorithm of Analog circuits based on Node-Voltage relation”, 12th IMEKO TC1 & TC7 Joint Symposium on Man Science & Measurement, pp. 297-304, 2008. [27] S.Seshu and R.Waxman, “Fault isolation in conventional linear systems- A feasibility study”, IEEE Transactions on Reliability, R-15, pp. 11-16, 1986.

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In this paper we present a novel approach to analog electronic circuits fault diagnosis based on selection of both nodes and frequency for the first time as far as we know. Two fault isolation and ...

In this paper we present a novel approach to analog electronic circuits fault diagnosis based on selection of both nodes and frequency for the first time as far as we know. Two fault isolation and localization algorithms are presented in this paper. The first algorithm selects nodes and frequencies which isolate all or desired number of faults. The second algorithm presented converts the fault dictionary contents into binary form. Importantly this helps in the automation of the fault diagnosis process.

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