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MODEL NAME : ZAVA1/ZAVC1


PCB NO : DA80011D000 LA-B015P-R1.0

D D

C C

Schematic Document
Intel BoardWell ULT
B
ZAVA1/ZAVC1 B

DIS AMD 25W/M2+DDR3x8


2014-10-17 Rev: 1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/10/17 Deciphered Date 2018/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 1 of 56
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AMD OPAL_128bit_4GB
D D

VRAM 256M*16 64bit


AMD_OPAL

P
a
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e
5
3
~
5
4
DDR 3 *4 PEG 2.0 x4
M2 29x29mm
VRAM 256M*16 64bit

P
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4
7
~
5
2
P
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5
5
~
5
6
DDR 3 *4 Memory Bus (DDR3L)
Dual Channel DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

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1
7
,
1
8
1.35V DDR3L 1600 MHz

eDP Conn. eDP 8GB Max


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3
1
USB 3.0 Port 1
HDMI Conn. DDI Intel USB 3.0 Conn. 1
P
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2
0

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2
4
Port 0
Broadwell ULT-U
Processor USB2.0 Port 2
BGA 1168 Port 1 USB 3.0 Conn. 2

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2
4
C C

Port 2
USB 2.0 Conn. 3

P
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2
5
PCI-E
x1 x1
Port 6 Port 3
Port 4 3D Camera Conn.
NGFF 2230 Ethernet USB3.0 Re-driver

P
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4
6

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4
6
WiFi/WiGi RTL8106E
/BT4.0
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2
6

P
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2
1 Port 4 NGFF 2230

P
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2
6
WiFi/WiGi/BT4.0
Port 7 Digital Camera

P
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3
1
(With Digital MIC)
Port 5
Touch Screen

P
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3
1
SATA HDD Conn. Port 6 Card Reader
Port 0 SATA Rediver SATA3.0
P
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3
2

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3
2

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2
5
RTS5179
B B

Digital Mic.

HD Audio Audio Codec Headphone Jack /

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2
2
ALC3234

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2
2
Mic. Jack combo

SPI ROM SPI Int. Speaker R / L

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2
2
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6
~
1
6
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9

8MB

LPC Bus
I2C
33MHz

ENE KBC PS/2


Int.KBD KB9012 Touch Pad
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2
7

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3
0

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7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/10/17 Deciphered Date 2018/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 2 of 56
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Compal Confidential
File Name : LA-B015P
D D

C C

USB
FFC
RJ45
16 pin
CardReader Slot
HDMI

USB

CardReader/B
USB

B Audio Jack B

FFC
8 pin M/B
# 3D Camera Conn. (@ BOT)
Cable conbined by eDP cable

LED/B
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/10/17 Deciphered Date 2018/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB/DB Drawing
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 3 of 56
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Board ID Table for AD channel


Vcc 3.3V +/- 1%
Ra 100K +/- 1% HSW BOARD ID Table
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID UMA DIS(JET) DIS(Topaz) DIS(OPAL)
0 0 0.000V 0.000V 0.300V 0x00 - 0x0B 0 SSI USB3.0
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C 1 SSI
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26 2 SSI Port1 USB connector 1
D D
3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30 3 PT
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3B 4 PT Port2 USB connector 2
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46 5 PT
6 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54 6 ST Port3
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64 7 ST
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76 8 ST Port4 3D Camera
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87 9 1.0
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96 10 1.0 USB2.0
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA3 11 1.0
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA4 - 0xAD 12 Port0 USB connector 1
13 240K +/- 1% 2.316V 2.329V 2.343V 0xAE - 0xB7 13
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xC0 14 Port1 USB connector 2
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC1 - 0xC9 15
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD3 Port2 USB connector 3 (D/B)
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD4 - 0xDC BDW BOARD ID Table
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDD - 0xE6 Board ID UMA DIS(JET) DIS(Topaz) DIS(OPAL) Port3
C C
19 NC 3.000V 3.300V 3.300V 0xE7 - 0xFF 0 1.0_3D CAM
1 1.0_3D CAM
Port4 MINI Card (WLAN)
SMBUS Control Table
2 1.0_3D CAM
3 SSI(BDW) Port5 Touch Screen Panel
SOURCE BATT Charger VGA DIMM XDP Thermal Sensor FFS 4
5
SSI(BDW)
ULT Port6 Card Reader
SSI(BDW)
EC_SMB_CK1
EC_SMB_DA1
KB9012 V V 6 PT(BDW)
SSI_3D CAM
PT(BDW) Port7 Camera
7 SSI_3D CAM
EC_SMB_CK2
EC_SMB_DA2
KB9012 V V 8
ST(BDW)
PT(BDW)
SSI_3D CAM
PCI EXPRESS
9 PT_3D CAM
SMBCLK
SMBDATA
ULT V V 10 ST(BDW)
PT_3D CAM
ST(BDW) Lane 1
Link 11 PT_3D CAM
SML0CLK ULT 12 1.0(BDW)
ST_3D CAM
SML0DATA
13 1.0(BDW) Lane 2
ST_3D CAM
SML1CLK ULT 14 1.0(BDW)
ST_3D CAM
SML1DATA
15 SSI Lane 3 10/100 LAN
B B
16 PT
17 ST Lane 4 MINI Card (WLAN)
18 1.0
Lane 5 PEG (AMD JET/TOBAZ)
CLOCK SIGNAL ( Diff. 100MHz ) Lane 6

Symbol Note : CLKOUT_PCIE0 SATA

: means Digital Ground


CLKOUT_PCIE1 SATA0 HDD
CLKOUT_PCIE2 10/100 LAN SATA1
: means Analog Ground
CLKOUT_PCIE3 MINI Card (WLAN) SATA2

CLKOUT_PCIE4 dGPU SATA3


A A

CLKOUT_PCIE5

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/10/17 Deciphered Date 2018/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ID Table / Function Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 4 of 56
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2.2K 10K
SMBUS Address [0x9a]

2.2K
+3.3V_ALW_PCH 10K
+3VS

D
MEM_SMBCLK
N-MOS DDR_XDP_WLAN_TP_SMBCLK 202
D
AP2 DIMM1 SMBUS Address [A0]
MEM_SMBDATA
N-MOS DDR_XDP_WLAN_TP_SMBDAT 200
AH1
1K
202 DIMM2
+3.3V_ALW_PCH SMBUS Address [A4]
1K 200

AN1 SML0CLK
MCH 0 ohm
AK1 SML0DATA DDR_XDP_SMBCLK_R1 53 XDP1 SMBUS Address [TBD]
Shark bay 0 ohm
2.2K DDR_XDP_SMBDAT_R1 51

2.2K
+3.3V_ALW_PCH

SML1_SMBCLK
N-MOS EC_SMB_CK2
AN1
SML1_SMBDATA
N-MOS EC_SMB_DA2
AK1

C 2.2K C

2.2K
+3VALW

79 EC_SMB_CK2
80 EC_SMB_DA2

2.2K

2.2K
+3VS_VGA

N-MOS VGA_SMB_CK2 T4 UV28 GPU SMBUS Address [0xXX]


N-MOS VGA_SMB_DA2 T3

2.2K

2.2K
+3VALW

77 EC_SMB_CK1
0 ohm SCL 11 PU701 POWER SMBUS Address [0x12]
0 ohm Charger
B
KBC 78 EC_SMB_DA1 SDA 10
B

KB9012A4 100 ohm 3 PD1 4 BAT_ALERT 3 PBATT BATT SMBUS Address [0x16]
100 ohm CONN
1 6 BATT_PRS 5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/10/17 Deciphered Date 2018/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus/I2C Connection Map
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 5 of 56
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BDW_Pre-QS for DVT2 BDW_QS for DVT2


i3 CPU i3 CPU

HASWELL_MCP_E
UC1A

DDI1_LANE_N0 C54 C45


<20> DDI1_LANE_N0 DDI1_TXN0 EDP_TXN0 EDP_TX0# <31>
i5 CPU DDI1_LANE_P0 C55 B46
D <20> DDI1_LANE_P0 DDI1_TXP0 EDP_TXP0 EDP_TX0 <31> D
i5 CPU DDI1_LANE_N1 B58 A47
<20> DDI1_LANE_N1 DDI1_TXN1 EDP_TXN1 EDP_TX1# <31>
DDI1_LANE_P1 C58 B47
<20> DDI1_LANE_P1 DDI1_TXP1 EDP_TXP1 EDP_TX1 <31>
UC1 I5_2.2G@ DDI1_LANE_N2 B55
<20> DDI1_LANE_N2 DDI1_TXN2
UC1 I5_1.2G@ DDI1_LANE_P2 A55 C47
<20> DDI1_LANE_P2 DDI1_TXP2 EDP_TXN2
DDI1_LANE_N3 A57 C46
<20> DDI1_LANE_N3
DDI1_LANE_P3 B57 DDI1_TXN3 EDP_TXP2 A49 COMPENSATION PU FOR eDP
<20> DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
C50 DDI2_TXN0 A45 +VCCIOA_OUT
FH8065801620204 QH3G F0 2.2G DDI2_TXP0 EDP_AUXN EDP_AUX# <31>
CL8065801674128 QG21 C0 1.2G C53 B45 EDP_AUX <31>
B54 DDI2_TXN1 EDP_AUXP
SA00008990L DDI2_TXP1
SA00007OS0L C49 D20 EDP_COMP 2 1
B50 DDI2_TXN2 EDP_RCOMP A43 EDP_DISP_UTIL 1 2 24.9_0402_1%~D RC71
DDI2_TXP2 EDP_DISP_UTIL EDP_BIA_PWM <10,31>
i7 CPU A53
B53 DDI2_TXN3 @
i7 CPU DDI2_TXP3 RC72
CAD Note:Trace width=20 mils ,Spacing=25mil,
UC1 I7_2.4G@ 0_0402_5% Max length=100 mils.
UC1 I7_1.2G@

1 OF 19 Rev1p2

@
FH8065801620004 QH3E F0 2.4G
CL8065801675027 QG22 C0 1.2G
SA000089A0L
SA00007OT0L

BDW (ES2) CPU for 3D / 4G


UC1 1.8G1600@ UC1 1.6G1600@

CL8065801703601 QGH9 D0 1.8G CL8065801703603 QGHB D0 1.6G


SA00007U90L SA00007UH0L
C UC1 1.6G1333@ C

SYS_RESET#
SYS_RESET# <10>
CL8065801703602 QGHA D0 1.6G
SA00007UG0L
SYS_RESET# 2 1 +3VS
RC362
1K_0402_1%
+1.05VS_PCH 1 2

1 2 H_CATERR# CC17
@ RC58 49.9_0402_1% 0.1U_0402_10V7K
1 2 H_PROCHOT#
RC60 62_0402_5%

H_CPUPWRGD
HASWELL_MCP_E
UC1B
1

1
RC66 CC27 D61 7/15
10K_0402_5% 100P_0402_50V8J H_CATERR# K61 PROC_DETECT MISC XDP_TDI & XDP_TMS add Test Point for Factory. +1.05VS_PCH
@EMI@ PECI_EC N62 CATERR J62
2 <30> PECI_EC PECI PRDY K62
2

JTAG
PREQ E60 XDP_TCK
PROC_TCK E61 XDP_TMS
ESD solution 1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST# 1 2 PCH_JTAG_RST#
<30,34> H_PROCHOT# PROCHOT PROC_TRST PCH_JTAG_RST# <8>
RC67 56_0402_5% THERMAL F63 XDP_TDI R3 0_0402_5%
PROC_TDI F62 XDP_TDO
PROC_TDO XDP_TDO 1 8
CAD Note: H_CPUPWRGD C61 XDP_TCK 2 7
B Avoid stub in the PWRGD path H_PROCHOT# PROCPWRGD PWR XDP_TRST# 3 6 B
while placing resistors RC115 BPM#0
J60 XDP_OBS0_R RC141 1 @ 2 0_0402_1% 4 5
1 H60 XDP_OBS1_R
@EMI@ BPM#1 H61 @ T111 RP45
CC42 BPM#2 H62 @ T112 51_8P4R_5%
22P_0402_50V8J SM_RCOMP0 AU60 BPM#3 K59 @ T113
DDR3 COMPENSATION SIGNALS 2 SM_RCOMP1 AV60 SM_RCOMP0
SM_RCOMP1
DDR3 BPM#4
BPM#5
H63 @ T114 PU/PD for JTAG signals
SM_RCOMP2 AU61 K60 @ T115
AV15 SM_RCOMP2 BPM#6 J61 @ T116
<17> DDR3_DRAMRST#_CPU SM_DRAMRST BPM#7
200_0402_1% 2 1 RC68 SM_RCOMP0 AV61
<17> DDR_PG_CTRL SM_PG_CNTL1
120_0402_1% 2 1 RC69 SM_RCOMP1
2 OF 19 Rev1p2
100_0402_1% 2 1 RC70 SM_RCOMP2
@

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

DDR3_DRAMRST#_CPU
1
CC35 @ESD@

0.047U_0402_16V4Z
2

Place CC35
on BOT

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(1,2/19) eDP,XDP,MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 6 of 56
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Interleaved Memory

HASWELL_MCP_E
UC1D
HASWELL_MCP_E <17> DDR_A_D[32..47]
D UC1C D

<17> DDR_A_D[0..15]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0 DDR_A_D32 AY31 AM38 M_CLK_DDR#2
SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <17> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <18>
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_A_D33 AW31 AN38 M_CLK_DDR2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <17> SB_DQ1 SB_CK0 M_CLK_DDR2 <18>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_A_D34 AY29 AK38 M_CLK_DDR#3
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <17> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <18>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 DDR_A_D35 AW29 AL38 M_CLK_DDR3
SA_DQ3 SA_CLK1 M_CLK_DDR1 <17> SB_DQ3 SB_CK1 M_CLK_DDR3 <18>
DDR_A_D4 AH61 DDR_A_D36 AV31
DDR_A_D5 AH60 SA_DQ4 AU43 DDR_CKE0_DIMMA DDR_A_D37 AU31 SB_DQ4 AY49 DDR_CKE2_DIMMB
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <17> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <18>
DDR_A_D6 AK61 AW43 DDR_CKE1_DIMMA DDR_A_D38 AV29 AU50 DDR_CKE3_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <17> SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <18>
DDR_A_D7 AK60 AY42 DDR_A_D39 AU29 AW49
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_A_D40 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_A_D41 AW27 SB_DQ8 SB_CKE3
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_A_D42 AY25 SB_DQ9 AM32 DDR_CS2_DIMMB#
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <17> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <18>
DDR_A_D11 AP62 AR32 DDR_CS1_DIMMA# DDR_A_D43 AW25 AK32 DDR_CS3_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <17> SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <18>
DDR_A_D12 AM61 DDR_A_D44 AV27
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_A_D45 AU27 SB_DQ12 AL32
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_A_D46 AV25 SB_DQ13 SB_ODT0
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_A_D47 AU25 SB_DQ14 AM35 DDR_B_RAS#
<18> DDR_B_D[0..15] SA_DQ15 SA_RAS DDR_A_RAS# <17> <18> DDR_B_D[32..47] SB_DQ15 SB_RAS DDR_B_RAS# <18>
DDR_B_D0 AP58 AW34 DDR_A_WE# DDR_B_D32 AM29 AK35 DDR_B_WE#
SA_DQ16 SA_WE DDR_A_WE# <17> SB_DQ16 SB_WE DDR_B_WE# <18>
DDR_B_D1 AR58 AU34 DDR_A_CAS# DDR_B_D33 AK29 AM33 DDR_B_CAS#
SA_DQ17 SA_CAS DDR_A_CAS# <17> SB_DQ17 SB_CAS DDR_B_CAS# <18>
DDR_B_D2 AM57 DDR_B_D34 AL28
DDR_B_D3 AK57 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D35 AK28 SB_DQ18 AL35 DDR_B_BS0
SA_DQ19 SA_BA0 DDR_A_BS0 <17> SB_DQ19 SB_BA0 DDR_B_BS0 <18>
DDR_B_D4 AL58 AV35 DDR_A_BS1 DDR_B_D36 AR29 AM36 DDR_B_BS1
SA_DQ20 SA_BA1 DDR_A_BS1 <17> SB_DQ20 SB_BA1 DDR_B_BS1 <18>
DDR_B_D5 AK58 AY41 DDR_A_BS2 DDR_B_D37 AN29 AU49 DDR_B_BS2
SA_DQ21 SA_BA2 DDR_A_BS2 <17> SB_DQ21 SB_BA2 DDR_B_BS2 <18>
DDR_B_D6 AR57 DDR_B_D38 AR28
SA_DQ22 DDR_A_MA[0..15] <17> SB_DQ22 DDR_B_MA[0..15] <18>
DDR_B_D7 AN57 AU36 DDR_A_MA0 DDR_B_D39 AP28 AP40 DDR_B_MA0
DDR_B_D8 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D40 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_B_D9 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D41 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_B_D10 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D42 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_B_D11 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D43 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_B_D12 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D44 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_B_D13 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D45 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_B_D14 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D46 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_B_D15 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D47 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
<17> DDR_A_D[16..31] SA_DQ31 SA_MA8 <17> DDR_A_D[48..63] SB_DQ31 SB_MA8
DDR_A_D16 AY58 AU40 DDR_A_MA9 DDR_A_D48 AY23 AU46 DDR_B_MA9
DDR_A_D17 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_A_D49 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D18 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_A_D50 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
C SA_DQ34 SA_MA11 SB_DQ34 SB_MA11 C
DDR_A_D19 AW56 DDR CHANNEL A AU41 DDR_A_MA12 DDR_A_D51 AW21 AU47 DDR_B_MA12
DDR_A_D20 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_A_D52 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D21 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_A_D53 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D22 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_A_D54 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D23 AU56 SA_DQ38 SA_MA15 DDR_A_D55 AU21 SB_DQ38 SB_MA15
SA_DQ39 DDR_A_DQS#[0..1] <17> SB_DQ39 DDR_A_DQS#[4..5] <17>
DDR_A_D24 AY54 AJ61 DDR_A_DQS#0 DDR_A_D56 AY19 AW30 DDR_A_DQS#4
DDR_A_D25 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_A_D57 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_A_DQS#5
SA_DQ41 SA_DQSN1 DDR_B_DQS#[0..1] <18> SB_DQ41 SB_DQSN1 DDR_B_DQS#[4..5] <18>
DDR_A_D26 AY52 AM58 DDR_B_DQS#0 DDR_A_D58 AY17 AN28 DDR_B_DQS#4
DDR_A_D27 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_B_DQS#1 DDR_A_D59 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#5
SA_DQ43 SA_DQSN3 DDR_A_DQS#[2..3] <17> SB_DQ43 SB_DQSN3 DDR_A_DQS#[6..7] <17>
DDR_A_D28 AV54 AV57 DDR_A_DQS#2 DDR_A_D60 AV19 AW22 DDR_A_DQS#6
DDR_A_D29 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#3 DDR_A_D61 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_A_DQS#7
SA_DQ45 SA_DQSN5 DDR_B_DQS#[2..3] <18> SB_DQ45 SB_DQSN5 DDR_B_DQS#[6..7] <18>
DDR_A_D30 AV52 AL43 DDR_B_DQS#2 DDR_A_D62 AV17 AN21 DDR_B_DQS#6
DDR_A_D31 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_B_DQS#3 DDR_A_D63 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
<18> DDR_B_D[16..31] SA_DQ47 SA_DQSN7 <18> DDR_B_D[48..63] SB_DQ47 SB_DQSN7
DDR_B_D16 AK40 DDR_A_DQS[0..1] <17> DDR_B_D48 AR21 DDR_A_DQS[4..5] <17>
DDR_B_D17 AK42 SA_DQ48 AJ62 DDR_A_DQS0 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_A_DQS4
DDR_B_D18 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_A_DQS5
SA_DQ50 SA_DQSP1 DDR_B_DQS[0..1] <18> SB_DQ50 SB_DQSP1 DDR_B_DQS[4..5] <18>
DDR_B_D19 AM45 AN58 DDR_B_DQS0 DDR_B_D51 AM22 AM28 DDR_B_DQS4
DDR_B_D20 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_B_DQS1 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS5
SA_DQ52 SA_DQSP3 DDR_A_DQS[2..3] <17> SB_DQ52 SB_DQSP3 DDR_A_DQS[6..7] <17>
DDR_B_D21 AK43 AW57 DDR_A_DQS2 DDR_B_D53 AP21 AV22 DDR_A_DQS6
DDR_B_D22 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS3 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_A_DQS7
SA_DQ54 SA_DQSP5 DDR_B_DQS[2..3] <18> SB_DQ54 SB_DQSP5 DDR_B_DQS[6..7] <18>
DDR_B_D23 AM42 AL42 DDR_B_DQS2 DDR_B_D55 AK22 AM21 DDR_B_DQS6
DDR_B_D24 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_B_DQS3 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_B_D25 AK46 SA_DQ56 SA_DQSP7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
DDR_B_D26 AM49 SA_DQ57 AP49 DDR_B_D58 AK18 SB_DQ57
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ58
DDR_B_D27 AK49 AR51 +SM_VREF_DQ0 DDR_B_D59 AL18
DDR_B_D28 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_B_D60 AK20 SB_DQ59
SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ60
DDR_B_D29 AK48 DDR_B_D61 AM20
DDR_B_D30 AM51 SA_DQ61 DDR_B_D62 AR18 SB_DQ61
DDR_B_D31 AK51 SA_DQ62 DDR_B_D63 AP18 SB_DQ62
SA_DQ63 SB_DQ63

B B

4 OF 19 Rev1p2
3 OF 19 Rev1p2
@
@

+1.35V +1.35V +1.35V


1

1
RC14 RC15 RC16
1.82K_0402_1% 1.82K_0402_1% 1.82K_0402_1%
+SM_VREF_CA_DIMM +SM_VREF_CA +SM_VREF_DQ1_DIMM2 +SM_VREF_DQ1 +SM_VREF_DQ0_DIMM1 +SM_VREF_DQ0
2

2
1 2 1 2 1 2
1 1
RC17 1 RC18 RC19
2.2_0402_1% 2.2_0402_1% CC9 2.2_0402_1% CC10
1

1
CC8 0.022U_0402_16V7K 0.022U_0402_16V7K
RC20 RC21 2 RC22 2
0.022U_0402_16V7K
1.82K_0402_1% 2 1.82K_0402_1% 1.82K_0402_1%
change 22nF change 22nF
1

1
change 22nF
1

RC24 RC25
2

2
RC23 24.9_0402_1%~D 24.9_0402_1%~D
24.9_0402_1%~D
2

2
2

A confirm by intel request PDG P141 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(3,4/19) DDR3
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

+RTCVCC

1
RTC Battery RC1
330K_0402_1%

2
+RTCBATT

D PCH_INTVRMEN D
JP14
@

2
2 1
+RTCVCC 2 1

1
+CHGRTC RC10

@
1K_0402_5% JUMP_43X39
RC2
330K_0402_1% +3VS
W=20mils JP12
1 @

2
W=20mils 2 1 1 2 PCH_AZ_SDOUT
+CHGRTC 2 1 +3VLP
3

@ RC3 1K_0402_5%
DC1 JUMP_43X39
BAT54CW_SOT323-3
INTVRMEN - INTEGRATED SUS 1.05V VRM FLASH DESCRIPTOR SECURITY OVERRIDE
ENABLE
For GCLK LOW = DESABLED (DEFAULT)
1

+RTCVCC High - Enable Internal VRs HIGH = ENABLED


1 PCH_RTCX1 Low - Enable External VRs
<19> PCH_RTCX1
CC26
W=20mils 1U_0603_10V6K
2

CC1 XTAL@
1 2 PCH_RTCX1

15P_0402_50V8J

1
XTAL@ XTAL@
RC4
HASWELL_MCP_E
YC1 10M_0402_5% UC1E

2
32.768KHZ_12.5PF_Q13FC1350000

2
CC2 XTAL@
15P_0402_50V8J AW5
1 2 PCH_RTCX2 AY5 RTCX1
1 2 INTRUDER# AU6 RTCX2 J5
INTRUDER RTC SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0_C <32>
RC7 1M_0402_5% PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0_C <32>
C +RTCVCC 1 2 SRTCRST# AV6 B15 SATA HDD C
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0_C <32>
RC5 1 2 20K_0402_5% PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0_C <32>
RC6 20K_0402_5% 2
J8
CC3 SATA_RN1/PERN6_L2 H8
SATA_RP1/PERP6_L2 A17
1U_0402_6.3V6K SATA_TN1/PETN6_L2
1 B17
SATA_TP1/PETP6_L2
1 2 PCH_AZ_BITCLK AW8 J6
1 2 PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 PCH Rx side need use strap pin to update PCIE +/-
PCH_AZ_RST# AU8 B14
PCH_AZ_CODEC_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15 +3VS
<22> PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
@ AU12
CMOS1 SHORT PADS~D 1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
<30> ME_EN HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0

2
1 2 RC8 1K_0402_5% AW10 E5
CC4 1U_0402_6.3V6K AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 RC107
I2S1_SCLK SATA_TP3/PETP6_L0 10K_0402_5%

1
V1 EC_SMI#
CMOS place near DIMM SATA0GP/GPIO34 U1 PCH_GPIO35
EC_SMI# <30>
SATA1GP/GPIO35 V6 ODD_DETECT# +1.05VS_ASATA3PLL
SATA2GP/GPIO36 ODD_DETECT#
AC1 PCH_GPIO37
PCH_JTAG_RST# AU62 SATA3GP/GPIO37
<6> PCH_JTAG_RST# PCH_TRST
PCH_JTAG_TCK AE62 A12 SATA_IREF RC126 1 @ 2 0_0603_1%
PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
PCH_JTAG_TDO AE61 PCH_TDI RSVD K10
PCH_JTAG_TMS AD62 PCH_TDO JTAG RSVD C12 SATA_RCOMP RC131 1 2 3.01K_0402_1%
AL11 PCH_TMS SATA_RCOMP U3 SATA_ACT# SATA Impedance Compensation
RSVD SATALED SATA_ACT# <25>
AC4 within 500 mils
RTC discharge by EC 7/15
PCH_JTAG_TCK add Test Point for Factory.
AE63
AV2
RSVD
JTAGX CAD note:
RSVD Place the resistor within 500 mils of the PCH. Avoid
SRTCRST#
routing next to clock pins.
PCH_RTCRST# reference FFRD sch 0.5

@ 5 OF 19 Rev1p2
6

B D DMN66D0LDW-7_SOT363-6 B
2 G
@
S QC2B
1

@
3

+3VS
<30> RTC_DIS
5 G
D

S
DMN66D0LDW-7_SOT363-6
QC2A HDA for Codec
4
1

RC368
CMOS_CLR1 CMOS setting ODD_DETECT# 1 8
@ 100K_0402_5% Shunt Clear CMOS PCH_GPIO35 2 7
EMI@ R2356 1 2 33_0402_5% PCH_AZ_SDOUT PCH_GPIO37 3 6
<22> PCH_AZ_CODEC_SDOUT
Open Keep CMOS 4 5
2

EMI@ R2357 1 2 33_0402_5% PCH_AZ_SYNC


<22> PCH_AZ_CODEC_SYNC
RP37
ME_CLR1 TPM setting EMI@ R2358 1 2 33_0402_5% PCH_AZ_RST# 10K_8P4R_5%
<22> PCH_AZ_CODEC_RST#

Shunt Clear ME RTC Registers EMI@ R2359 1 2 33_0402_5% PCH_AZ_BITCLK


<22> PCH_AZ_CODEC_BITCLK

Open Keep ME RTC Registers


1 @EMI@
CC5
27P_0402_50V8J
2

+1.05VS_PCH

1 8 PCH_JTAG_TDI
EMI depop location
2 7 PCH_JTAG_TDO
3 6 PCH_JTAG_TMS
4 5

RP48
51_8P4R_5%
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(5/19) RTC,SATA,HDA,JTAG
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

DE7 1 2 RB751V-40_SOD323-2

PCH_GPIO60 2 1 FW_UPDATE
FW_UPDATE <30,46>
RC370 @ 0_0402_5%

+3VALW_PCH
MEM Bus : DDR/XDP/WLAN/TP

D +3VS D

1
R2329 R2330 +3VS
10K_0402_5% 10K_0402_5%

1
HASWELL_MCP_E
UC1G R2331 R2332

2
10K_0402_5% 10K_0402_5%
LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#
<30> LPC_LAD0 LAD0 SMBALERT/GPIO11

2
LPC_LAD1 AW12 AP2 MEM_SMBCLK
<30> LPC_LAD1

2
LPC_LAD2 AY12 LAD1 LPC SMBCLK AH1 MEM_SMBDATA

G
<30> LPC_LAD2 LAD2 SMBDATA
LPC_LAD3 AW11 AL2 PCH_GPIO60 MEM_SMBCLK 6 1
<30> LPC_LAD3 LAD3 SML0ALERT/GPIO60 DDR_XDP_WLAN_TP_SMBCLK <17,18,32>

S
LPC_LFRAME# AV12 SMBUS AN1 SML0CLK
<30> LPC_LFRAME# LFRAME SML0CLK AK1 SML0DATA QC1B
SML0DATA

5
AU4 PCH_HOT# DMN66D0LDW-7_SOT363-6
EMI EMI@ SML1ALERT/PCHHOT/GPIO73 AU3 SML1_SMBCLK

G
R2333 SML1CLK/GPIO75 AH3 SML1_SMBDATA MEM_SMBDATA 3 4
SML1DATA/GPIO74 DDR_XDP_WLAN_TP_SMBDAT <17,18,32>

S
PCH_SPI_CLK_R 1 1 2 15_0402_1% PCH_SPI_CLK AA3
PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T97 QC1A
@EMI@ Y4 SPI_CS0 CL_CLK AD2 @ T98 DMN66D0LDW-7_SOT363-6
C2326 RP39 AC2 SPI_CS1 SPI C-LINK CL_DATA AF4 @ T99
68P_0402_50V8J 2 PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI AA2 SPI_CS2 CL_RST
PCH_SPI_MISO_1 2 7 PCH_SPI_MISO AA4 SPI_MOSI
PCH_SPI_WP1# 3 6 PCH_SPI_WP# Y6 SPI_MISO
PCH_SPI_HOLD1# 4 5 PCH_SPI_HOLD# AF1 SPI_IO2
SPI_IO3
15_8P4R_5%
+3VALW_PCH

R2334 1 2 1K_0402_1% 7 OF 19 Rev1p2


R2335 1 2 1K_0402_1%
@

SML1 Bus : EC/Sensors


C C
U2302
+3VALW_PCH +3VALW_PCH
WINBOND
64M W25Q64FVSSIQ SOIC 8P +3VALW_PCH 9/10. PCH_GPIO60 1 2
Add PU for 3D CAMERA Function 10K_0402_5% RC373

2
SA000039A30 C2327 QH1B
0.1U_0402_10V7K

G
SPI ROM ( 8MByte ) 1 2 RP40 SML1_SMBCLK 1 6 EC_SMB_CK2 <30,33,48>

D
MEM_SMBCLK 1 8

5
U2302 MEM_SMBDATA 2 7 DMN66D0LDW-7_SOT363-6
PCH_SPI_CS0# 1 8 SML1_SMBCLK 3 6

G
PCH_SPI_MISO_1 2 CS# VCC 7 PCH_SPI_HOLD1# SML1_SMBDATA 4 5 SML1_SMBDATA 4 3
DO(IO1) HOLD#(IO3) EC_SMB_DA2 <30,33,48>

D
PCH_SPI_WP1# 3 6 PCH_SPI_CLK_R
4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 2.2K_0804_8P4R_5% QH1A
GND DI(IO0) DMN66D0LDW-7_SOT363-6
64M EN25Q64-104HIP SOP 8P
RP49
@ SML0CLK 1 8
SML0DATA 2 7
3 6
4 5
For GCLK
1K_0804_8P4R_5%
XTAL24_IN
<19> XTAL24_IN

7/15.
Add CC6 for LCD flash issue ( issued by CD Factory)

CC6
3.3P_0402_50V8C
2 1
B B

1M_0402_5%
2

3
4
HASWELL_MCP_E

RC12
UC1F XTAL@
YC2
24MHZ_12PF_X3G024000DC1H

1
2
XTAL@ CC7
C43 A25 XTAL24_IN 15P_0402_50V8J
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 2 1
U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21 RC13 XTAL@
B41 RSVD M21 3.01K_0402_1%
A41 CLKOUT_PCIE_N1 RSVD C26 CLK_BIASREF 1 2
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_AXCK_LCPLL
Y5 RP41 10K_8P4R_5%
PCIECLKRQ1/GPIO19 C35 SWAP_1 SWAP_2 1 8
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 SWAP_2 SWAP_1 2 7
<21> CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
10/100 LAN -------> CLK_PCIE_LAN B42 AK8 3 6
<21> CLK_PCIE_LAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
AD1 AL8 4 5
<21> LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_WLAN# B38 AN15 CLKOUT_LPC0 2 1 EMI@
<26> CLK_PCIE_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC <30>
WLAN(Mini Card)---> CLK_PCIE_WLAN C37 AP15 R2336 22_0402_5%
<26> CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1
WLAN_CLKREQ#_R N1
PCIECLKRQ3/GPIO21 B35
CLK_PEG_VGA# A39 CLKOUT_ITPXDP_N A35
<47> CLK_PEG_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
dGPU---> CLK_PEG_VGA B39
<47> CLK_PEG_VGA CLKOUT_PCIE_P4
U5
<48> PEG_CLKREQ# PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
T2 CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
@ R2452
1 2 6 OF 19 Rev1p2
+3VS_WLAN_NGFF +3VS
0_0402_5%~D @
DII-DMN65D8LW-7~D RP42
A 1 8 A
1 3 WLAN_CLKREQ#_R 2 7
D

<26> WLAN_CLKREQ#
3 6
Q2409 4 5
G
2

+3VS 10K_8P4R_5%
1

R2453
100K_0402_5%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(6,7/19) CLK,SMB,SPI,LPC
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Tuesday, September 16, 2014 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

PCH_PLTRST#
1
CC33 ESD@

0.047U_0402_16V4Z +3VS
+3VALW_PCH 2
D @ CC11 D
1 2 ME_SUS_PWR_ACK Place CC33 1 2
RC27 10K_0402_5%
1 2 SUSACK# close to UC3.1 & UC3.2 0.1U_0402_10V7K
@ RC28 10K_0402_5%
1 2 SUS_STAT#/LPCPD#

5
@ RC29 10K_0402_5%

VCC
PCH_PLTRST# 1
IN1 4 PLT_RST#
+3V_DSW OUT PLT_RST# <21,26,30,47>
2

GND
IN2

1
UC3
1 2 AC_PRESENT MC74VHC1G08DFT2G_SC70-5 R159

3
RC32 10K_0402_5% 100K_0402_5%
1 2 PCH_BATLOW#
RC31 8.2K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#_R

2
1 2 PCIE_WAKE#_R RC33 @ 0_0402_5%
RC34 1K_0402_5%
1 2 PCH_SLP_WLAN# ME_SUS_PWR_ACK_R 1 2 SUSACK#
RC39 10K_0402_5% RC35 @ 0_0402_5%

DSWODVREN - On Die DSW VR Enable


Note: SUSACK# and SUSWARN# can be tied together if HEnable(DEFAULT)
+3VS
EC does not want to involve in the handshake mechanism * LDisable
for the Deep Sleep state entry and exit
1 2 CLKRUN# CAN be NC ,if not support Deep Sx +RTCVCC DSWODVREN - ON DIE DSW VR ENABLE
DPWROK: Tired toghter with RSMRST#
RC36 8.2K_0402_5% that do not support Deep Sx HIGH = ENABLED (DEFAULT)
HASWELL_MCP_E
UC1H
R2337 1 2 330K_0402_5%
R2338 1 @ 2 330K_0402_5% LOW = DISABLED
SYSTEM POWER MANAGEMENT
SUSACK# RC37 1 @ 2 0_0402_1% SUSACK#_R AK2 AW7 DSWODVREN
<30> SUSACK# SUSACK DSWVRMEN
SYS_RESET# AC3 AV5 PCH_DPWROK
<6> SYS_RESET# SYS_RESET DPWROK PCH_DPWROK <30>
SYS_PWROK SYS_PWROK 1 8 SYS_PWROK_R AG2 AJ5 PCIE_WAKE#_R 1 2 PCIE_WAKE#
<30> SYS_PWROK SYS_PWROK WAKE PCIE_WAKE# <21,30>
1 2 7 PCH_PWROK_R AY7 @
<30> PCH_PWROK PCH_PWROK
C CC31 @ESD@ 3 6 PM_APWROK_R AB5 RC97 C
4 5 PCH_PLTRST# AG7 APWROK V5 CLKRUN# 0_0402_5%
0.047U_0402_16V4Z PLTRST CLKRUN/GPIO32 AG4 SUS_STAT#/LPCPD#
2 RP50 SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK <26>
0_8P4R_5% AP5 SIO_SLP_S5#
SLP_S5/GPIO63 SIO_SLP_S5# <30>
Place CC31 RC41 1 @ 2 0_0402_1% PCH_RSMRST#_R AW6
<30> EC_RSMRST# RSMRST T103 PAD~D@
RC42 1 @ 2 0_0402_1% ME_SUS_PWR_ACK_R AV4
on BOT <30> ME_SUS_PWR_ACK SUSWARN/SUSPWRDNACK/GPIO30 T104 PAD~D @
PBTN_OUT# AL7 AJ6 SIO_SLP_S4#
<30> PBTN_OUT# PWRBTN SLP_S4 SIO_SLP_S4# <30>
<30,34,35,48> ACIN 1 2 AC_PRESENT AJ8 AT4 SIO_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 SIO_SLP_S3# <30>
DH1 RB751V-40_SOD323-2 PCH_BATLOW# AN4 AL5 @ T105
PCH_PWROK SIO_SLP_S0# AF3 BATLOW/GPIO72 SLP_A AP4
<30> SIO_SLP_S0# SLP_S0 SLP_SUS SLP_SUS# <30>
1 PCH_SLP_WLAN# AM5 AJ7 @ T107
CC34 @ESD@ SLP_WLAN/GPIO29 SLP_LAN

0.047U_0402_16V4Z PCH_BATLOW# Need pull high to VCCDSW3_3 @ T106


2
(If no deep Sx , connect to VCCSUS3_3)
8 OF 19 Rev1p2
Place CC34
close to RP50.2&RP50.3 @

+3VS

HASWELL_MCP_E CPU_DPB_CTRLDAT 1 8
UC1I
+3VS CPU_DPB_CTRLCLK 2 7
@ CPU_DPC_CTRLCLK 3 6
RC81 CPU_DPC_CTRLDAT 4 5
0_0402_1%
1 2 DGPU_PWROK EDP_BIA_PWM 2 1 EDP_BKLCTL B8 B9 CPU_DPB_CTRLCLK RP52
<6,31> EDP_BIA_PWM EDP_BKLCTL DDPB_CTRLCLK CPU_DPB_CTRLCLK <20>
RC73 10K_0402_5% PANEL_BKLEN A9 C9 CPU_DPB_CTRLDAT 2.2K_8P4R_5%
<30> PANEL_BKLEN EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA CPU_DPB_CTRLDAT <20>
1 2 PCH_TP_INT# ENVDD_PCH C6 D9 CPU_DPC_CTRLCLK
<31> ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK
RC74 10K_0402_5% D11 CPU_DPC_CTRLDAT
1 @ 2 EDP_BIA_PWM DDPC_CTRLDATA CPU_DPB_AUX# 1 8
B B
RC75 10K_0402_5% CPU_DPB_AUX 2 7
1 2 TS_RST# DGPU_PWROK U6 CPU_DPC_AUX 3 6
<30,42> DGPU_PWROK PIRQA/GPIO77
RC76 10K_0402_5% PXS_PWREN P4 C5 CPU_DPB_AUX# CPU_DPC_AUX# 4 5
<11,37,41,42,49> PXS_PWREN PIRQB/GPIO78 DISPLAY DDPB_AUXN
1 2 DGPU_HOLD_RST# DGPU_HOLD_RST# N4 B6 CPU_DPC_AUX#
<47> DGPU_HOLD_RST# PIRQC/GPIO79 DDPC_AUXN
RC77 10K_0402_5% FFS_INT1 N2 B5 CPU_DPB_AUX RP51
<32> FFS_INT1 PIRQD/GPIO80 DDPB_AUXP
1 2 FFS_INT1 T117 @ AD4 A6 CPU_DPC_AUX 100K_8P4R_5%
RC79 10K_0402_5% PME GPIO DDPC_AUXP
PCH_TP_INT# U7
1 2 ENVDD_PCH TS_RST# L1 GPIO55
<31> TS_RST# GPIO52
@ RC87 100K_0402_5% L3 C8 DPB_HPD
GPIO54 DDPB_HPD DPB_HPD <20>
2 1 CODEC_IRQ R5 A8 DPC_HPD
@ RC88 1K_0402_1% CODEC_IRQ L4 GPIO51 DDPC_HPD D6 CPU_EDP_HPD#
GPIO53 EDP_HPD

9 OF 19 Rev1p2 DPC_HPD 2 1

@ RC84
+3VS 100K_0402_5%

@
2

RC82
0_0402_1%
G

2 1 CPU_EDP_HPD# 2 1
EDP_CPU_HPD <31>
1 3 PCH_TP_INT#
<27> TP_INT#
RC89
D

100K_0402_5%
QC3
2N7002K_SOT23-3

1 2
RC367 0_0402_5%
A @ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(8,9/19) DDI,EDP,GPIO
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

D D

+3VS +3VS

1
+1.05VS_PCH 3D@ OPAL@
RC117 RC135
+1.05VS_PCH 10K_0402_5% 10K_0402_5%
Close to R2346
1

2
CC28

1
100P_0402_50V8J PCH_GPIO85 PCH_GPIO89
HASWELL_MCP_E
UC1J @ESD@
R2346 2

1
1K_0402_5%
RB751V-40_SOD323-2 2 1 DE5 ESD solution NON3D@ NONOPAL@

2
RC130 RC139
PCH_AUDIO_EN P1 D60 H_THERMTRIP# 10K_0402_5% 10K_0402_5%
3D_CAM_EN 1 2 PCH_GPIO57 AU2 BMBUSY/GPIO76 THERMTRIP V4 KB_RST#
<30,46> 3D_CAM_EN KB_RST# <30>

2
RC371 @ 0_0402_5% PCH_GPIO12 AM7 GPIO8 RCIN/GPIO82 T4 SERIRQ
@ T182 PAD~D LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ SERIRQ <30>
EC_LID_OUT# AD6 AW15 PCH_OPI_COMP 1 2
<30> EC_LID_OUT# GPIO15 MISC PCH_OPI_RCOMP
Y1 AF20
ODD_DA# T3 GPIO16 RSVD AB21 RC101
BT_ON# AD5 GPIO17 RSVD 49.9_0402_1% +3VS +3VS
<26> BT_ON# GPIO24
1 @ 2 GPIO27 AN5
<30> WAKE_PCH# RC38 0_0402_1% GPIO27
HOST_ALERT1_R_N AD7 +3VS
GPIO28

1
KB_DET# AN3
<27> KB_DET# GPIO26 R6 PCH_GPIO83 JET@ UMA@
GSPI0_CS/GPIO83 PAD~D T177 @
PCH_GPIO56 AG6 L6 PCH_GPIO84 RC112 RC100 SERIRQ 2 1
GPIO56 GSPI0_CLK/GPIO84 PAD~D T176 @
PCH_GPIO57 AP1 N6 PCH_GPIO85 10K_0402_5% 10K_0402_5% 10K_0402_5% RC102
+3VS SLATE_MODE_R AL4 GPIO57 GSPI0_MISO/GPIO85 L8 BBS_BIT LCD_CBL_DET# 2 1

2
WL_OFF# AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 DGPU_PRSNT# 10K_0402_5% RC106
<26> WL_OFF# GPIO59 GSPI1_CS/GPIO87
PCH_GPIO44 AK4 L5 PROJECT_ID CPPE# 2 1
2 1 DEVSLP0 PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89 100K_0402_5% RC108
C @ T174 PAD~D GPIO47 GSPI1_MISO/GPIO89 C

1
RC11 10K_0402_5% PCH_GPIO48 U4 K2 PCH_GPIO90 CPUSB# 2 1
@ T124 PAD~D GPIO48 GSPI_MOSI/GPIO90 PAD~D T179 @ TOPAZ@ DIS@
PCH_GPIO49 Y3 J1 CPPE# 100K_0402_5% RC111
2 1 SIO_EXT_SCI# @ T125 PAD~D TS_INT# P3 GPIO49 UART0_RXD/GPIO91 K3 CPUSB# RC113 RC99 FFS_INT2 2 1
<31> TS_INT# GPIO50 UART0_TXD/GPIO92
RC98 100K_0402_5% Y2 J2 PCH_GPIO93 10K_0402_5% 10K_0402_5% 100K_0402_5% RC115
HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 PAD~D T180 @
AT3 G1 PCH_GPIO94 RP53
PAD~D T181 @

2
2 1 PCH_GPIO56 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 I2C1_SDA 1 8
@ T126 PAD~D GPIO14 UART1_RXD/GPIO0
RC9 100K_0402_5% PCH_GPIO25 AM4 G2 FFS_INT2 I2C1_SCL 2 7
@ T127 PAD~D GPIO25 UART1_TXD/GPIO1 FFS_INT2 <32>
AG5 J3 LCD_CBL_DET# I2C0_SDA 3 6
PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 I2C0_SCL 4 5
GPIO46 UART1_CTS/GPIO3 F2 I2C0_SDA
+3V_DSW PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL 10K_0804_8P4R_5%
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA RC363 2 @ 1 0_0402_5%
<30> EC_SCI# GPIO10 I2C1_SDA/GPIO6 I2C1_SDA_PNL <31>
DEVSLP0 P2 F1 I2C1_SCL RC364 2 @ 1 0_0402_5%
<32> DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 I2C1_SCL_PNL <31>
C4 E3
2 1 GPIO27 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 RC365 2 @ 1 0_0402_1%
DEVSLP1/GPIO38 SDIO_CMD/GPIO65 I2C1_SDA_TP <27>
RC105 10K_0402_5% SIO_EXT_SCI# N5 D3 PCH_GPIO66 RC366 2 @ 1 0_0402_1%
DEVSLP2/GPIO39 SDIO_D0/GPIO66 I2C1_SCL_TP <27>
HDA_SPKR V2 E4 CAM_DETECT KB_RST# 10K_0402_5% 2 1 RC109
<22> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 CAM_DETECT <46>
C3
+3VALW_PCH SDIO_D2/GPIO68 E2 TS_INT# 10K_0402_5% 2 1 RC114
SDIO_D3/GPIO69
2 1 PCH_GPIO57 9/10. 10 OF 19 Rev1p2
RC372 10K_0402_5% Add PU for 3D CAMERA Function
@
2 1 KB_DET#
RC103 10K_0402_5%
2 1 PCH_GPIO44 +3VS
RC104 10K_0402_5%
2 1 SLATE_MODE_R
RC110 10K_0402_5% CAM_DETECT 1 2
2 1 PCH_AUDIO_EN RE74 10K_0402_5%
RC116 10K_0402_5% +3VS +3VS
1

@
@ RC119
RC118 10K_0402_5%
1K_0402_5% +3VALW_PCH +3VS
B B
2

1
PCH_GPIO66 BBS_BIT
@ @
1

RC120 RC121
1

@ 1K_0402_5% 1K_0402_5%
RC122

2
1K_0402_5% RC123
1K_0402_5% HOST_ALERT1_R_N HDA_SPKR
2

+3VS
2

RP54 GPIO66 GPIO86 GPIO15 GPIO81


8 1 ODD_DA#
7 2 BT_ON# TOP-BLOCK SWAP OVERRIDE BOOT BIOS STRAP BIT BBS TLS CONFIDENTIALITY NO REBOOT STRAP
6 3 WL_OFF#
5 4 PXS_PWREN HIGH depop RC288 (DEFAULT) HIGH LPC HIGH HIGH
PXS_PWREN <10,37,41,42,49>
8.2K_8P4R_5% LOW pop RC288 LOW(DEFAULT) SPI LOW(DEFAULT) LOW(DEFAULT)
GPIO15 NOT Used
+3VALW_PCH +3VALW_PCH
1

RC124 RC125
10K_0402_5% 10K_0402_5%
2

PCH_GPIO46 PCH_GPIO9

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(10/19) GPIO,LPIO,MISC
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Tuesday, September 16, 2014 Sheet 11 of 56
5 4 3 2 1
5 4 3 2 1

D D

HASWELL_MCP_E
UC1K

PEG_CRX_GTX_N0 F10 AN8 USB20_JUSB1_N0


<47> PEG_CRX_GTX_N0 PERN5_L0 USB2N0 USB20_JUSB1_N0 <24>
PEG_CRX_GTX_P0 E10 AM8 USB20_JUSB1_P0 USB Conn JUSB1
<47> PEG_CRX_GTX_P0 PERP5_L0 USB2P0 USB20_JUSB1_P0 <24>
PEG_CTX_GRX_N0 DIS@ CC18 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N0 C23 AR7 USB20_JUSB2_N1
<47> PEG_CTX_GRX_N0 PETN5_L0 USB2N1 USB20_JUSB2_N1 <24>
PEG_CTX_GRX_P0 DIS@ CC19 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P0 C22 AT7 USB20_JUSB2_P1 USB Conn JUSB2
<47> PEG_CTX_GRX_P0 PETP5_L0 USB2P1 USB20_JUSB2_P1 <24>
PEG_CRX_GTX_N1 F8 AR8 USB20_JUSB3_N2
<47> PEG_CRX_GTX_N1 PERN5_L1 USB2N2 USB20_JUSB3_N2 <25>
PEG_CRX_GTX_P1 E8 AP8 USB20_JUSB3_P2 USB Conn JUSB3
<47> PEG_CRX_GTX_P1 PERP5_L1 USB2P2 USB20_JUSB3_P2 <25>
PEG_CTX_GRX_N1 DIS@ CC20 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N1 B23 AR10
<47> PEG_CTX_GRX_N1 PETN5_L1 USB2N3
PEG_CTX_GRX_P1 DIS@ CC21 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P1 A23 AT10
<47> PEG_CTX_GRX_P1 PETP5_L1 USB2P3
PEG_CRX_GTX_N2 H10 AM15 USB20_MINI1_N4
<47> PEG_CRX_GTX_N2 PERN5_L2 USB2N4 USB20_MINI1_N4 <26>
PEG_CRX_GTX_P2 G10 AL15 USB20_MINI1_P4 Mini Card (WLAN)
<47> PEG_CRX_GTX_P2 PERP5_L2 USB2P4 USB20_MINI1_P4 <26>
PEG_CTX_GRX_N2 DIS@ CC22 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N2 B21 AM13 USB20_TOUCH_N5
<47> PEG_CTX_GRX_N2 PETN5_L2 USB2N5 USB20_TOUCH_N5 <31>
PEG_CTX_GRX_P2 DIS@ CC23 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P2 C21 AN13 USB20_TOUCH_P5 Touch screen panel
<47> PEG_CTX_GRX_P2 PETP5_L2 USB2P5 USB20_TOUCH_P5 <31>
PEG_CRX_GTX_N3 E6 AP11 USB20_CR_N6
<47> PEG_CRX_GTX_N3 PERN5_L3 USB2N6 USB20_CR_N6 <25>
PEG_CRX_GTX_P3 F6 AN11 USB20_CR_P6 Card Reader
<47> PEG_CRX_GTX_P3 PERP5_L3 USB2P6 USB20_CR_P6 <25>
PEG_CTX_GRX_N3 DIS@ CC24 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_N3 B22 AR13 USB20_CAM_N7
<47> PEG_CTX_GRX_N3 PETN5_L3 USB2N7 USB20_CAM_N7 <31>
PEG_CTX_GRX_P3 DIS@ CC25 1 2 0.1U_0402_10V7K PEG_CTX_GRX_C_P3 A21 AP13 USB20_CAM_P7 Camera
<47> PEG_CTX_GRX_P3 PETP5_L3 USB2P7 USB20_CAM_P7 <31>

C PCIE_PRX_LANTX_N3 G11 C
<21> PCIE_PRX_LANTX_N3 PERN3
PCIE_PRX_LANTX_P3 F11 G20 USB3RN1_JUSB1
<21> PCIE_PRX_LANTX_P3 PERP3 USB3RN1 USB3RN1_JUSB1 <24>
10/100 LAN H20 USB3RP1_JUSB1
USB3RP1 USB3RP1_JUSB1 <24>
PCIE_PTX_LANRX_N3 CC32 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_N3_C C29 USB Conn JUSB1
<21> PCIE_PTX_LANRX_N3 PETN3 PCIe USB
PCIE_PTX_LANRX_P3 CC40 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_P3_C B30 C33 USB3TN1_JUSB1
<21> PCIE_PTX_LANRX_P3 PETP3 USB3TN1 USB3TN1_JUSB1 <24>
B34 USB3TP1_JUSB1
USB3TP1 USB3TP1_JUSB1 <24>
PCIE_PRX_WLANTX_N4 F13
<26> PCIE_PRX_WLANTX_N4 PERN4
PCIE_PRX_WLANTX_P4 G13 E18 USB3RN2_JUSB2
<26> PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 USB3RN2_JUSB2 <24>
NGFF WLAN F18 USB3RP2_JUSB2
USB3RP2 USB3RP2_JUSB2 <24>
PCIE_PTX_WLANRX_N4 CC36 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C B29 USB Conn JUSB2
<26> PCIE_PTX_WLANRX_N4 PETN4
PCIE_PTX_WLANRX_P4 CC41 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C A29 B33 USB3TN2_JUSB2
<26> PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 USB3TN2_JUSB2 <24>
A33 USB3TP2_JUSB2
USB3TP2 USB3TP2_JUSB2 <24>
G17
F17 PERN1/USB3RN3
PERP1/USB3RP3
C30
C31 PETN1/USB3TN3 AJ10 USBRBIAS
PETP1/USB3TP3 USBRBIAS AJ11
USB3RN3_3D_CAM F15 USBRBIAS AN10 PAD~D T118 @
<46> USB3RN3_3D_CAM PERN2/USB3RN4 RSVD

1
USB3RP3_3D_CAM G15 AM10 PAD~D T119 @
<46> USB3RP3_3D_CAM PERP2/USB3RP4 RSVD RC90
USB3TN3_3D_CAM B31 22.6_0402_1%~D
<46> USB3TN3_3D_CAM PETN2/USB3TN4
USB3TP3_3D_CAM A31
<46> USB3TP3_3D_CAM PETP2/USB3TP4 AL3 USB_OC0#
USB_OC0# <24>

2
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 USB_OC1# <25>
AH2 USB_OC2#
RC91 @ T120PAD~D E15 OC2/GPIO42 AV3 USB_OC3#
3.01K_0402_1% @ T121PAD~D E13 RSVD OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 RSVD
+1.05VS_AUSB3PLL PCIE_RCOMP
B27 CAD NOTE:
PCIE_IREF
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
11 OF 19 Rev1p2 Recommended minimum spacing to other signal traces is 15 mils.

B B

+3VALW_PCH

USB_OC0# 1 8
USB_OC1# 2 7
USB_OC2# 3 6
USB_OC3# 4 5

RP55
10K_8P4R_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(11/19) PCIE,USB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 12 of 56
5 4 3 2 1
5 4 3 2 1

VCCST_PG_EC
+CPU_CORE +1.35V
1
C79 ESD@ C40
1 2
220P_0402_50V8J +CPU_CORE
2 22U_0603_6.3V6M UC1L HASWELL_MCP_E
D D
+1.05VS_PCH @ESD@
Place C79 L59 C36
+1.35V J58 RSVD VCC C40
between R286 and UC1 ESD solution RSVD VCC

1
C44
R286 AH26 VCC C48
AJ31 VDDQ VCC C52
10K_0402_5% VDDQ VCC
AJ33 C56
AJ37 VDDQ VCC E23

2
AN33 VDDQ VCC E25
VCCST_PG_EC AP43 VDDQ VCC E27
<30> VCCST_PG_EC VDDQ VCC
AR48 E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
Define EC OD pin, need double confirm. +VCCIO_OUT AY44 VDDQ VCC E35
+CPU_CORE AY50 VDDQ VCC E37
VDDQ VCC E39
VCC

2
F59 E41
N58 VCC VCC E43
AC58 RSVD VCC E45
R245 @ RSVD VCC E47
0_0603_5% VCCSENSE E63 VCC E49

1
T38 @ AB23 VCC_SENSE VCC E51
VR_ON +VCCIO_OUT_R A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
1 +VCCIOA_OUT VCCIOA_OUT VCC
C80 ESD@ AD23 E57
AA23 RSVD 12 OF 19 VCC F24
0.1U_0402_10V7K AE59 RSVD VCC F28
SVID ALERT +1.05VS_PCH
2 RSVD VCC
VCC
F32
H_CPU_SVIDALRT# L62 F36
0_0402_1% 1 @ 2 R248 H_CPU_SVIDCLK N63 VIDALERT VCC F40
Place C80 <40> VR_SVID_CLK
H_CPU_SVIDDATA L63 VIDSCLK VCC F44
close to R250.1 VIDSOUT VCC
1

VCCST_PG_EC B59 HSW ULT POWER F48


Place the PU VCCST_PWRGD VCC
R252 resistors close to CPU 0_0402_1% 1 @ 2 R250 VR12.5_VR_ON_R F60 F52
<30,40> VR_ON VR_EN VCC
75_0402_5% <40> H_VR_READY 0_0402_1% 1 @ 2 R251 VR_READY_R C59 F56
VR_READY VCC G23
R254 D63 VCC G25
2

43_0402_1% CPU_PWR_DEBUG# H59 VSS VCC G27


C PWR_DEBUG VCC C
2 1 H_CPU_SVIDALRT# P62 G29
<40> VR_SVID_ALRT# VSS VCC
T39 @ P60 G31
T40 @ P61 RSVD_TP VCC G33
T41 @ N59 RSVD_TP VCC G35
T42 @ N61 RSVD_TP VCC G37
H_CPU_SVIDCLK T43 @ T59 RSVD_TP VCC G39
RF T44
T45
@
@
AD60
AD59
RSVD
RSVD
VCC
VCC
G41
G43
1 RSVD VCC
+1.05VS_PCH RF@ T46 @ AA59 G45
SVID DATA C5212 T47 @ AE60 RSVD
RSVD
VCC
VCC
G47
Place the PU 68P_0402_50V8J T48 @ AC59 G49
2 T49 @ AG58 RSVD VCC G51
SVID_DAT need to pull-up double side resistors close to CPU RSVD VCC
1

( PWR_VR & CPU ) +1.05VS_PCH T50 @ U59 G53


R256 T51 @ V59 RSVD VCC G55
130_0402_1% RSVD VCC G57
@ AC22 VCC H23
R257 +CPU_CORE AE22 VCCST VCC J23
2

0_0402_1% AE23 VCCST VCC K23


2 1 H_CPU_SVIDDATA VCCST VCC K57
<40> VR_SVID_DAT VCC
AB57 L22
AD57 VCC VCC M23
AG57 VCC VCC M57
+1.05VS_PCH C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
VCC VCC
2 @ Rev1p2
R253 R253
150_0402_1% @
INTEL Check list , XDP use only
+1.35V
1

CPU_PWR_DEBUG#
+CPU_CORE VDDQ DECOUPLING
2

@
B R255 B
1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
10K_0402_5%

C35

C36

C37

C38

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
R1
1

C39

C41

C72

C42

C45

C74
100_0402_1%
2

2 2 2 2 2 2 2 2 2 2

VCCSENSE
CAD Note: PU resistor on HW side
<40> VCCSENSE

VSSSENSE CAD Note: PD resistor on HW side


<15,40> VSSSENSE +1.35V : 470UF/2V/7343 *2 (PWR)
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
1

R2
100_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(12/19) Power
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 13 of 56
5 4 3 2 1
5 4 3 2 1

+1.05VS_PCH
+1.05VS_PCH +CPU_CORE
C46

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M
1 2

D 1 1 22U_0603_6.3V6M D
@ESD@

CD63
@ESD@

CD65
@ESD@
+ + C47
1 2
2 2 22U_0603_6.3V6M
Close to N8 @ESD@
+1.05VS_PCH C57 @1 2 1U_0402_6.3V6K
ESD solution
+RTCVCC
+1.05VS_PCH +1.05VS_AUSB3PLL

L11 2 C58 1 2 1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0402_6.3V6K
C59 1 2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% 1 1 1
UC1M HASWELL_MCP_E

C54

C55

C56
+1.05VS_ASATA3PLL K9
+1.05VS_PCH VCCHSIO 2 2 2
L10 0_0603_1% 2 @ 1 R264 +3VALW_PCH
M9 VCCHSIO
L21 2 C63 1 2 1U_0402_6.3V6K N8 VCCHSIO mPHY AH11 C51 1 2 1U_0402_6.3V6K
+1.05VS_PCH VCC1_05 RTC VCCSUS3_3
C65 1 2 100U_1206_6.3V6M P9 AG10 +RTCVCC
2.2UH_LQM2MPN2R2NG0L_30% B18 VCC1_05 VCCRTC AE7
+1.05VS_AUSB3PLL VCCUSB3PLL DCPRTC
+1.05VS_ASATA3PLL B11 +VCCRTCEXT C52 1 2 0.1U_0402_10V7K
R267 +1.05VS_APLLOPI VCCSATA3PLL
+3VALW_PCH
0_0805_1%
1 @ 2 Y20 SPI Y8 @ C68 1 2 0.1U_0402_10V7K
C69 1 2 1U_0402_6.3V6K AA21 RSVD OPI VCCSPI
+1.05VS_APLLOPI VCCAPLL
L31 @ 2 C70 @1 2 100U_1206_6.3V6M W21
2.2UH_LQM2MPN2R2NG0L_30% VCCAPLL AG14 +1.05VS_PCH +3VS
VCCASW +1.05VS_PCH
AG13 C44
+1.05VS_AXCK_DCB VCCASW 1 2
USB3
+1.05VS_PCH
+1.05VS_PCH 0_0402_5% 2 @ 1 RC142 J13
DCPSUS3 J11 C60 1 2 10U_0603_6.3V6M 22U_0603_6.3V6M
C83 1 2 1U_0402_6.3V6K C92 1 @2 1U_0402_6.3V6K VCC1_05 H11 C61 1 2 1U_0402_6.3V6K @ESD@
L4 1 2 C84 1 2 100U_1206_6.3V6M AH14 AXALIA/HDA VCC1_05 H15 C62 1 2 1U_0402_6.3V6K
+VCCHDA VCCHDA VCC1_05
2.2UH_LQM2MPN2R2NG0L_30% AE8 C64
C VCC1_05 AF22 +PCH_VCCDSW 1U_0402_6.3V6K ESD solution C

0_0402_5% 2 @ 1 RC143 AH13 VRM/USB2/AZALIA VCC1_05 AG19 1 2


+1.05VS_AXCK_LCPLL +1.05VS_PCH DCPSUS2 CORE DCPSUSBYP AG20
C91 1 @2 1U_0402_6.3V6K DCPSUSBYP AE9
VCCASW +1.05VS_PCH
C85 1 2 1U_0402_6.3V6K AF9 @ C66 1 2 22U_0603_6.3V6M
L5 1 2 C86 1 2 100U_1206_6.3V6M AC9 VCCASW AG8 C67 1 2 1U_0402_6.3V6K
+3VALW_PCH VCCSUS3_3 VCCASW +1.05VS_PCH +1.35V
2.2UH_LQM2MPN2R2NG0L_30% AA9 AD10
AH10 VCCSUS3_3 DCPSUS1 AD8 RC137 1 @ 2 0_0402_5% +1.05VS_PCH C43
+3V_DSW VCCDSW3_3 GPIO/LCC DCPSUS1
+3VS V8 C93 1 2 1U_0402_6.3V6K 1 2
W9 VCC3_3 @
VCC3_3 J15 22U_0603_6.3V6M
THERMAL SENSOR VCCTS1_5 +1.5VS
K14 +3VS ESD@
VCC3_3 K16 C71 1 2 0.1U_0402_10V7K
+1.5VS +3VS +3VALW_PCH +VCCHDA VCC3_3
ESD solution
RC127 1 2 0_0402_5% +1.05VS_AXCK_DCB J18
K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
RC128 1 @ 2 0_0402_5% +1.05VS_AXCK_LCPLL A20 T9 C73 1 2 1U_0402_6.3V6K
J17 VCCACLKPLL VCCSDIO
+1.05VS_PCH VCCCLK +PCH_VCCDSW +3V_DSW
RC129 1 @ 2 0_0402_5% +1.05VS_PCH R21
T21 VCCCLK LPT LP POWER
VCCCLK SUS OSCILLATOR C5215
K18 AB8 RC136 1 @ 2 0_0402_5% +1.05VS_PCH Reserve for inrush
C77 1 2 0.1U_0402_10V7K M20 RSVD DCPSUS4 C90 @1 2 1U_0402_6.3V6K 1 2
+VCCHDA RSVD current issue
V21 CC37 @1 2 47U_0603_2.5V7
AE20 RSVD AC20 CC38 @1 2 47U_0603_2.5V7
Reserve for HDA issue, C77 close to AH14 +3VALW_PCH
AE21 VCCSUS3_3 RSVD AG16 0.47U_0402_6.3V6K
VCCSUS3_3 USB2 VCC1_05 +1.05VS_PCH @
AG17
VCC1_05 C76 1 2 1U_0402_6.3V6K

13 OF 19 Rev1p2

C50 1 2 1U_0402_6.3V6K @
+1.05VS_PCH C53 1 2 1U_0402_6.3V6K Close to K9,M9

B B
+3V_DSW C81 1 2 1U_0402_6.3V6K Close to AH10

+3VALW_PCH C78 1 2 22U_0603_6.3V6M Close to AC9/AA9/AE20/AE21

+3VS C82 1 2 22U_0603_6.3V6M Close to V8

+1.05VS_PCH C87 1 2 1U_0402_6.3V6K Close to J17

+1.05VS_PCH C88 1 2 1U_0402_6.3V6K Close to R21

+3VALW_PCH C75 2 1 0.1U_0402_10V7K Close to AH14

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(13/19) Power
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Friday, October 17, 2014 Sheet 14 of 56
5 4 3 2 1
5 4 3 2 1

D D

HASWELL_MCP_E HASWELL_MCP_E
UC1N UC1O UC1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C VSS VSS VSS VSS VSS VSS C
AB7 AL13 AR33 AY16 D54 N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE <13,40>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
VSS VSS VSS VSS

1
AH30 AN32 AU53 C18
AH32 VSS VSS AN35 AU55 VSS VSS C20 @
VSS VSS VSS VSS @
AH34 AN36 AU57 C25 RC163
AH36 VSS VSS AN39 AU59 VSS VSS C27 100_0402_1%
AH38 VSS VSS AN40 AV14 VSS VSS C38

2
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B VSS VSS VSS VSS B
AH51 AN48 AV33 D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23 CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS

@
14 OF 19 Rev1p2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(14,15,16/19) VSS
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 15 of 56
5 4 3 2 1
5 4 3 2 1

D D

HASWELL_MCP_E HASWELL_MCP_E
UC1Q UC1R

@
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 N23 RSVD_N23 PAD~D T129
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 RSVD @
DC_TEST_AY3_AW3 AY3 A4 DC_TEST_A4 PAD~D T168 @ R23 RSVD_R23 PAD~D T130
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 RSVD @
@ T166PAD~D DC_TEST_AY60 AY60 @ T23 RSVD_T23 PAD~D T131
DAISY_CHAIN_NCTF_AY60 T128 PAD~D RSVD_AT2 AT2 RSVD @
DC_TEST_AY61_AW61 AY61 A60 DC_TEST_A60 PAD~D T169 @ @ RSVD U10 RSVD_U10 PAD~D T133
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 T132 PAD~D RSVD_AU44 AU44 RSVD
DC_TEST_AY62_AW62 AY62 A61 DC_TEST_A61_B61 @ RSVD
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 T134 PAD~D RSVD_AV44 AV44
@ T167PAD~D TP_DC_TEST_B2 B2 A62 DC_TEST_A62 PAD~D T170 @ @ RSVD
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 T135 PAD~D RSVD_D15 D15 @
DC_TEST_A3_B3 B3 AV1 DC_TEST_AV1 PAD~D T171 @ RSVD AL1 RSVD_AL1 PAD~D T136
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 RSVD @
DC_TEST_A61_B61 B61 AW1 DC_TEST_AW1 PAD~D T172 @ AM11 RSVD_AM11 PAD~D T137
DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 RSVD @
B62 AW2 DC_TEST_AY2_AW2 @ AP7 RSVD_AP7 PAD~D T139
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 T138 PAD~D RSVD_F22 F22 RSVD @
DC_TEST_B62_B63 B63 AW3 DC_TEST_AY3_AW3 @ RSVD AU10 RSVD_AU10 PAD~D T141
DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 T140 PAD~D RSVD_H22 H22 RSVD @
C1 AW61 DC_TEST_AY61_AW61 @ RSVD AU15 RSVD_AU15 PAD~D T142
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 T143 PAD~D RSVD_J21 J21 RSVD @
DC_TEST_C1_C2 C2 AW62 DC_TEST_AY62_AW62 RSVD AW14 RSVD_AW14 PAD~D T144
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 RSVD @
AW63 DC_TEST_AW63 PAD~D T173 @ AY14 RSVD_AY14 PAD~D T145
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2 RSVD

18 OF 19 Rev1p2
@

C C

UC1S HASWELL_MCP_E

AC60 AV63
CFG STRAPS for CPU
PAD~D T146 @
AC62 CFG0 RSVD_TP AU63 PAD~D T147 @
AC63 CFG1 RSVD_TP CFG4
AA63 CFG2
CFG4 AA60 CFG3 C63 PAD~D T148 @
CFG4 RSVD_TP

1
Y62 C62 PAD~D T149 @
Y61 CFG5 RSVD_TP B43 PAD~D T150 @ RC138
Y60 CFG6 RSVD 1K_0402_1%
V62 CFG7 A51 PAD~D T151 @
V61 CFG8 RSVD_TP B51 PAD~D T152 @

2
V60 CFG9 RSVD_TP
U60 CFG10 L60 PAD~D T153 @
T63 CFG11 RESERVED RSVD_TP
T62 CFG12 N60 PAD~D T154 @
T61 CFG13 RSVD
B CFG14 B
T60 W23 PAD~D T155 @
CFG15 RSVD Y22 PAD~D T156 @ Display Port Presence Strap
AA62 RSVD AY15 PROC_OPI_RCOMP
U63 CFG16 PROC_OPI_RCOMP
AA61 CFG18 AV62 PAD~D T157 @ 1: Disabled; No Physical Display Port
CFG17 RSVD
U62
CFG19 RSVD
D58 PAD~D T158 @
CFG4 attached to Embedded Display Port
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21 0: Enabled; An external Display Port device is
VSS
@ T159PAD~D A5
RSVD P20 PAD~D T160 @
connected to the Embedded Display Port
@ T161PAD~D E1 RSVD R20 PAD~D T162 @
@ T163PAD~D D1 RSVD RSVD
@ T164PAD~D J20 RSVD
@ T165PAD~D H18 RSVD
TDI_IREF B12 RSVD
TD_IREF
19 OF 19 Rev1p2

2 1 CFG_RCOMP
RC132 49.9_0402_1%
1 2 TDI_IREF PROC_OPI_RCOMP 1 2
RC133 8.2K_0402_1% 49.9_0402_1% RC134

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP(17,18,19/19) CFG,RSVD
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 16 of 56
5 4 3 2 1
5 4 3 2 1

+DIMM1_VREF_DQ
H=4mm
+1.35V +1.35V

1 2 1
JDIMM1
2
2-3A to 1 DIMMs/channel
+SM_VREF_DQ0_DIMM1 VREF_DQ VSS
3 4 DDR_A_D4
VSS DQ4

2.2U_0402_6.3V6M

0.1U_0402_10V7K
D @ DDR_A_D0 5 6 DDR_A_D5 D
RD1 DDR_A_D1 7 DQ0 DQ5 8 +1.35V
0_0402_1% 9 DQ1 VSS 10 DDR_A_DQS#0
Populate RD1, De-Populate RD7 for Intel DDR3 1 1 VSS DQS0#

CD1

CD2
11 12 DDR_A_DQS0
VREFDQ multiple methods M1 13 DM0 DQS0 14
VSS VSS

1
Populate RD7, De-Populate RD1 for Intel DDR3 2 2
DDR_A_D2 15
DQ2 DQ6
16 DDR_A_D6
VREFDQ multiple methods M3 DDR_A_D3 17 18 DDR_A_D7 RD3
19 DQ3 DQ7 20 470_0402_5%
DDR_A_D8 21 VSS VSS 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13

2
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28 1 2
DQS1# DM1 <18> DDR3_DRAMRST# DDR3_DRAMRST#_CPU <6>
DDR_A_DQS1 29 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 @
DDR_A_D10 33 VSS VSS 34 DDR_A_D14 @ESD@ RD5
<7> DDR_A_DQS#[0..7] DQ10 DQ14 1
DDR_A_D11 35 36 DDR_A_D15 CD3 0_0402_1%
37 DQ11 DQ15 38 0.1U_0402_10V7K
<7> DDR_A_D[0..63] All VREF traces should VSS VSS
have 10 mil trace width DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2
<7> DDR_A_DQS[0..7] DQ17 DQ21
43 44
DDR_A_DQS#2 45 VSS VSS 46
<7> DDR_A_MA[0..15] DQS2# DM2
DDR_A_DQS2 47 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
Layout Note: Note: DDR_A_D19 53 DQ18 DQ23 54 CAD NOTE
DQ19 VSS
Place near JDIMM1 Check voltage tolerance of DDR_A_D24
55
57 VSS DQ28
56
58
DDR_A_D28
DDR_A_D29
PLACE THE CAP NEAR TO
DDR_A_D25 59 DQ24 DQ29 60 DIMM RESET PIN
VREF_DQ at the DIMM socket 61 DQ25
VSS
VSS
DQS3#
62 DDR_A_DQS#3
63 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS VSS 68 DDR_A_D30
+1.35V DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
C 1 1 1 1 1 1 1 1 75 76 C
77 VDD VDD 78 DDR_A_MA15
NC A15
CD4

CD5

CD6

CD7

CD8

CD9

CD10

CD11

DDR_A_BS2 79 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
2 2 2 2 2 2 2 2 DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88 M_ODT
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
A8 A6 1
DDR_A_MA5 91 92 DDR_A_MA4 CD64 ESD@
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2 0.1U_0402_10V7K
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0 2
99 A1 A0 100
+1.35V M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1 Place CC31
<7>
<7>
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR#0 103
105
CK0
CK0#
CK1
CK1#
104
106
M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#1
<7>
<7> DDR3L SODIMM ODT GENERATION between QD2 and R2349
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7> +5VALW +1.35V
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D3_2.5VY_R6M

DDR_A_BS0 109 110 DDR_A_RAS#


<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112 QD2
DDR_A_WE# 113 VDD VDD 114 DDR_CS0_DIMMA# BSS138-G_SOT23-3
1 <7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
1 1@ 1 1 1@ 1 1 1 DDR_A_CAS# 115 116 M_ODT0
<7> DDR_A_CAS# CAS# ODT0

1
CD16

CD17

CD12

CD18

CD19

CD20

CD13

CD14

CD15

+ 117 118 1 3 M_ODT 1 2 M_ODT0

S
DDR_A_MA13 119 VDD VDD 120 M_ODT1 R2347 R2348 66.5_0402_1%
DDR_CS1_DIMMA# 121 A13 ODT1 122 +SM_VREF_CA_DIMM 220K_0402_5%~D 1 2 M_ODT1
2 2 2 2 2 2 2 2 2 <7> DDR_CS1_DIMMA# S1# NC
123 124 R2349 66.5_0402_1%

G
2
125 VDD VDD 126 1 2 1 2
M_ODT2 <18>

2
TEST VREF_CA

2.2U_0402_6.3V6M

0.1U_0402_10V7K
127 128 R2350 66.5_0402_1%
DDR_A_D32 129 VSS VSS 130 DDR_A_D36 @ 1 2
DQ32 DQ36 M_ODT3 <18>
DDR_A_D33 131 132 DDR_A_D37 1 1 RD4 R2352 66.5_0402_1%
DQ33 DQ37

2
CD21

CD22
133 134 0_0402_1% @
DDR_A_DQS#4 135 VSS VSS 136 R2351
DDR_A_DQS4 137 DQS4# DM4 138 2M_0402_5% 0.675V_DDR_VTT_ON
DQS4 VSS 2 2 0.675V_DDR_VTT_ON <39>
139 140 DDR_A_D38
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39

1
DDR_A_D35 143 DQ34 DQ39 144
Layout Note: DQ35 VSS
145 146 DDR_A_D44
Place near JDIMM1.203,204 DDR_A_D40 147 VSS DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
B DQ41 VSS B
151 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46 +1.35V
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 @
161 DQ43 DQ47 162 CD23
+0.675VS DDR_A_D48 163 VSS VSS 164 DDR_A_D52 U2303 0.1U_0402_10V7K
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 1 5 1 2
167 DQ49 DQ53 168 NC VCC
DDR_A_DQS#6 169 VSS VSS 170 2
DQS6# DM6 <6> DDR_PG_CTRL A
DDR_A_DQS6 171 172 4 0.675V_DDR_VTT_ON
DQS6 VSS Y
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

173 174 DDR_A_D54 3


DDR_A_D50 175 VSS DQ54 176 DDR_A_D55 GND
1 1 1 1 1 1 DQ50 DQ55
CD24

CD25

CD26

CD27

CD28

CD29

DDR_A_D51 177 178 74AUP1G07GW_TSSOP5


179 DQ51 VSS 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
2 2 2 2 2 2 DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
RD61 2 10K_0402_5% 197 VSS VSS 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA DDR_XDP_WLAN_TP_SMBDAT <9,18,32>
1 2 201 202
SA1 SCL DDR_XDP_WLAN_TP_SMBCLK <9,18,32>
2.2U_0402_6.3V6M

RD7 10K_0402_5% 1 1 203 204 +0.675VS


VTT VTT
0.1U_0402_10V7K

@ +0.675VS
CD30

CD31

205 206
207 GND1 GND2 208
2 2 BOSS1 BOSS2

BELLW_80001-1021
CONN@

A A

+3VS +1.35V
CD62
1 2

22U_0603_6.3V6M
ESD@

ESD solution
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 17 of 56
5 4 3 2 1
5 4 3 2 1

+DIMM2_VREF_DQ +1.35V
H=4mm +1.35V

JDIMM2
2-3A to 1 DIMMs/channel
+SM_VREF_DQ1_DIMM2 1 2 1 2
3 VREF_DQ VSS1 4 DDR_B_D22
VSS2 DQ4

2.2U_0402_6.3V6M

0.1U_0402_10V7K
@ DDR_B_D23 5 6 DDR_B_D16
RD8 DDR_B_D17 7 DQ0 DQ5 8
0_0402_1% 9 DQ1 VSS3 10 DDR_B_DQS#2
1 1 VSS4 DQS#0

CD32

CD33
D 11 12 DDR_B_DQS2 D
13 DM0 DQS0 14
Populate RD4, De-Populate RD8 for Intel DDR3 DDR_B_D21 15 VSS5 VSS6 16 DDR_B_D19
VREFDQ multiple methods M1 2 2 DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
DQ3 DQ7
Populate RD8, De-Populate RD4 for Intel DDR3 19
VSS7 VSS8
20
VREFDQ multiple methods M3 DDR_B_D3 21 22 DDR_B_D4
DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS9 VSS10 28
DDR_B_DQS0 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <17>
31 32
<7> DDR_B_DQS#[0..7] VSS11 VSS12
DDR_B_D0 33 34 DDR_B_D6 1
DDR_B_D1 35 DQ10 DQ14 36 DDR_B_D7
<7> DDR_B_D[0..63] All VREF traces should DQ11 DQ15
have 10 mil trace width 37 38 @ESD@
DDR_B_D12 39 VSS13 VSS14 40 DDR_B_D13 CD34
<7> DDR_B_DQS[0..7] DQ16 DQ20 2
DDR_B_D8 41 42 DDR_B_D9 0.1U_0402_10V7K
43 DQ17 DQ21 44
<7> DDR_B_MA[0..15] VSS15 VSS16
DDR_B_DQS#1 45 46
DDR_B_DQS1 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D11
Layout Note: Note: DDR_B_D14 51 VSS18
DQ18
DQ22
DQ23
52 DDR_B_D10
CAD NOTE
DDR_B_D15 53 54
Place near JDIMM2 Check voltage tolerance of 55 DQ19
VSS20
VSS19
DQ28
56 DDR_B_D30 PLACE THE CAP NEAR TO
DDR_B_D31 57 58 DDR_B_D26
VREF_DQ at the DIMM socket DDR_B_D25 59 DQ24
DQ25
DQ29
VSS21
60 DIMM RESET PIN
61 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS23 VSS24 68 DDR_B_D29
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
+1.35V 71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
1 1 1 1 1 1 1 1 75 76
77 VDD1 VDD2 78 DDR_B_MA15
NC1 A15
CD35

CD36

CD37

CD38

CD39

CD40

CD41

CD42
C DDR_B_BS2 79 80 DDR_B_MA14 C
<7> DDR_B_BS2 BA2 A14
81 82
2 2 2 2 2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
+1.35V 99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<7> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <7>
105 106
VDD11 VDD12
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D3_2.5VY_R6M

DDR_B_MA10 107 108 DDR_B_BS1


A10/AP BA1 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
1 111 112
@ @ DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
1 1 1 1 1 1 1 1 <7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
CD43

CD44

CD45

CD46

CD47

CD48

CD49

CD50

CD51

+ DDR_B_CAS# 115 116 M_ODT2


<7> DDR_B_CAS# CAS# ODT0 M_ODT2 <17>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
2 2 2 2 2 2 2 2 2 A13 ODT1 M_ODT3 <17> +SM_VREF_CA_DIMM
DDR_CS3_DIMMB# 121 122
<7> DDR_CS3_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126 1 2
127 NCTEST VREF_CA 128
VSS27 VSS28

2.2U_0402_6.3V6M

0.1U_0402_10V7K
DDR_B_D32 129 130 DDR_B_D33 @
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34 RD10
133 DQ33 DQ37 134 0_0402_1%
VSS29 VSS30 1 1

CD53
DDR_B_DQS#4 135 136
DQS#4 DM4

CD52
DDR_B_DQS4 137 138
139 DQS4 VSS31 140 DDR_B_D39
DDR_B_D36 141 VSS32 DQ38 142 DDR_B_D37 2 2
DDR_B_D38 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
Layout Note: VSS34 DQ44
DDR_B_D40 147 148 DDR_B_D41
Place near JDIMM2.203,204 DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
B DM5 DQS5 B
155 156
DDR_B_D43 157 VSS37 VSS38 158 DDR_B_D47
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
DDR_B_D52 163 VSS39 VSS40 164 DDR_B_D51
+0.675VS DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D55
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D48
VSS44 DQ54
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_D50 175 176 DDR_B_D54


DDR_B_D53 177 DQ50 DQ55 178
1 1 1 1 1 1 DQ51 VSS45
CD54

CD55

CD56

CD57

CD58

CD59

179 180 DDR_B_D56


DDR_B_D63 181 VSS46 DQ60 182 DDR_B_D57
DDR_B_D62 183 DQ56 DQ61 184
2 2 2 2 2 2 185 DQ57 VSS47 186 DDR_B_DQS#7
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D60
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
195 DQ59 DQ63 196
+3VS 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA DDR_XDP_WLAN_TP_SMBDAT <9,17,32>
2 1 201 202
SA1 SCL DDR_XDP_WLAN_TP_SMBCLK <9,17,32>
RD12 10K_0402_5% +0.675VS 203 204 +0.675VS
VTT1 VTT2
1
10K_0402_5%
RD13

0.1U_0402_10V7K

205 206
G1 G2
2.2U_0402_6.3V6M

1 1
CD61

@ BELLW_80011-1021
CD60

CONN@
2

2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 18 of 56
5 4 3 2 1
5 4 3 2 1

D D

UG1 GCLK@ UG1 @

SLG3NB3375VTR TQFN 16P CRYSTAL SLG3NB3374VTR TQFN 16P CRYSTAL

SLG3NB3374V is for DIS by output 24M*1, 25M*1, 27M*1, 32K*1


SLG3NB3375V is for UMA by output 24M*1, 25M*1, , 32K*1
+RTCVCC +RTCBATT

+RTCVCC

1
RG4 RG1

1
330_0402_5% 330_0402_5%
+1.05VS_PCH +LAN_VDD33 +3VLP +3VALW @ GCLK@ RG2 @
0_0402_5%

2
1 GCLK@ 1 GCLK@ 1 GCLK@ 1 GCLK@

2.2U_0603_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CG2 CG3 CG4 CG10 1
C CG5 1 C
2 2 2 2 22U_0805_6.3V6M

CG6
GCLK@
GCLK@ 2
UG1 2

GCLK_VRTC 10 14 RTC_VOUT
VBAT VDD_RTC_OUT
Place close +3VLP 15 CPU_RTC 32.768k(P.8)
+V3.3A
to UG1.8 Place RG3 close to YC1
+3VALW 2 0_0402_5%
VDD 9 PCH_RTCX1_R RG3 1 2
32kHz PCH_RTCX1 <8>
GCLK@

11 12
VDDIO_27M 27MHz
+LAN_VDD33 8 6 LAN_X1_R RG5 1 2 33_0402_5% XTLI_R 1 2
VDDIO_25M_A 25MHz_A XTLI <21>
GCLK@ RG8 GCLK@ 0_0402_5%
+1.05VS_PCH 3 5 PCH_X1_R RG6 1 2 22_0402_5%
VDDIO_25M_B 25MHz_B XTAL24_IN <9>
GCLK@ 1 LAN 25M(P.21)
CLK_X1 1 GCLK@ Place RG8 close to YL2
CLK_X2 16 XTAL_IN CG7
XTAL_OUT
CPU_CLK 24M(P.9)

GND1
GND2
GND3

GND4
CLK_X1 Place RG6 close to YC2 5P_0402_50V8C
CG8 GCLK@ 2
2 1
RG3,RG8, RG6 0ohm_0402

4
7
13

17
15P_0402_50V8J YG1 GCLK@ SLG3NB274VTR_TQFN16_2X3 for isolated CLK tail
1 2
OSC GND @
3 4
OSC GND
CG9 GCLK@ 25MHZ_10PF_7V25000014
2 1

12P_0402_50V8J CLK_X2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Green CLK
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Wednesday, September 10, 2014 Sheet 19 of 56
5 4 3 2 1
5 4 3 2 1

D Place close to JHDMI D

+VDISPLAY_VCC

DLW21HN900HQ2L_4P
W=40mils
TMDS_TXCN 1 2 TMDS_L_TXCN +5VS 2 1
1 2

10U_0603_6.3V6M
0.1U_0402_16V7K
1 1

CX21
CX12 2 1 0.1U_0402_10V7K TMDS_TXCN FX1
<6> DDI1_LANE_N3
CX13 2 1 0.1U_0402_10V7K TMDS_TXCP TMDS_TXCP 4 3 TMDS_L_TXCP 1.5A_6V_1206L150PR~D CX22
<6> DDI1_LANE_P3 4 3
CX14 2 1 0.1U_0402_10V7K TMDS_TX0N LX2 EMI@ +3VS 2 2
<6> DDI1_LANE_N2
CX15 2 1 0.1U_0402_10V7K TMDS_TX0P
<6> DDI1_LANE_P2
CX16 2 1 0.1U_0402_10V7K TMDS_TX1N
<6> DDI1_LANE_N1
CX17 2 1 0.1U_0402_10V7K TMDS_TX1P
<6> DDI1_LANE_P1

1
CX18 2 1 0.1U_0402_10V7K TMDS_TX2N RX12
<6> DDI1_LANE_N0
CX19 2 1 0.1U_0402_10V7K TMDS_TX2P DLW21HN900HQ2L_4P 10K_0402_5%
<6> DDI1_LANE_P0
TMDS_TX0N 1 2 TMDS_L_TX0N
1 2

2
JHDMI
TMDS_TX0P 4 3 TMDS_L_TX0P HDMI_HPLUG 19
4 3 HP_DET

1
2
3
4

4
3
2
1
18
RP59 RP58 LX3 EMI@ 17 +5V
CPU_DPB_CTRLDAT_R 16 DDC/CEC_GND
680_8P4R_5% 680_8P4R_5% SDA
CPU_DPB_CTRLCLK_R 15
14 SCL

8
7
6
5

5
6
7
8
13 Reserved
TMDS_L_TXCN 12 CEC 20
11 CK- GND 21
DLW21HN900HQ2L_4P TMDS_L_TXCP 10 CK_shield GND 22
TMDS_TX1N 1 2 TMDS_L_TX1N TMDS_L_TX0N 9 CK+ GND 23
1 2 8 D0- GND
TMDS_L_TX0P 7 D0_shield
+3VS TMDS_TX1P 4 3 TMDS_L_TX1P TMDS_L_TX1N 6 D0+
4 3 D1-

1
5
D LX4 EMI@ TMDS_L_TX1P 4 D1_shield
C D1+ C
2 QX3 TMDS_L_TX2N 3
G 2N7002K_SOT23-3 2 D2-
D2_shield

1
S TMDS_L_TX2P 1
RX13 D2+

3
100K_0402_5% CONCR_099ATAC19NBLCNF
CONN@
2
LX5 EMI@
TMDS_TX2P 4 3 TMDS_L_TX2P
4 3

TMDS_TX2N 1 2 TMDS_L_TX2N 46@ ROYALTY HDMI W/LOGO


1 2
Part Number Description
DLW21HN900HQ2L_4P
RO0000002HM HDMI W/Logo:RO0000002HM

TMDS_L_TXCN @EMI@ CX23 1 2 3.3P_0402_50V8C

TMDS_L_TXCP @EMI@ CX24 1 2 3.3P_0402_50V8C

TMDS_L_TX0N @EMI@ CX25 1 2 3.3P_0402_50V8C

TMDS_L_TX0P @EMI@ CX26 1 2 3.3P_0402_50V8C

TMDS_L_TX1N @EMI@ CX27 1 2 3.3P_0402_50V8C


+5VS
TMDS_L_TX1P @EMI@ CX28 1 2 3.3P_0402_50V8C

B TMDS_L_TX2N @EMI@ CX29 1 2 3.3P_0402_50V8C B


+3VS
TMDS_L_TX2P @EMI@ CX30 1 2 3.3P_0402_50V8C
2

RX16 RX17
2.2K_0402_5% 2.2K_0402_5%
QX4B
1

1
2

DMN66D0LDW-7_SOT363-6 +3VS
G

1 6 CPU_DPB_CTRLCLK_R
<10> CPU_DPB_CTRLCLK
S

D
5

1
C
QX5 2 1 2 HDMI_HPLUG
G

<10> CPU_DPB_CTRLDAT 4 3 CPU_DPB_CTRLDAT_R MMBT3904_NL_SOT23-3 B


S

E RX15 1

1
QX4A <10> DPB_HPD 150K_0402_5%
DMN66D0LDW-7_SOT363-6 CX20 @

1
220P_0402_50V8J RX34
2 20K_0402_5%
RX14

2
100K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/04/01 Deciphered Date 2015/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B015P
Date: Tuesday, September 16, 2014 Sheet 20 of 56
5 4 3 2 1
1 2 3 4 5

W=40mils +LAN_IO rising time : >1ms and <100ms 60mils_3via


JP3 @
2 1 2 LAN_L@ 1
W=40mils +LAN_REGOUT RL1 +LAN_VDD10
+3VALW 2MM 0_0603_5%
LAN_SW@
+LAN_VDD33
+LAN_REGOUT 1 2
40mils_2via
CL39 W=40mils 1.5A
1U_0402_6.3V6K UL2 LL1
2 1 5 1 2.2UH_LQM2MPN2R2NG0L_30%
VIN VOUT 1 1 1 1 1 1

0.1U_0402_10V7K

0.1U_0402_10V7K
A 1 A

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

1U_0402_6.3V4Z
LAN_SW@

4.7U_0603_6.3V6K
1 1

CL5

CL6

CL7

CL8

CL9
CL4
WOL_EN 3 CL3
<30> WOL_EN EN 0.1U_0402_25V6
CL15 CL19 2 LAN_L@ 2 2 2 2 2 2
4 2 2 2
SS GND

2
RL27 APL3512ABI-TRG_SOT23-5
100K_0402_5% 1 @
@
CL38 RTL8111G(LDO mode) RTL8111GS(SWR mode) Place close to each VDD10 pin

1
0.1U_0603_25V7K
2

APL3512 PIN 4 tire to VIN

+LAN_VDD33 +3VALW +LAN_VDD33 +LAN_VDDREG


@
RL6 1 2 0_0603_5%
UL3
1 5
+3VALW OUT IN

0.1U_0402_16V7K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
2 @1 @1 1 @ 2 @1

CL12

CL13

CL14

CL16

CL17
RL40 GND
1 2 3 4 WOL_EN
10K_0402_5% OC EN @
2 2 2 1 2
SY6288C20AAC_SOT23-5

B These caps close to UL1: Pin 11,32 B


+LAN_VDD33 Rising time (10%~90%)>1mS and <100mS

CL30, CL31 close to UL1 Pin 17, 18 UL1


+LAN_VDD10 TL2
CL30 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C 17 3
<12> PCIE_PRX_LANTX_P3 HSOP AVDD10
CL31 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C 18 8
<12> PCIE_PRX_LANTX_N3 HSON AVDD10 30
AVDD10 22
DVDD10
+LAN_VDD33 S X'FORM_ NS0015 LF LAN
11 SP050005Y00
AVDD33 32 RL19
AVDD33 TL2 75_0603_5%
PCIE_PTX_LANRX_P3 13
<12> PCIE_PTX_LANRX_P3 HSIP MCT0 1 2
PCIE_PTX_LANRX_N3 14 23 +LAN_VDDREG MDI1- 1 16 MDO1-
<12> PCIE_PTX_LANRX_N3 HSIN VDDREG RD+ RX+
24 +LAN_REGOUT MDI1+ 2 15 MDO1+
REGOUT RD- RX-
3 14 MCT0 MCT1 1 2
1 MDI0+ 4 CT CT 13
MDIP0 2 MDI0- NC NC
MDIN0 5 12 RL20
4 MDI1+ 6 NC NC 11 MCT1 1
19 MDIP1 5 MDI1- CT CT 75_0603_5% EMI@
<10,26,30,47> PLT_RST# PERSTB MDIN1 MDI0- 7 10 MDO0- CL33
MDI0+ 8 TD+ TX+ 9 MDO0+
ISOLATEB 20 15 TD- TX- 100P_1206_2KV8J
ISOLATEB REFCLK_P CLK_PCIE_LAN <9> 2
16
REFCLK_N CLK_PCIE_LAN# <9> 2

<10,30> PCIE_WAKE#
PCIE_WAKE# 21
LANWAKEB CLKREQB
12
LAN_CLKREQ# <9> CL41
350UH_LF-H1201P-2
@
Place close to TCT pin
28 XTLO 5/2_EMI requests to change
CKXTAL1 0.01U_0402_16V7K
+LAN_VDD33 1 2 26 29 XTLI 1 from 10P to 100P.
RL39 10K_0402_5% LED1/GPO CKXTAL2
@ 25 @ T94 PAD~D
6 LED2 27 @ T95 PAD~D
7 NC LED0
C
9 NC 31 RL31 2 1 2.49K_0402_1%
C

10 NC RSET
NC
GND
33 For GCLK JLAN

RTL8106E-CG QFN 32P E-LAN CTRL XTLI 8


<19> XTLI PR4-
7
PR4+
+3VS
MDO1- 6
PR2-
+LAN_VDD33 CL36 5
1

1 2 XTLI PR3-
RL33
4
1K_0402_5% 10P_0402_50V8J YL2 PR3+
1 2 PCIE_WAKE# 1 2 MDO1+ 3
OSC GND PR2+
2

RL34 XTAL@
3 4 MDO0- 2
10K_0402_5% ISOLATEB OSC GND PR1-
CL37 25MHZ_10PF_7V25000014 MDO0+ 1
1 2 XTLO PR1+
9
2

XTAL@ GND
10P_0402_50V8J
RL35
10
15K_0402_5% GND
XTAL@
+3VS +LAN_VDD33
1

XTAL CONN@

@
LAN_CLKREQ# 1 2
RL37 10K_0402_5%
@
WOL_EN 1 2
D D
RL38 10K_0402_5%

Reserve 10K pull LAN_IO


Security Classification Compal Secret Data Compal Electronics, Inc.
Title
Issued Date 2014/04/01 Deciphered Date 2015/04/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
10/100 LAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B015P
Wednesday, September 10, 2014 Sheet 21 of 56
1 2 3 4 5
5 4 3 2 1

CA53, CA55 change Value


Line1-VREFO-L
CA71, CA51 place close to Pin 26 from 10U_0603_6.3V6M~D to
4.7U_0603_6.3V6K Line1-VREFO-R

CA57,CA58 close JACK_PLUG Delay circutis

1
+5VA +5V_PVDD +5V_PVDD
to UA1 pin1 RA165
4.7K_0402_5%
RA166
4.7K_0402_5%
+3VS +3VS

4.7U_0603_6.3V6K
CA71

4.7U_0603_6.3V6K
CA53

4.7U_0603_6.3V6K
CA55
+3VS 1 1 1
1 1 1

2
0.1U_0402_16V7K
CA51

0.1U_0402_16V7K
CA54

0.1U_0402_16V7K
CA56
1 1

1
2 2 2

0.1U_0402_16V7K
CA58

4.7U_0603_6.3V6K
CA57
LINE1-L CA67 1 2 1 2 Line-IN-L @ @ JACK_SENSE#
2 2 2 4.7U_0603_6.3V6K RA80 1K_0402_1% RA1 RA2
LINE1-R CA68 1 2 1 2 Line-IN-R 100K_0402_5% 100K_0402_5%
2 2 4.7U_0603_6.3V6K RA82 1K_0402_1%
D D

3
D
@
5 G QA5A
@ S DMN66D0LDW-7_SOT363-6
+3VS CPVDD 1 +CODEC_AVDD2 QA5B

4
6
UA1 CA61 DMN66D0LDW-7_SOT363-6
CA59 CA60 close CA59
1 1
CA60 1 26 4.7U_0603_6.3V6K JACK_PLUG# 1 2 2 G
D

DVDD AVDD1
to UA1 pin9 4.7U_0603_6.3V6K 0.1U_0402_16V7K
9 AVDD2
40
2 Reserve for HDA issue @
RA3
S

1
2 2 DVDD-IO 10K_0402_5% 1 1
36 CPVDD
CPVDD 41 +3VS +1.5VS +CODEC_AVDD2 @ @
6 PVDD1 46 CA1 CA2
<8> PCH_AZ_CODEC_BITCLK BCLK PVDD2 2 2 10U_0603_6.3V6M
RA8 1 2 0_0402_5% 10U_0603_6.3V6M
<8> PCH_AZ_CODEC_SDOUT 5
SDATA-OUT 13 JACK_SENSE# RA13 1 2 100K_0402_5%
HP/LINE1 JD(JD1) +3VS
<8> PCH_AZ_CODEC_SYNC 10 14 RA9 1 @ 2 0_0402_5%
SYNC MIC2/LINE2 JD(JD2) 15
1 2 8 SPDIFO/FRONT JD(JD3)/GPIO3
<8> PCH_AZ_CODEC_SDIN0 SDATA-IN
RA130 22_0402_5%
<8> PCH_AZ_CODEC_RST# 11
RESETB 32 HPOUT-L JACK_PLUG# RA4 1 2 200K_0402_5% JACK_SENSE#
HPOUT-L(PORT-I-L) 33 HPOUT-R
LINE1-R 21 HPOUT-R(PORT-I-R)
LINE1-L
Line1-VREFO-R
22
30
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
Reserve for cancel Delay circutis
Line1-VREFO-L 31 LINE1-VREFO-R 42 INT-SPK-L+ +5V_PVDD +5VS +MIC2-VREFO
23 LINE1-VREFO-L SPK-OUT-L+ 43 INT-SPK-L-
24 LINE2-R(PORT-E-R) SPK-OUT-L- 45 INT-SPK-R+
LINE2-L(PORT-E-L) SPK-OUT-R+ 44 INT-SPK-R- 2 1
+A_VCC SPK-OUT-R- RA1110
16 +5VA @ 0_0603_1% +5VS 2 1 MIC_IN
MONO-OUT RA53 2.2K_0402_5% RA29 1 2 0_0603_1%
2 @
GPIO0/DMIC-DATA A_MIC_DATA <31>
+3VALW 1 2 +MIC2-VREFO +MIC2-VREFO 29 3 MIC_CLK_C 2 1 2 1 RING2 RA30 1 2 0_0603_1%
RA10 0_0402_5% RING2 17 MIC2-VREFO GPIO1/DMIC-CLK 48 RA1111 RA1109 2.2K_0402_5% @
MIC_IN 18 MIC2-L(PORT-F-L)/RING SPDIF-OUT/GPIO2 @ 0_0603_1% RA31 1 2 0_0603_1%
C MIC2-R(PORT-F-R)/SLEEVE C
+RTCVCC 1 2 2 1 MIC1-L 19 @
RA11 0_0402_5% 10U_0603_6.3V6M CA74 MIC_CAP 37 RA32 1 2 0_0603_1%
CBP 35 1U_0402_6.3V6K 2 1 CA24 @
@ CBN
AGND was requested
+A_VCC 20
by Realtek NC
EC_MUTE# 47
<30> EC_MUTE# PDB 28 2.2U_0603_6.3V6K 2 1 CA23
RA12 1 2 100K_0402_5% VREF 12
GNDA GND
CA62 1 2 10U_0603_6.3V6M 27 PCBEEP 34 1U_0402_6.3V6K 2 1 CA25
CA63 1 2 10U_0603_6.3V6M 39 LDO1-CAP CPVEE
@EMI@ CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP
RA1112 LDO3-CAP Place on the moat between GND & GNDA.
0_0402_5% 0_0402_5%
PCH_AZ_CODEC_BITCLK 1 2 1 2 4 25
@ RA1113 DVSS AVSS1 38
49 AVSS2
1 GND
@EMI@
CA21 ALC3234-CG_MQFN48_6X6
22P_0402_50V8J
2 LA1 EMI@
MIC_CLK_C 1 2 A_MIC_CLK DA8
A_MIC_CLK <31>
BLM15BB221SN1D_2P 2
PC_BEEP 2 1 RA79 2 1 CA65 EC Beep <30> BEEP#
1K_0402_1% 0.1U_0402_16V7K 1 PC_BEEP
SM01000BV00 1
@EMI@
100P_0402_50V8J 2 1 CA69 @ need CIS symbol CA22
MCU Beep <11> HDA_SPKR
3

1
22P_0402_50V8J
2 BAT54C-7-F_SOT23-3 @
1 2 RA19
RA81 10K_0402_5% 10K_0402_5%

2
+RTCVCC

PC Beep
1

MIC_IN
B RA5 Close to UA1 B
470K_0402_5% Pin11,13,14,16
close to Codec
2

JSPK
3

INT-SPK-R- EMI@ LA3 1 2 NBQ160808T-800Y-N 0603 SPK_R1-_CONN 1


5 G
D
QA6A INT-SPK-R+ EMI@ LA4 1 2 NBQ160808T-800Y-N 0603 SPK_R2+_CONN 2 1
QA6B S DMN66D0LDW-7_SOT363-6 INT-SPK-L- EMI@ LA5 1 2 NBQ160808T-800Y-N 0603 SPK_L1-_CONN 3 2
DMN66D0LDW-7_SOT363-6 INT-SPK-L+ EMI@ LA6 1 2 NBQ160808T-800Y-N 0603 SPK_L2+_CONN 4 3
4

4
6