You are on page 1of 14

EECE481

CMOS Fabrication in Deep Submicron Technology

R. Saleh
Dept. of ECE
University of British Columbia
res@ece.ubc.ca

RAS EECE481 1

CMOS Has Two Transistor Types

g
Look at cross-section
s d

nMOS pMOS

n+ n+ p+ p+
p n

n+ to p substrate
substrate must be p substrate must be n
• CMOS devices require two types of substrate for isolation of
transistors
• n-type for pMOS (usually in an N-well)
• p-type for nMOS (usually substrate material)
RAS EECE481 2

1
EECE481

Fabrication Steps

Fabrication is the process used to create devices and wires.


• We will look at how to create:
– Working transistors
• ndiff, pdiff, wells, poly, transistors, threshold adjust implants
– Wires
• contacts, metal1, via, metal2

Fabrication is pretty complex.


• Give a brief overview of the process, for background.
• Want to understand origin of layout rules / process parameters
– The abstractions of the process for the designer (us).

RAS EECE481 3

Making Chips

20-30 masks

Masks
100-1000 chips

Layout
Chips

200-300mm diameter Processed


0.35mm-1.25mm thick Wafer
Wafers
Chemicals

Fabrication

RAS EECE481 4

2
EECE481

Basic Fabrication Step

Two parts:
1) Transfer an image of the design to the wafer
2) Using that image as a guide, create the desired layer on silicon
– diffusion (add impurities to the silicon)
– oxide (create an insulating layer)
– metal (create a wire layer)

Use the same basic mechanism (photolithography) to do step 1.


Use three different methods to do step 2.
• Ion Implant - used for diffusion. Shoot impurities at the silicon.
• Deposition - used for oxide/metal. Usually from chemical vapor
deposition (CVD)
• Grow - used for some oxides. Place silicon in oxidizing ambient.
RAS EECE481 5

Basic Processing

Start with wafer at current step

Spin on a photoresist

UV light
Glass mask
Pattern photoresist with mask

Step specific processing


etch, implant, etc...

Wash off resist

RAS EECE481 6

3
EECE481

Integrated Circuit Fabrication

• Repeat:
– Create a layer on the wafer
– Put a photo-sensitive material (resist) on top of the wafer
– Optically project an image of the pattern you desire on the wafer
– Develop the resist
– Use the resist as a mask to prevent the etch (or other process) from
reaching the layer under the resist, transferring the pattern to the
layer
– Remove the resist
• Key point is that all the chips (die) on the wafer are processed in
parallel, and for some chemical steps, many wafers are processed in
parallel.

RAS EECE481 7

Making Transistors

Cross-sectional View Plan View


p-well n-well
1. Create n and p
wells; Create STI STI STI

shallow trench
isolation regions

2. Define thin oxide gate oxide gate oxide


grow field oxide,
implant doping to
adjust transistor
threshold, grow
thin oxide.
polysilicon gate polysilicon gate

3. Deposit and etch


polysilicon

RAS EECE481 8

4
EECE481

Making Transistors

n+ implant p+ implant

4. Implant source
and drain

5. Coat the top of the polycide

poly and diffusion


salicide
with metal to
reduce resistance.
(silicide). Poly with
silicide is referred
to as polycide
Notice that the diffusion regions are formed in a self-aligned
process. An oversized implant mask is used, but the STI regions
and poly themselves actually define the diffusion regions. So,
difficult alignment is avoided.
RAS EECE481 9

Final CMOS Structure

shallow
trench spacers polycide
isolation salicide

n+ n+ p+ p+

STI p-well STI n-well STI

Drain/source extensions

substrate

RAS EECE481 10

5
EECE481

Making Wires

Insulating material

1. Deposit insulator
may be polished
to make it flat

contact cuts
contact cuts filled with tungsten
2. Etch contacts to Si
fill with conductor

RAS EECE481 11

Making Wires

Deposited and patterened metal 1

3. Deposit first
metal layer and
then pattern to
provide desired
connections Deposited and patterened metal 2
Metal 1 Metal 2

4. Repeat same
steps for all
subsequent layers

RAS EECE481 12

6
EECE481

Multi-level Interconnect Structure

Today, wires are made of copper (both metal and via)

M6

via5
Cu
M5
low-k between wires via4
via1 M4
via3
M1 M3
contact via2
(W) M2
silicon

RAS EECE481 13

Fabrication Information

• Now that we know what fabrication is trying to do, how do we tell


them precisely what to build?
GDS-II

“tapeout”

Layout
Design (mask data) Foundry

House (Fab)
Design Rules
(layout)
Process Parameters
(simulation)

• We don’t care about the real details of the fab, but we have to
define the patterning of the layers (that meet their rules) to
specify our design.
• Sometimes knowing more about the fab details is useful when
you need to debug a part.

RAS EECE481 14

7
EECE481

Geometric Design Rules

(a) Resolution
3λ min. width rule
min. spacing 3λ


(b) Alignment
min. poly width 2λ poly overlap
of field 2λ
min. contact
size 2λx2λ min. contact
spacing to
poly to gate 2λ
diffusion
spacing 2λ min. contact
overlap λ

RAS EECE481 15

Transistor Layout Issues

Which one is the preferred layout?

n+ diffusion

D λ x 2λ
2λ λ p-well D
λ x 2λ
2λ λ
λ

polysilicon λ

G λ
W=4λ λ
L=2λ
p+ diffusion
G λ
W=2λ λ
L=2λ

λ
2λ λ
Z=2λ contact
λ
5λ λ

S
S B

n+ diffusion

(this one)

RAS EECE481 16

8
EECE481

Deep Submicron MOS Device Models

• For deep submicron devices, we must have an elaborate set of


device models in SPICE to handle realistic situations when the
chip is fabricated
• To address these issues, we will:
• Briefly review the most important issues
• Device modeling history
• Binning of device sizes
• Process variations
• Temperature variations
• Voltage variations

RAS EECE481 17

MOSFET Modeling… 2 basic approaches

Physical parameters make physical sense; mostly extracted


from process (tox, Leff, etc.) ; usually few params

Empirical curves match measured devices well parameters


are difficult to understand, and there are lots
parameters extracted from carefully measured
devices

Reality is always a compromise between the two.


***NOTE***
Empirical models can break in unpredictable ways if pushed
beyond their characterization space. (but we need them since
physics can only help us model to the limits of our knowledge)

RAS EECE481 18

9
EECE481

Brief history of Spice MOS models

• First generation
• Hspice Level 1, 2, 3
• “physical” analytical models with geometry in model
equations
• Holding onto hand-calculation...
• Second generation
• Hspice level 13 (Bsim), 28 (“MetaMOS”), 39(Bsim2)
• Shift in emphasis to circuit simulation with lots of
mathematical conditioning
• Quality of outcome is highly dependent on parameter
extraction methodology
• Good luck with hand-calculation
• => BUT served industry well for over 12 years!

RAS EECE481 19

Spice MOS models... the present

• Second generation models fell apart somewhere between 0.8m


and 0.5m
• There is also a new need: low-voltage design

• Third generation: Hspice level 49 (Bsim3v3), 55 (EKV)

Bsim3 intent was return to simplicity... but... now Bsim3v3 > 100
parameters!
– Vendors have now figured out how to reliably build Bsim3v3
models
– You will be using a Bsim3v3 model (or BSIM4 in the future)

EKV model developed by EPFL in Switzerland... has promise

RAS EECE481 20

10
EECE481

Checking out your models

Linear
Generate IV Characteristics

RAS EECE481 21

Checking out your models

• Try out multiple W/L’s and compare against measure data


• Try out NMOS and PMOS devices
• Check out Ids vs. Vgs to estimate VT
• Try different temperature ranges
• Check out Ids vs. Vgs
• Check out Ids vs. Vbs
• Check out VT vs. L
• Check out VT vs. W
• Run simple timing experiments: compute Req, Cg, Cj, etc.
• For analog circuits, need to plot gm, gds, gmbs
• etc...

RAS EECE481 22

11
EECE481

Ids vs. Vgs (NMOS)

• Plot log(Ids) vs. Vgs


Active
• Examine two regions
Log IDS
•saturation
•subthreshold Subthreshold
• Leakage currents flow
when device is
completely off Leakage

VGS

RAS EECE481 23

Binning approach to Modeling

• May need to bin space of models & stay inside covered space
Wmax

Wmin

Lmin Lmax
Beware of non-physical behavior beyond boundaries! Some model sets
were really just developed with minimum L’s rather than all possible L’s.

RAS EECE481 24

12
EECE481

Process Variations

• So far we have talked about


transistors as if all transistors Normal Distribution

were the same 1

• Not true -- no two are exactly 0.8

alike 0.6

Prob
Series1
• Parameters of a fabrication 0.4

run are generally normally


0.2
distributed - mean, standard
deviation 0
-3 -2 -1 0 1 2 3
sigma

RAS EECE481 25

Circuit Parameters

• We need a way to identify and use the extreme points in


parameter distributions (spec limits)
• Wan to stress circuits at these points
• Good place to test your design for robustness

• Define Process Corners:


• Select appropriate process parameters:
– Poly linewidth, nMOS Vt, pMOS Vt, Tox,
P
– metal width, oxide thickness

• Choose operating conditions


– Operating voltage (die voltage) V
– Temp (0-100oC die temp) T

RAS EECE481 26

13
EECE481

Process Corners

• Group parameters into transistor effects, and operating effects


• nMOS can be slow, typical, fast (S, T, F)
• pMOS can be slow, typical, fast (S, T, F)
• Temperature can be hot, typical, cold (S, T, F)
• Vdd can be high, typical, low (F, T, S)

• Label process corner as nMOS, pMOS, Temp, Vdd


TTTT = typical nMOS, typical pMOS, room temp, nominal supply
SSSS = slow nMOS, slow pMOS, hot temp, low supply
FSSS = fast nMOS, slow pMOS, hot temp, low supply

RAS EECE481 27

Summary of MOS Spice modeling

• Big problem of MOS modeling exists


- No one really makes sure that you have a good model
-There is still disagreement between fab folks & circuit folks...
you may hear:
“any circuit design that requires such an accurate model
must be broken to begin with”
• Result: caveat emptor
Do the following and you will be safe: demand good models and
make your circuits tolerant of variations in supply, process and
temperature

RAS EECE481 28

14