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You are on page 1of 4

This lecture reviews the design of combination logic and introduces the use of VHDL for logic design.

After this lecture you should be able to convert a text description of a combinational logic circuit into three forms: (1)

a truth table, (2) a sum of products boolean equation, and (3) a VHDL entity/architecture description.

Logical Variables and Boolean Alge- a b c p

0 0 0 1

bra 0 0 1 0

0 1 0 0

A logic variable can take on one of two values, typ- 0 1 1 1

ically called true and false (T and F). With positive- 1 0 0 0

true logic true values are represented by a high (H) 1 0 1 1

voltage. With negative-true logic true values are rep- 1 1 0 1

resented by a low (L) voltage. Variables using neg- 1 1 1 0

ative logic are usually denoted by placing a bar over

the name (B), or an asterisk after the variable name

( ).

Warning: We will use or 1 and 0 to represent truth Sum of Products Form

values rather than voltage levels. However, some au-

thors use 1 and 0 to represent voltage levels instead. From the truth table we can obtain an expression for

This can be very confusing. Also note that an overbar each output as a function of the input variables.

is sometimes used to indicate a logical complement The simplest method is to write a sum of prod-

operation rather than a negative-true signal. ucts expression. Each term in the sum corresponds

to one line of the truth table for which the desired

output variable is true (1). The term is the product

Combinational Logic of the each input variable (if that variable is 1) or its

complement (if that variable is 0). Each such term is

A combinational logic circuit is one where the output

called a minterm and such an equation is said to be

is a function of the current input only. A combina-

in canonical form.

tional logic circuit can be represented as:

For example, the variable above takes on a value

a truth table that shows the output values for of 1 in four lines (the first, fourth, sixth and seventh

each possible combination of input values, lines) so there would be four terms. The first term

corresponds to the case where the input variables are

a boolean equation that defines the value of , and . So the term is abc. Note

each output variable as a function of the input that this product will only be true when a, b and c

variables, or have the desired values, that is, only for the specific

a schematic that shows a connection of hard- combination of inputs on the third line.

ware logic gates (and possibly other devices) If we form similar terms for the other lines where

that implement the circuit. the desired output variable takes on the value one and

then sum all these terms we will have an expression

Truth Tables that will evaluate to one only when required and will

evaluate to zero in all other cases.

For example, the truth table for a circuit with an out-

put that shows if its three inputs have an even number Exercise: Write out the sum-of-products equation for .

of 1s (even parity) would be: Evaluate the expression for the first two lines in the table.

1

Common Combinational Logic Circuits B A a b c d e f g

0 0 1 1 1 1 1 1 0

In addition to the standard logic functions (NAND, 0 1 0 1 1 0 0 0 0

OR, etc) some combinational logic functions are 1 0 1 1 0 1 1 0 1

widely used and are often available as SSI ICs and 1 1 1 1 1 1 0 0 1

as library blocks for ASIC design:

From the truth table we can then write out the sum

a decoder is a circuit with inputs and

of products expressions for each of the outputs:

outputs. The output selected by the input bits

a = AB + AB + AB

(treated as a binary number) is set true and the

b = 1

other outputs are false. This circuit is often used

c = AB + AB + AB

for address decoding.

d = AB + AB + AB

a priority encoder does the inverse operation. e = AB + AB

The output bits represent the number of the f = AB

(highest numbered) input line. g = AB + AB

Exercise: Draw a schematic of a circuit that imple-

a multiplexer copies the value of one of in- ments the above logic function.

puts to a single output. The input is selected by

an -bit input.

Combinational Logic Design with

a demultiplexer does the inverse operation and

copies one input to one of outputs. VHDL

adders, comparators and ALUs (arithmetic VHDL is a Very-complex Hardware Description

logic units) implement the basic arithmetic and Language that we will use to design logic circuits.

logic functions

state or open collector (OC) outputs Lets start with a simple example a type of circuit

called example1 that has one output signal (c) that

Exercise: Write out the truth table and the canonical is the AND of two input signals (a and b). The file

sum-of-products expression for a 2-to-1 multiplexer. example1.vhd contains the following VHDL de-

scription:

Example: 7-segment display driver

LED numeric displays typically use seven segments -- example 1: An AND gate

to 9: a, b: in bit ;

a c: out bit ) ;

end example1 ;

f b

g architecture rtl of example1 is

begin

e c process(a,b)

d begin

c <= a and b ;

This example shows the design of a circuit that end process ;

end rtl ;

converts a 2-bit number into seven outputs that turn

the segments on and off to show numbers between 0

First some observations on VHDL syntax:

and 3. We use the variables A and B for the two input

bits and a to g for the seven outputs. We can build up Actually, the V stands for VHSIC. VHSIC stands for Very

a truth table for this function as follows: High Speed IC.

2

VHDL is case-insensitive. There are many cap- Example 2 - if/then/else

italization styles. I prefer all lower-case. You

Within a process we can use other programming

may use whichever style you wish as long as

language constructs such as if/then/else and

you are consistent.

case statements.

Everything following two dashes -- on a line The next example uses an if/then/else state-

ment in a process:

is a comment and is ignored.

Statements can be split across any number of -- example 2: XOR using if/then/else

lines. A semicolon ends each statement. In- entity example2 is port (

dentation styles vary but an end should be in- x1, x2: in bit ;

dented the same as its corresponding begin y: out bit ) ;

end example2 ;

Entity and signal names begin with a letter fol- architecture rtl of example2 is

begin

lowed by letters, digits or underscore ( ) char- process(x1,x2)

acters. begin

if x1 /= x2

then

A VHDL description has two parts: an entity part y <= 1 ;

else

and an architecture part. The entity part defines the y <= 0 ;

input and output signals for the device or entity end if ;

end process ;

being designed while the architecture part describes end rtl ;

the behaviour of the entity.

Each architecture is made up of one or more pro- which synthesizes to the following:

cesses, all of which execute at the same time (con-

currently). Within each process, statements are exe-

cuted one after the other (sequentially). Relational operators that can be used in expres-

The (a,b) after process is called the sen- sions include = (equal), /= (not equal), >, <, >=,

sitivity list and should include all the signals that and <=. The result of relational operators is of type

might affect the value(s) computed in the process. boolean.

The single statement in this examples single pro- The logical operators (e.g. and) can also be ap-

cess is a signal assignment that assigns the value of plied to values of type boolean. However, note that

an expression to the output signal c. Expressions in general there is no automatic type conversion in

involving signals of type bit can use the logical op- VHDL. For example, boolean values cannot be as-

erators and, nand, or, nor, xor, xnor, and not. signed to bit values and integers cannot be assigned

Parentheses can be used to force evaluation in a cer- to bit vectors.

tain order. Exercise: What schematic would you expect if the /=

To ensure that well end up with a simple combi- were replaced with = ?

national circuit each output signal should be assigned

a value exactly once in the architecture.

Example 3 - Vectors

From this VHDL description a program called a

logic synthesizer can design a circuit that has the re- VHDL also allows signals of type bit_vector

quired functionality. In this case its not too surpris- which are one-dimensional arrays of bits. The next

ing that the result is the following circuit: example is a VHDL description of the 7-segment

LED driver and demonstrates the case statement

and bit vectors.

The resulting hardware doesnt actually execute but this -- example 3: 7-segment LED driver for

point of view is useful when using VHDL for simulation. -- 2-bit input values

3

Exercise: Re-write example 3 so that the architecture

entity example3 is port (

uses only signal assignments.

n: in bit_vector (1 downto 0) ;

seg: out bit_vector (6 downto 0) ) ;

end example3 ;

begin

process(n)

begin

case n is

when "00" => seg <= "1111111" ;

when "01" => seg <= "0110000" ;

when "10" => seg <= "1101101" ;

when "11" => seg <= "1111001" ;

end case ;

end process ;

end rtl ;

increasing (upto) or decreasing (downto) values.

bit_vector constants are formed by enclosing an

ordered sequence of bit values in double quotes.

Exercise: If x is declared as bit vector (0 upto

3) and in a process the assignment x<="0011" is made,

what is the value of x(3)? What if x had been declared

as bit vector (3 downto 0)?

Substrings of vectors can be extracted by speci-

fying a range in the index expression and vectors

can be concatenated using the & operator. For ex-

ample x <= x(6 downto 0) & 0 would

shift the 8-bit value x left by 1 bit.

The logical operators (e.g. and) can be applied

to bit vectors and operate on a bit-by-bit basis. The

= and /= operators can also be used and evaluate to

true only if all elements are the same.

Exercise: Write a VHDL entity and architecture for the

2-to-1 multiplexer designed in the previous exercise. Use

a case statement.

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