Zero-voltage-switching DC/AC inverter

C.-M. Wang

Abstract: A novel zero-voltage-switching (ZVS) DC/AC inverter is proposed. The proposed

inverter can not only provide output voltage that is higher or lower than DC input voltage but
can also use the pulse-width modulation (PWM) control technique. Furthermore, in the proposed
inverter, besides operating at constant frequency, all semiconductor devices operate at soft-
switching without additional voltage stress and current stress. A design example of 1000 W
ZVS PWM buck boost inverter is examined to assess the inverter performance.

1 Introduction voltage characteristic but also provides ZVS on all semicon-

Voltage-source pulse-width modulation (PWM) inverters
have been widely used in industrial applications such as unin-
terruptible power supplies, static frequency changers and
variable speed drives. This is due to their capability in allow-
ing continuous and linear control of the frequency and funda-
mental component of the output voltage. However, the
conventional voltage source inverter (VSI) shown in Fig. 1a,
referred to as buck PWM inverter in this paper [16], is prob-
ably the most popular and important power converter top-
ology. But its instantaneous average output voltage is
always lower than the input DC voltage, thus decreasing its
application range. In order to extend its application range, a
boost PWM DC/DC converter must be used between the
DC source and the buck PWM inverter so that the inverter
can have the step-up and step-down voltage characteristics.
It is shown in Fig. 1b. However, this solution has some draw-
backs. First, because it has a separate main circuit and a con-
troller, the switching cycle is asynchronous and the switching
noise of the main circuit and controler interfere with each
other. Second, to minimise size and weight and to reduce
switching losses and electromagnetic interference, the oper-
ation frequency must be increased and the soft-switching tech-
niques must be used. This solution will result in high
complexity of overall circuit, an increase in weight, high
cost and reduced efficiency. To overcome these, the author
has proposed a single-stage series-resonant buckboost
inverter [79]. Series resonant method is used to
accomplish step-up/down function with single-stage
topology and these topologies operate at discontinuous
conduction mode. Thus, this inverter suitable for lower
power application.
A novel single-stage zero-voltage-switching (ZVS)
PWM buck boost inverter using PWM technology and
suitable for medium power application is proposed in this
paper and shown in Fig. 1c. Although this topology is the
same as combining the boost PWM DC/DC converter
with the buck PWM inverter, the control strategy in the pro-
posed inverter is not the same. The new control strategy not
only enables the boost DC/DC converter to have the boost
# The Institution of Engineering and Technology 2007
doi:10.1049/iet-epa:20060166
Paper first received 9th October 2005 and in revised form 3rd August 2006
The author is with the Department of Electrical Engineering, National Ilan
University, 1, Sec. 1, Shen-Lung Road, I-Lan 260, Taiwan, Republic of China
E-mail: jimiwang@ms6.hinet.net
IET Electr. Power Appl., 2007, 1, (3), pp. 387 394
ductors in the buck inverter. Also, the switching cycle of the
boost DC/DC converter and buck PWM inverter in the pro-
posed inverter is synchronous. The switching noise interfer-
ence can be removed. Furthermore, in order that all
semiconductor devices in the proposed inverter operate at
soft-switching without additional voltage stress and current
stress, the proposed inverter also uses a ZVSPWM
commutation cell. Thus, the switching losses in the proposed
inverter can be reduced. It not only has the step-up and step-
down voltage characteristic depending on the duty-cycle but
its configuration is inherently simple and compact. To
achieve dynamic regulation and to properly gate the power
switches, the sinusoidal PWM (SPWM) control strategy is
designed. System analysis for predicting and evaluating
the inverter performance are conducted.
2 Principle of the ZVS PWM buck boost
inverter
The power stage diagram of the proposed ZVS PWM
buck boost inverter is shown in Fig. 1c. The circuit can
be divided into three sections. The first section is a conven-
tional PWM buck inverter with unipolar voltage switching.
It is composed switches S1 , S2 , S3 , S4 and output filters Lf ,
Cf . The second section is the PWM continuous conduction
mode step-up DC/DC converter, composed of L1 , Sa1 and
C1 . This section operates as a fixed duty-cycle and fre-
quency boost DC/DC converter. It provides the ZVS on
all semiconductors in the buck inverter. The third section
is a ZVS PWM commutation cell to provide the soft-
switching on switch Sa1 . It is composed of auxiliary
diodes Da1 , Da2 , Da3 , resonant inductors Lr1 , Lr2 , resonant
capacitors Cr1 , Cr2 and auxiliary switch Sa2 , which are
rated for a small power when compared with the output
power. In the positive (negative) half-period of the desired
output vo(t), switch S2 (S1) is always off, switches S1 (S2)
and S4 (S3) always on, and switch S3 (S4) performs the
inversion function at high frequency switching, whereas
switch Sa1 performs the boost DC/DC conversion function
in PWM continuous conduction mode. For convenience in
analysis, only the positive-half period of the desired
output voltage is described. To simplify the analysis, it is
assumed that the proposed ZVS PWM buck boost inver-
ter is operating in the kth switching period and the
following assumptions are made during one switching
cycle.
387
 zero-current-switching (ZCS) and S3 turns off with ZVS
S2 S1
Lf at t t0 . Resonant inductor Lr2 charges linearly with
voltage VC1k . The resonance also begins. Both resonant
Vin Cf RL current iLr1(t) and resonant voltage vCr1(t) are increased via
the resonance of Lr1 and Cr1 . The stage ends when the
S3 S4 sum current of resonant currents iLr1(t) and iLr2(t) reaches
input current IL1k ILfk and body diodes of switches S1 ,
a S2 , S3 and S4 naturally turn off with ZVS at t t1 .

S2 S1
2.1.2 Stage 2 [Fig. 2b: t1 , t , t2]: During this stage,
Lf the ZVS PWM commutation cell continuously maintains
resonance behaviour. Resonant currents iLr1(t), iLr2(t) and
Cf RL resonant voltages vCr1(t), vCr2(t) are continuously increased.
LB
The energy stored in capacitor C1 flows gradually to the
CB
Vin S3 S4 buck inverter. Input inductor L1 is gradually charged with
input voltage Vin . The stage ends when resonant voltage
Boost DC/DC Converter vCr2(t) drops to zero.
b
2.1.3 Stage 3 [Fig. 2c: t2 , t , t3]: This stage begins
L1 C1 p when resonant voltage vCr2(t) is equal to zero and the
body diode of switch Sa1 turns on at ZVS. Because the free-
Da1 wheeling loop is formed by D3a , Lr2 , Sa2 , D1a and the body
S2 S1 Lf
diode of Sa1 in this stage, resonant current iLr2(t) is main-
Sa2 A
tained at the value iLr2(t2). Resonant inductor Lr1 and
Vin Cf ZL
Sa1
Cr2 capacitor Cr1 continuously maintain resonance behaviour
Lr1 Lr2
Da2 B in Stage 2. Resonant current iLr1(t) decreases and resonant
voltage vCr1(t) continuously increases. The energy stored
Cr1 Da3 S4 S3 in capacitor C1 flows continuously to the buck inverter.
n Input inductor L1 is continuously charged with input
c voltage Vin . This stage ends when the sum current of res-
onant currents iLr1(t) and iLr2(t) is equal to input current
Fig. 1 Voltage source PWM invertors IL1k ILfk again and the body diode of switch Sa1 naturally
a Conventional VSI closes at ZCS and ZVS.
b Conventional circuit used to generate an output voltage larger than
input DC voltage
c Circuit topology of the novel ZVSPWM buck boost inverter
2.1.4 Stage 4 [Fig. 2d: t3 , t , t4]: During this stage,
the resonance continues in Stage 3. Resonant currents
iLr1(t) and iLr2(t) flow through switch Sa1 and its body
1. All components and devices are ideal. diode turns off with ZCS and ZVS at t t3 . Resonant
2. Input filter inductance L1 is large enough to assume that current iLr2(t) is continuously maintained at the value,
input current IL1k is constant during the kth switching period iLr2(t2). Resonant current iLr1(t) increases towards its nega-
and is much greater than that of resonant inductor Lr1 and Lr2 . tive peak value. Resonant voltage vCr1(t) continuously
3. Output filter inductance Lf is large enough to assume that increases. The energy stored in capacitor C1 flows continu-
output current ILfk is constant during the kth switching ously to the buck inverter and input inductor L1 is continu-
period. ously charged with input voltage Vin . This stage ends when
4. Capacitor C1 is large enough to assume that voltage VC1k resonant current iLr1(t) is equal to resonant current iLr2(t).
is constant during the kth switching period. Diode Da1 is naturally closed and switch Sa2 is turned off
5. Input voltage Vin is constant. at ZCS.
6. During the kth switching period, resonant voltage vCr1(t)
is equal to zero and resonant voltage vCr2(t) is equal to VC1k , 2.1.5 Stage 5 [Fig. 2e: t4 , t , t5]: This stage begins
and resonant currents iLr1(t) and iLr2(t) are equal to zero. when switch Sa2 turns off at ZCS. The resonance begins
by the way of Cr1 , Lr1 , Lr2 and Da3 . Resonant current
Based on these assumptions, circuit operations in one
iLr1(t) increases continuously towards the negative peak
switching cycle can be divided into nine stages. The nine
value and then decreases when it reaches peak value.
dynamic equivalent circuits of the new ZVS PWM
Resonant current iLr2(t) increases towards the positive
buck boost inverter during one switching period are
peak value and then decreases when it reaches peak value.
shown in Fig. 2. The ideal relevant waveform of the new
The energy stored in capacitor C1 is continuously provided
ZVS PWM buck boost inverter is shown in Fig. 3.
to the buck inverter and input inductor L1 is continuously
charged with input voltage Vin . Resonant voltage vCr1(t)
2.1 Stage of operation of the new ZVS PWM decreases. This stage ends when resonant currents iLr1(t),
buck boost inverter iLr2(t) reach zero and diode Da3 naturally closes at ZCS.

2.1.1 Stage 1 [Fig. 2a: t0 , t , t1]: Before t t0 , 2.1.6 Stage 6 [Fig. 2f: t5 , t , t6]: This stage begins
switches Sa1 , Sa2 and S2 maintain turn-off state, and when diode Da3 turns off at ZCS. The energy stored in
switches S1 , S3 and S4 maintain turn-on state. The energy capacitor C1 flows continuously to the buck inverter, and
stored in inductor L1 is delivered to capacitor C1 while input inductor L1 is continuously charged with input
the output loop of the inverter is in a freewheeling voltage Vin . The remaining semiconductors are in the off
state. This stage begins when Sa2 turns on with state.
388 IET Electr. Power Appl., Vol. 1, No. 3, May 2007
 L1 C1 p L1 C1 p

IL1k VC1k + IL1k VC1k +

Da1 Da1
S2 S1 Lf S2 S1 Lf
Cr2 Sa2 A Cr2 Sa2 A
ILfk ILfk
Vin vCr2 Lr1 Lr2 Cf ZL Vin vCr2 Lr1 Lr2 Cf ZL
Sa1 + iLr1 Sa1 + iLr1
iLr2 B iLr2 B
Da2 Da2

vCr1 Cr1 Da3 vCr1 Da3
S4 S3 Cr1 S4 S3
+ +
n n
a b

L1 C1 p L1 C1 p

IL1k VC1k + IL1k VC1k +

Da1 Da1
S2 S1 Lf S2 S1 Lf
Cr2 Sa2 A Cr2 Sa2 A
ILfk ILfk
Vin vCr2 Lr1 Lr2 Cf ZL Vin vCr2 Lr1 Lr2 Cf ZL
Sa1 + iLr1 Sa1 + iLr1
iLr2 B iLr2 B
Da2 Da2

vCr1 Da3 vCr1 Da3
Cr1 S4 S3 Cr1 S4 S3
+ +
n n
c d

L1 C1 p L1 C1 p

IL1k VC1k + IL1k VC1k +

Da1 Da1
S2 S1 Lf S2 S1 Lf
Cr2 Sa2 A Cr2 Sa2 A
ILfk ILfk
Vin vCr2 Lr1 Lr2 Cf ZL Vin vCr2 Lr1 Lr2 Cf ZL
Sa1 + iLr1 Sa1 + iLr1
iLr2 B iLr2 B
Da2 Da2

vCr1 Da3 vCr1 Da3
Cr1 S4 S3 Cr1 S4 S3
+ +
n n
e f

L1 C1 p L1 C1 p

IL1k VC1k + IL1k VC1k +

Da1 Da1
S2 S1 Lf S2 S1 Lf
Cr2 Sa2 A Cr2 Sa2 A
ILfk ILfk
Vin vCr2 Lr1 Lr2 Cf ZL Vin vCr2 Lr1 Lr2 Cf ZL
Sa1 + iLr1 Sa1 + iLr1
iLr2 B iLr2 B
Da2 Da2

vCr1 Da3 vCr1 Da3
Cr1 S4 S3 Cr1 S4 S3
+ +
n n
g h

L1 C1 p

IL1k VC1k +
Da1
S2 S1 Lf
Cr2 Sa2 A
ILfk
Vin vCr2 Lr1 Lr2 Cf ZL
Sa1 + iLr1 iLr2 B
Da2

vCr1 Cr1 Da3 S4 S3
+
n
i

Fig. 2 Topology stages of the new ZVS PWM buckboost inverter

2.1.7 Stage 7 [Fig. 2g: t6 , t , t7]: This stage begins capacitor Cr2 is continuously charged by current IL1k .
when switch Sa1 turns off at ZVS. Resonant capacitor Cr2 Resonant voltage vCr1(t) decreases linearly and resonant
is charged by current IL1k . Resonant voltage vCr2(t) increases voltage vCr2(t) increases linearly. The energy stored in capaci-
linearly. The energy stored in capacitor C1 flows continu- tor C1 flows continuously to the inverter and continuously
ously to the inverter and gradually decreases. This stage decreases. This stage ends when resonant voltage vCr1(t) is
ends when resonant voltage vCr2(t) is equal to resonant equal to zero and resonant voltage vCr2(t) is equal to VC1k .
voltage vCr1(t).
2.1.9 Stage 9 [Fig. 2i: t8 , t , t9]: In this stage, the
2.1.8 Stage 8 [Fig. 2h: t7 , t , t8]: In this stage, energy stored in inductor L1 is delivered to capacitor C1
resonant capacitor Cr1 is discharged and resonant and the energy stored in capacitor C1 stops flowing to the
IET Electr. Power Appl., Vol. 1, No. 3, May 2007 389
 1
iLr1 vr p 6
t Cr1 Lr1
vCr1
iLr2
t s
Lr1
vCr2
t Zo 7
VC1k Cr1
vSa1 t
VC1k iSa1 v
3
IL1k+ ILfk u 2  s
2
t u
u1 1 1 1 1 4 5
VC1k iSa2 vSa2
KA t 4 1 1

IL1k+ ILfk 2 nC nC nL nC nC nL nC nL
t
vpn
VC1k 8
t
vAB v
VC1k u 2  s 3

2
u
t u 1 1 1 1 1 4
KB t 4 1
1
5
2 nC nC nL nC nC nL nC nL
Vgate,Sa1
t
Vgate,Sa2
9
t
The kth output voltage Vok of the inverter is
Vgate,S1
t Ts
Dk
h2
Vgate,S2
t
Vok vABk dt Dk
h2 VC1k Vin 10
0 1
D k h1
Vgate,S3
t where
Vgate,S4
t
t0t1 t2 t3 t4 t5 t6 t7 t8 t9 Lr IL1k =VC1k nL =1nL p=4vr
DkTs
KA2
KB2 =KA3
KB3
KA KB
Ts
1 nC Cr VC1k =2IL1k
h2 11
Ts
Fig. 3 Ideal relevant waveforms of the new ZVS PWM
buck boost inverter Fig. 4a shows the voltage conversion ratio Vok/Vin for
different values of fs/fr at nC 0.15 and nL 1/3, as a
function of the duty ratio for this new ZVS PWM buck
inverter. The body diodes of switches S1 , S2 , S3 and S4 are boost inverter. Because the relationship of duty-cycle
naturally turned on at ZVS. The output loop of the inverter against output voltage is nonlinear, the output voltage wave-
starts in a freewheeling state. form of the proposed inverter has some distortion. The com-
After Stage 9, the circuit operation returns to the first parison between the simulated waveform of using the
stage. Resonant voltage vCr1(t) is equal to zero, resonant SPWM technique and the voltage conversion characteristics
voltage vCr2(t) is equal to VC1k and resonant currents iLr1(t) of (2) with the pure sinusoidal one is shown in Fig. 4b. And
and iLr2(t) are also equal to zero. Thus, the assumption the error waveform between them is shown in Fig. 4c. The
previously made is proven to be valid. controller of proposed inverter is constructed in Fig. 5a. It
consists a sinusoidal generator, an error amplifier, a com-
2.2 Output characteristics pensator network, a rectifier, a pulse-width modulator and
a control logic circuit. The SPWM technique is used to
In steady-state operation, the integral of inductor voltage regulate the system dynamics. The error amplifier is necess-
vL1k over one switching period must be zero. Thus ary to compare the sampled-out signal with the reference
from the sinewave generator. The output signal of error
Ts amplifier is rectified and then a controlled voltage from
vL1k dt 0 1 the error amplifier drives the pulse-width modulator to gen-
0
erate a pulse train, which is prescribed to have a constant
period with a variable duty ratio to gate the power switch.
1 After the pulse-width modulator and control logic circuit,
VC1k V 2
1
Dk h1 in the gating signals for S1 , S2 , S3 , S4 , Sa1 and Sa2 can be
obtained.
where
2.3 Commutation analysis
Lr IL1k =VC1k nL =1 nL p=2vr
KA2
KB2 =KA3
KB3
KA KB In order to achieve soft commutation at ZVS for the active
h1 3 switches, for the described operation mode, the following
Ts
inequalities should be satisfied
Cr2 Cr2
nC ; 4 nC ,1 12
Cr1 Cr1

Lr2 Lr2
nL ; 5 nL ,1 13
Lr1 Lr1

390 IET Electr. Power Appl., Vol. 1, No. 3, May 2007

 ( r
nC nL v t nC

1 Cr1 2
nC=0.15, nL=1/3 fs
= 0.15
Dt3 ; t3
t2 tan sin
1
fr vr Zo iLr1 t2 nL
fs
= 0.25
fr 9
Vok fs
>
fr
= 0.35
IL1k
iLr2 t2 =
Vin fs
= 0.45  q 17
iL t2 2 nC =nL vC 1 t2 =Zo 2 >
fr
fs
= 0.55
;
fr r1 r
fs
fr
= 0.65 ( r
nC nL vC t2 nC
Dt4 ; t4
t3 tan
1 r1 sin
1
Duty Ratio Dk vr Zo iLr1 t2 nL
a
200
9
no feedback >
=
150 compensate iLr2 t2
output waveform  q
Dt3 18
iLr1 t2 2 nC =nL vCr 1 t2 =Zo 2 >
100
vo(t)
sinusoid ;
(V) 50
waveform
0

-50
and this time interval must be less than the minimum con-
-100
duction time of the inverter
-150 Dton;Sa2  Dmin Ts 19
-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
b where Dmin is minimum duty-cycle.
200

150
3 Realisation and experimental results
100

verror(t)
50 An example of a 1 kW ZVS PWM buck boost inverter is
(V) 0 designed and realised. The implemented power stage circuit
-50 of the new ZVS PWM buck boost inverter is shown in
-100 Fig. 1c. The design procedure and example of the new
-150
ZVS PWM buck boost inverter is described as follows:
-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
Step 1 Input and output data specification. Vin 100 V
t,sec
c p 1000 W (maximum output
(input voltage); Po,max
power); vo t 110 2 sin2p60t (output voltage);
Fig. 4 Voltage output characteristics fs 80 kHz (switching frequency).
a Theoretical voltage conversion characteristics for the new ZVS Step 2 Calculation of the resonant parameters. In order to
PWM buck boost inverter, nC 0.15, nL 1/3 minimise the influence of the resonant parameters and to
b Simulated waveform of using the SPWM technique and the voltage achieve easily soft commutation at ZCS for both active
conversion characteristics compared with the pure sinusoidal one
c Error voltage verror t of b
switches, we selected the data fs/fr 0.35, Zo 40,
nC 0.15 and nL 1/3. Thus, we can obtain the resonant
angular frequency as follows
Time interval Dton;Sa2 to turn on switch Sa2 is governed by
1
vr p 2pfr 2pfs =0:35 1:436  106 20
Dton;Sa2 Dt1 Dt2 Dt3 Dt4 Lr1 Cr1
(    
1 Zo IL1k nL p KA2
KB2 and
s
vr Vok 1nL 2 KA3
KB3
KA KB
Lr1
r Zo 40 21
vC t2 nC Cr1
nC nL tan
1 r1
Zo iLr1 t2 nL
Thus, expression (21) divided by (20) leads to
)
iLr2 t2
nC nL sin
1 q Lr1 27:9  10
6 22
iLr1 t2 2 nC =nL vCr1 t2 =Zo 2
To make the phenomenon of the ZVS clearer, we use
14 Lr1 30 H and Lr2 nLLr1 10 H. Substituting
Lr1 30 H into (20), we have Cr1 16.16 nF, choose
Cr1 16.4 nF, and Cr2 nCCr1 2.42 nF, choose
where Cr2 2.2 nF.
Step 3 Calculation of the maximum duty ratio Dmax .The
voltage conversion ratio is Vo,max/Vin 1.55. We can
Lr IL1 k ILf k  nL  obtain duty ratio Dmax 0.63 from Fig. 4.
Dt1 ; t1
t0 15 Step 4 Determination of input inductor L1 and capacitor
VC1 k 1 nL
C1 . Boost inductance value L1 and filter capacitance C1 to
minimise the ripple voltage across capacitor are specified
  as Lin 1 mH, C1 940 F.
p KA2
KB2
Dt2 ; t2
t1 16 Step 5 Determination of the output filter components of
2vr KA3
KB3
KA KB the inverter. Output filter inductor Lf and capacitor Cf to
IET Electr. Power Appl., Vol. 1, No. 3, May 2007 391
 L1 C1 p

Da1
S2 S1 Lf
Sa2 A
Vin Cf ZL
Cr2
Sa1
Lr1 Lr2 B
Da2

Cr1 Da3 S4 S3
n
To MOSFETs S1, S2, S3, S4, Sa1, Sa2
Controller
Control Logic Circuit and Drive Circuit

C1

R2 C2 R3 C3

R1
_
Pulse-Width
Rectifier
Modulator

+
Sine-Wave
Generator

Vcc

Vcc 1K 2nF

47K 150 4 8 14 3 2 1 Vcc

6 4047 10 0.1u 0.1u

2 3 12 11 8
14
to Sa1
5 7 9 12
47K
1 TL494
15 Vcc
6 5 4 7 13 16 9 10
Vcc 0.1u 0.1u

to Sa2
1K 2nF
4 8 14 3 2 1
20K Vcc
Vcc
10K 20K 10
6 4047
10K 10K 0.1u 0.1u
+ + 5 7 9 12
to S1
_ _

Vcc
C1
+ Vcc 0.1u 0.1u
vo R3 C3 R2 C2 _
to S2
R1
_
+ Vcc

Vcc Vcc 0.1u 0.1u

sine-wave reference
signal 1K 2nF to S3
4 8 14 3 2 1 Vcc
Vcc
6 4047 10
0.1u 0.1u
5 7 9 12
to S4

Fig. 5 Controller of the proposed inverter

a Control system of the proposed inverter
b Detail circuit of the controller

minimise the undesired harmonics of the output AC voltage Thus, the MOSFETs IRFBA22N50A is used as power
are specified as Lf 1 mH, Cf 4.7 mF. switch Sa1 . The maximum current through switch Sa2 can
Step 6 Selection of power switch and diode. From the be found as follow
circuit operation analysis, the maximum current through
switch Sa1 can be found as follows Po;max Po;max p VC1 ;max 1000
iSa2 ;max  2
Vin Vo;rms Zo 100
Po;max Po;max p 1000 1000 1000 p 246
iSa1 ;max  2  2 29 A 25
Vin Vo;rms 100 110 110 40
p
 2 22:856 A 23 and
vS VC1 ;max Vo;max =Dmax 246 V 26
a2 ;max
and
Thus, the MOSFETs IRFPS30N60K is used as power
vSa1 ;max VC1 ;max Vo;max =Dmax 246 V 24 switch Sa2 . The maximum current through switches S1 ,
392 IET Electr. Power Appl., Vol. 1, No. 3, May 2007
Fig. 6 Commutation in switches
a Sa1 b Sa2
c S1 d S2
e S3 f S4
(VSa1 , VSa2: 250 V/div; ISa1 , ISa2: 10 A/div, time: 1 ms. VS1 , VS2 , VS3 ,
VS4: 250 V/div; IS1 , IS2 , IS3 , IS4: 5 A/div, time:1 ms.)
Fig. 8 Experimental results of vo(t) and io(t) and their spectra
a With resistive load (RL 48 V)
S2 , S3 , and S4 can be found as follows b With inductive load (RL 100 V, LL 0.26 H) and
Po;max c Rectifier with RLC load (RL 48 V, LL 1 mH and
iS1 ;max iS2 ;max iS3 ;max iS4 ;max CL 1740 mF), (Vo: 100 V/div; Io: 5 A/div; time:2 ms/div)
Vo;rms
p 1000 p switches Da1 , Da2 and Da3 can be found as follows
 2  2 12:856 A 27
110
and iD1 ;max iD2 ;max iD3 ;max iSa2 ;max 29 A 29

vS1 ;max vS2 ;max vS3 ;max vS4 ;max VC1 ;max 246 V 28 and
Thus, the MOSFETs IRFP15N60L is used as power
switches S1 , S2 , S3 and S4 . The maximum current through vD1 ;max vD2 ;max vD3 ;max vSa2 ;max 246V 30

Fig. 7 Experimental results of voltage conversion for input and output voltage
a Input voltage Vin and output voltage vo . Vin , vo: 50 V/div, time: 2 ms
b Experimental results of voltage conversion characteristic

IET Electr. Power Appl., Vol. 1, No. 3, May 2007 393

 91

90

Proposed ZVS-PWM inverter

89

Efficiency (%)
88

87 Hard switching boost dc/dc converter

+
+
86 Hard switching inverter

85

84
100 200 300 400 500 600 700 800 900 1000
Output power (W)
a
Experimental efficiency (%)

Output power (W) 100 200 300 400 500 600 700 800 900 1000
Proposed ZVSPWM inverter 86.5 88.5 88.9 89.5 90 90.1 90.2 90.4 90.5 90.5
Hard switching boost DC/DC
converter
87 88 87.4 86 85.5 85 84.8 84.6 84.4 84.3
+
Hard switching inverter
b

Fig. 9 Experimental efficiency comparison of the new ZVSPWM buckboost inverter and combination circuit of the conventional
hard-switching PWM boost DC/DC converter and PWM inverter
a Curve
b Table

Thus, the 30CPU04 is used as power diodes Da1 , Da2
and Da3 .
The commutation phenomenon in switches Sa1 , Sa2 , S1 ,
S2 , S3 and S4 is measured in Fig. 6. The experimental
results shown in Fig. 6 demonstrate that ZVS is achieved
at constant frequency for the switches (Sa1 , Sa2 , S1 , S2 , S3
and S4). Therefore the switching energy losses for this
new ZVS PWM buck boost inverter are practically zero.
The waveforms of input voltage and output voltage are
shown in Fig. 7a and the experimental results of voltage
conversion characteristic are shown in Fig. 7b. From these
experimental results, it is sure that the output voltage of pro-
posed inverter can be higher or lower than the input DC
voltage. In order to assess the dynamic performance of
the presented inverter, three kinds of loads (resistive R,
inductive RL and rectifier with RLC) are examined in
Fig. 8, in which the measured total harmonic distortions
for the mentioned loads are given as 1.91% for the R
load, 2.63% for the RL load and 5.25% for the rectifier
with the RLC load. The efficiency of the presented
ZVS PWM buck-boost inverter in comparison with the
combination circuit of the conventional PWM boost DC/
DC converter and PWM inverter is also measured in
Fig. 9. The experimentally obtained efficiency from the
new ZVS PWM buck boost inverter is equal to 90.5%
and from the combination circuit is equal to 84.5%, for
rated load.
4 Conclusion
This paper presents a new single-stage ZVS PWM buck
boost inverter with a simple and compact configuration. The
operation of the proposed inverter was analysed. All
semiconductor devices in the proposed ZVS PWM
buck boost inverter operate at ZVS turn on and turn off
except that switch Sa2 operates at ZCS turn on and turn
off. The proposed inverter is regulated by the conventional
SPWM technique at constant frequency. Therefore the pro-
posed ZVS PWM inverter can use the PWM and ZVS
techniques. High power efficiency over 90.5% is achieved
under the rated power of 1000 W for proposed ZVS
PWM buck boost inverter. Some experiment results are
in agreement with the theoretical prediction.
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394 IET Electr. Power Appl., Vol. 1, No. 3, May 2007