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Using a Three-Phase Four-Wire

Grid-Interfacing Compensator

Yunwei Li, Student Member, IEEE, D. Mahinda Vilathgamuwa, Senior Member, IEEE, and

Poh Chiang Loh, Member, IEEE

AbstractThis paper presents a three-phase four-wire grid-in- will open and isolate the microgrid. However, when the utility

terfacing power quality compensator for microgrid applications. voltages are not so seriously unbalanced, the separation device

The compensator is proposed for use with each individual dis- will remain closed, subjecting the microgrid to sustained un-

tributed generation (DG) system in the microgrid and consists

of two four-phase-leg inverters (a shunt and a series), optimally balanced voltages at the point of common coupling (PCC), if

controlled to achieve an enhancement of both the quality of no compensating action is taken. Such an unbalance in voltages

power within the microgrid and the quality of currents flowing can cause increased losses in motor loads and abnormal opera-

between the microgrid and the utility system. During utility grid tion of sensitive equipment.

voltage unbalance, the four-phase-leg compensator can compen- An obvious solution is to balance the voltages within the

sate for all the unwanted positive-, negative-, and zero-sequence

voltagecurrent components found within the unbalanced utility. microgrid using some voltage regulation techniques. However,

Specifically, the shunt four-leg inverter is controlled to ensure large unbalanced currents can flow between the unbalanced

balanced voltages within the microgrid and to regulate power utility grid and microgrid due to the very low line impedance in-

sharing among the parallel-connected DG systems. The series terfacing both grids, if only the microgrid voltages are regulated

inverter is controlled complementarily to inject negative- and [1]. This flow of large currents can overstress semiconductor

zero-sequence voltages in series to balance the line currents, while

generating zero real and reactive power. During utility voltage devices within the interfacing inverters and the distribution

sags, the series inverter can also be controlled using a newly lines, and is expected to worsen during utility voltage sags when

proposed fluxcharge current-limiting algorithm to limit the flow the voltage differences between the utility grid and the micro-

of large fault currents between the micro- and utility grids. The grid increase. For low voltage distribution, where microgrids

performance of the proposed compensator has been verified in are usually constructed with a four-wire configuration to supply

simulations and experimentally using a laboratory prototype.

both single-phase and three-phase loads, the problem is further

Index TermsFault current limitation, four-phase-leg in- complicated by the flow of zero-sequence currents through the

verter, microgrid, power quality compensator, sequence volt-

ages/currents. line and neutral conductors.

To mitigate the above-mentioned complications, this paper

proposes a grid-interfacing power quality compensator for

I. I NTRODUCTION three-phase four-wire microgrid applications. The proposed

compensator is to be used with each individual distributed

M ICROGRIDS can generally be viewed as a cluster of

microgenerators connected to the mains utility grid,

usually through some voltage-source-inverter (VSI)-based in-

generator (DG), and it consists of two optimally controlled

four-phase-leg inverters (a shunt and a series as in Fig. 1).

terfaces. Concerning the interfacing of a microgrid to the utility Operating together, the two four-leg inverters can compensate

system, an important area of study is to investigate the impact for all the unwanted positive-, negative-, and zero-sequence

of unbalanced utility grid voltages and utility voltage sags, voltages/currents within the system, enhancing both the quality

which are two most common utility voltage quality problems, of power within the microgrid and the quality of current flowing

on the overall system performance. As a common practice, if between the microgrid and the utility. During utility voltage

the utility grid voltages are seriously unbalanced, a separation sags, the compensator can also be controlled to limit the flow of

device, connected between the microgrid and the mains grid to large fault currents using a newly proposed fluxcharge current-

provide isolation in the event of mains faults as in Fig. 1(a), limiting algorithm. The proposed system has been tested in

simulations and experimentally using a laboratory hardware

prototype. Lastly, to assist readers in identifying objectives of

Paper IPCSD-05-064, presented at the 2004 Industry Applications Society the paper, Table I, summarizing the compensator functionalities

Annual Meeting, Seattle, WA, October 37, and approved for publication in the and control features, is included.

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power

Converter Committee of the IEEE Industry Applications Society. Manuscript

submitted for review October 15, 2004 and released for publication August 26, II. T HREE -P HASE F OUR -W IRE G RID -I NTERFACING

2005.

The authors are with the Center for Advanced Power Electronics, School P OWER Q UALITY C OMPENSATOR

of Electrical and Electronic Engineering, Nanyang Technological University,

Singapore 639798 (e-mail: emahinda@ntu.edu.sg). Fig. 1 shows the general layout of the proposed grid-inter-

Digital Object Identifier 10.1109/TIA.2005.858262 facing power quality compensator. The compensator consists

1708 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

Fig. 1. Proposed microgrid compensator. (a) Overall system structure. (b) Inverter topology.

TABLE I

POWER COMPENSATOR FEATURES AND CONTROL STRUCTURES

of two four-phase-leg inverters, namely inverter A (shunt) and task would require inverter B to carry relatively large current

inverter B (series). The main functions of inverter A are to with a high compensating voltage appearing across it, implying

maintain a set of balanced sensitive load voltages within the that inverter B must have high power rating, too.

microgrid even under unbalanced load and grid voltage con- It is commented that the operational principles of the

ditions, generate and dispatch power, share the power demand compensator presented here are different from those of a

optimally with the other parallel-connected DG systems when unified power quality conditioner (UPQC), which is usually

the microgrid islands, and synchronize the microgrid with the constructed using a shunt and a series three-phase-leg inverter.

utility system at the instant of connection. In addition, being For a UPQC, the series three-leg inverter injects voltages to

connected directly to the microsource, inverter A must have maintain a set of balanced distortion-free voltages at the load

sufficiently high power capacity with rated voltage and head- terminals, while the shunt three-leg inverter injects harmonic

room for current higher than the rated value (in fault conditions) compensating currents into the alternating current (ac) system

in order to continuously condition the routine energy supplied to shape the supply currents drawn by the UPQC-conditioned

by the microsource (similar to most shunt inverter applications loads as balanced sinusoids. In addition, the UPQC is usually

on power systems). On the contrary, the main functions of designed to function with zero real power flow through it during

inverter B are to maintain a set of balanced line currents by in- steady state to minimize the size of the direct current (dc)

troducing negative- and zero-sequence voltages to compensate link energy storage capacitor [2]. These control objectives of a

for the grid voltage unbalance, and to limit the flow of large UPQC are obviously different from those of the proposed four-

fault currents during utility voltage sags. This second control phase-leg compensator, where inverter A is used for voltage

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1709

frame quantities {V , V , V0 }, used as reference voltages for

the voltagecurrent regulation block.

The external power blocks also incorporate synchronization

algorithms for ensuring smooth and safe reconnection of the

micro- and utility grids when the fault is cleared. Synchro-

nization can be achieved by aligning the voltage phasors at

the microgrid and utility ends of the separation device whose

location is indicated in Fig. 1(a), and it can conveniently be im-

plemented by adding two separate proportional and integral (PI)

synchronization regulators to the external real and reactive

power control algorithms [see Fig. 2(a)]. Inputs to these PI

regulators are the magnitude E and phase errors of the

two voltage phasors at both ends of the separation device, and

their outputs are fed to the real and reactive power loops to make

E 0 and 0, ensuring close tracking of the voltage

phasors at both ends of the separation device. As mentioned

earlier, details of these power control algorithms can be found

in an earlier publication [3].

Fig. 2(b) shows the voltagecurrent regulation scheme for

inverter A, which contains an inner filter inductor current con-

trol loop and an outer load voltage control loop. For the outer

voltage loop, the theoretical analysis is first presented in the

synchronous dq0 reference frames to assist in understand-

ing the control principles. The developed voltage controllers are

subsequently converted back to the stationary frame to allow for

Fig. 2. Control scheme for shunt inverter A. (a) Overall control structure.

(b) Voltage control algorithm. easier physical implementation.

As illustrated in Fig. 2(b), the three-phase load voltages are

regulation and power control, and inverter B is used for line first transformed from the stationary abc frame to the sta-

current balancing and fault current limiting, as described earlier. tionary 0 frame using the following quad transformation

Therefore, for the proposed compensator, the development of matrices [4]

an appropriate control algorithm is challenging since existing

UPQC control algorithms are not directly applicable, and most 2

U0 = T0 Uabcn (1)

references on four-phase-leg compensators in the literature are 3

for either a shunt or a series four-leg inverter, but not for both U0 = [U U U0 ]T (2)

used simultaneously. This control development is presented

next in the remaining sections of the paper. Uabcn = [Uan Ubn Ucn Un ]T (3)

1 12 21 0

III. C ONTROL OF S HUNT I NVERTER A

T0 = 0 2

3

23 0 (4)

A. Description of Control Algorithm 1

2 2

1

2 2

1

2 2

23 2

As shown in Fig. 2(a), the control system of shunt inverter where Un is a placeholder quantity, usually chosen to be 0

A contains a voltagecurrent regulation block, and external real [4]. The 0 voltages are subsequently transformed to

and reactive power control blocks. The detailed design of the the forward-rotating positive-sequence synchronous frame

power control blocks has already been presented by Li et al. [3] (indicated with superscript +) and reverse-rotating negative-

and is therefore not duplicated here. Instead, this paper focuses sequence frame (indicated with superscript ) using the

more on the design of the voltagecurrent regulation block of following transformation matrices:

shunt inverter A, after giving an introductory description of the

power control blocks for the sake of completeness. +

T

Udq0 = Ud+ Uq+ U0+ +

= Tdq0 U0 (5)

In brief, the power blocks control real and reactive power

flow, and facilitate power sharing between the paralleled DG cos(t) sin(t) 0

systems when a utility fault occurs and the microgrid islands.

+

Tdq0 = sin(t) cos(t) 0 (6)

This sharing of power is achieved with no physical communica- 0 0 1

tion link between the DG systems by introducing artificial real

= Ud Uq U0 = Tdq0

T

Udq0 U0 (7)

power versus supply frequency and reactive power versus

voltage magnitude droop characteristics into the power loops. cos(t) sin(t) 0

Outputs of the power controllers are the reference frequency ,

Tdq0 = sin(t) cos(t) 0 . (8)

phase , and the positive-sequence voltage magnitude E. These 0 0 1

1710 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

+

Note that the first two rows of T0 , Tdq0 , and Tdq0

resemble the commonly used three-phase abc to

to dq transformation. Equations (1)(8) can therefore be

viewed simply as an extension from the three-phase abc

to to dq transformation with only an independent

zero-sequence row added. It would therefore be convenient to

control the dq voltages independently from the zero-sequence

voltages, as indicated in Fig. 2(b) with the zero-sequence con-

trol path drawn external to the dotted box enclosing the dq

control paths.

To achieve zero steady-state errors when controlling the

positive- and negative-sequence dq voltages, two PI con-

trollers are used along the positive- and negative-sequence dq

control paths. Practically, the implementation of these dq con-

trollers can be computationally inefficient due to the numerous

coordinate frame transformations needed [6]. A more efficient

form of the voltage controllers can be derived by transforming

both the positive- and negative-sequence PI controllers to the

stationary frame using either the state-space or frequency-

domain technique [5], [6]. Performing this inverse transforma-

tion with kp+ = kp = kp and ki+ = ki = ki , the frame

voltage controllers can be expressed as

2kp + s22k+

is

2 0

. (9)

0 2kp + s22k+

is

2

duce an infinite gain at the positive (50 Hz) and negative

(50 Hz) fundamental frequencies to force the positive- and

negative-sequence voltage errors to zero [see Fig. 3(a) for an

example bode plot of (9) using a positive resonant frequency

of 50 Hz], and can conveniently be implemented in the sta-

tionary frame with minimum computational requirements

[6]. The same P + resonant compensator with the resonant

frequency set at 50 Hz can also be used for controlling the zero-

sequence voltage, again with zero steady-state error, as shown Fig. 3. Bode plots of P + resonant compensators using (a) (9) and (b) (15)

in Fig. 2(b). Note that for this work, the resonant frequency is with kP = 1, ki = 20, = 314 rad/s, and cut = 10 rad/s.

set by inverter A real power versus supply frequency droop

controller and not the utility grid frequency. A mechanism to constant gain and the closed-loop transfer functions of inverter

track the grid frequency for determining resonant condition (or A control scheme can be derived in the frame as

transformation phase for synchronous PI implementation) is

2kp s2 + 2ki s + 2 2 kp

therefore not required. V = V (10)

The outputs of the individual voltage controllers when added Cs3 + 2kp s2 + ( 2 C + 2ki )s + 2 2 kp

together give the demanded reference currents I , I , and

and along the zero-sequence axis as

I0 for the inner filter inductor current loop. This inner loop

is implemented using only proportional controllers with peak

kp0 s2 + 2ki0 s + 2 kp0

current limiting in the stationary 0 frame as any steady- V = V . (11)

state error in this loop would not affect the outer voltage loop Cs3 + kp0 s2 + ( 2 C + 2ki0 )s + 2 kp0 0

accuracy substantially. The outputs of the current controllers

are then transformed back to the abc frame and sent to Both (10) and (11) are third-order transfer functions, whose

a four-phase-leg pulsewidth-modulation (PWM) modulator for transient and tracking performance can be improved by increas-

switching shunt inverter A. ing the proportional gains {kp , kp0 } and resonant gains {ki , ki0 },

respectively, at the expense of stability. For this work, a tradeoff

is obtained by choosing 2kp = kp0 = 0.1 and ki = ki0 = 100

B. Closed-Loop Transfer Functions

(other system parameters are listed in Table II), which gives

As far as the dynamics of the outer voltage loop is concerned, the same bode plot in Fig. 4 for both (10) and (11). This figure

the inner current loop is considered to be having fast dynamic generally indicates good fundamental compensation and rapid

response. The inner loop can therefore be represented as a high-frequency attenuation of the controller with an infinite

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1711

TABLE II

SYSTEM PARAMETERS

Fig. 5. Control scheme for series inverter B. (a) General representation.

gain margin, 61.9 phase margin, 3.1-ms step response time, (b) Outer current loop in the negative synchronous frame. (c) Inner

voltage loop.

and 22.5% overshoot.

line currents are first transformed to the negative synchronous

IV. C ONTROL OF S ERIES I NVERTER B D URING dq0 reference frame using (1) and (7), and regulated with

U TILITY V OLTAGE U NBALANCE zero reference values using PI controllers for the negative-

sequence dq currents and a resonant controller for the zero-

A. Description of Control Algorithm

sequence component [see Fig. 5(b)]. (Note that the

The circuit connection of series inverter B is shown in resonant controllers described in Section III compensate for

Fig. 1(a), where a four-leg inverter is again adopted for the both positive- and negative-sequence components and therefore

control of zero-sequence component. The main function of the cannot be used here for solely compensating the negative-

series inverter is to maintain a set of balanced line currents; sequence component. In addition, note the use of a nonideal

i.e., to force the negative- and zero-sequence currents to zero in resonant controller along the zero-sequence control path, which

the three-phase four-wire system. Note that this inverter is not is particularly needed for this work due to experimental con-

designed to control the positive-sequence currents, which are straints described in the next subsection.)

already (directly) regulated by shunt inverter A (in the power Before feeding into the PI controllers, the current signals

control loop). should be filtered to remove positive-sequence currents, which

Fig. 5(a) shows the control scheme for series inverter B, appear as ac signals at twice the fundamental frequency, leaving

where an inner voltage loop is shown embedded within an only dc negative-sequence currents for compensation. This

outer current loop. The outer current loop (also referred to as filtering is needed for enhancing the robustness of the control

the reference voltage generator) functions to generate reference loop and is performed by averaging the dq currents over half a

voltages for the inner voltage loop using the negative- and fundamental cycle in the negative synchronous frame [8]. Quite

zero-sequence line currents as inputs. As seen, the measured obviously, a degradation associated with this half fundamental

1712 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

cycle filtering would be the overall poorer controller transient To confirm the robustness of the inverter B control scheme, a

response. Also shown in Fig. 5(b) are measures taken to de- typical distribution system where the line reactance is either

couple the d- and q-control paths (indicated by dotted lines the same or smaller than the line resistance [7] is consid-

in the figure) to arrive at three decoupled d-, q-, and 0-axis ered. With the series transformer leakage impedance lumped

control paths, which can be tuned independently. The outputs together with the line impedance for simplicity, and even with

of this outer reference voltage generator, consisting only of an onerous condition of XLine = (2f )LLine = 2RLine for

negative- and zero-sequence components, are then transformed this distribution system, the stability condition (13) becomes

back to the 0 frame and fed into the inner voltage Lf (2ki RLine / 2 f 2 ) > 0, which can easily be met. Con-

control loop. sequently, (14) can also be met since the term in (14) is

The block representation of the inner voltage loop is shown now minimized by having a relatively larger denominator than

in Fig. 5(c), where P + resonant controllers are used along the numerator (the numerator is usually small due to the presence

0 control paths. The use of P + resonant controllers in of a microfarad capacitive term Cf ).

the inner control loop will force the filtered capacitor voltages Once the design of the inner voltage loop is completed, the

VC of the series inverter to track the demanded negative- next step is to design the outer reference voltage generator

and zero-sequence reference voltages VC with zero steady- in the negative synchronous reference frame. In the negative

state errors and eliminate any positive-sequence component synchronous dq frame, positive-sequence currents, which

since its reference value is kept at zero for the series inverter. appear as ac signals at twice the fundamental frequency, should

The series inverter therefore injects only negative- and zero- be removed using half fundamental cycle filtering [8] to

sequence voltages into the system to maintain a set of balanced enhance the robustness of the control loop. Another consider-

line currents with no real and reactive power generation (or ation is to identify an alternative nonideal resonant controller

absorption) in the steady state. [see Fig. 5(b)] for use along the zero-sequence control path,

Note that an inner filter inductor current loop can be added whose transfer function is expressed as [6]

to the voltage control loop to give a better dynamic response.

However, due to the slow response of the outer reference volt-

age generation loop, a single inner voltage loop is considered 2ki0 cut s

kp0 + (15)

sufficient, and this loop can reasonably be represented by a s2 + 2cut s + 2

unity gain when designing the control scheme.

where cut represents the low-frequency cutoff. An example

B. Closed-Loop Transfer Functions bode plot of (15) is given in Fig. 3(b), which obviously shows

As a common practice, the design of the proposed control a wider resonant peak with a large finite gain, as compared to

algorithm for the series inverter begins with the inner voltage that of (9) given in Fig. 3(a). Equation (15) is therefore less

loop in the 0 frame. Analyzing Fig. 5(c) with Kinv = sensitive to frequency fluctuation, and the steady-state error

2/Vdc , the closed-loop transfer function of the inner voltage would be still kept relatively small. This nonideal controller

loop can be derived as in (12), shown at the bottom of the should generally be used in cases with resonant frequency

page, where RLine and LLine , which normally represent line variations, and it is particularly applicable to the experimental

resistance and inductance, are here lumped together with the series inverter implemented in Section VIII. In that prototype,

series transformer winding parameters for convenience. When the inverter neutral phase-leg is asynchronously switched by

performing zero-sequence analysis, neutral line parameters are an external analog comparator and triangular signal genera-

also lumped into RLine and LLine . tor due to the shortage of synchronized PWM channels on

To maintain stability, the Rouths stability criteria of (13) and the dSPACE DS1103 controller card. This causes slight fre-

(14) must be met for the inner voltage loop quency variation in the neutral line current waveform, whose

effect is nullified by the 0 transformation matrix in

2ki L2Line (4) along the outer negative-sequence PI control path. How-

Lf > 0 (13) ever, along the 0-axis control path, its effect is not nullified,

RLine

2kp RLine + 2ki LLine + RLine + Lf Cf RLine 2 and, therefore, the nonideal P + resonant compensator with a

wider resonant bandwidth is needed for reducing the system

2 sensitivity level.

2ki Lf Cf RLine + L2f Cf RLine 2

2k L2Line

> 0. (14) Incorporating these fine-tuning schemes, the final closed-

Lf Ri Line loop transfer functions of the proposed control algorithm can

GVcl = kp LLine s3 + (2kp RLine + 2ki LLine )s2 + (2kp 2 LLine + 2ki RLine )s + 2kp 2 RLine

Lf Cf LLine s5 + Lf Cf RLine s4 + (Lf + LLine + 2kp LLine + Lf Cf LLine 2 )s3 + (2kp RLine + 2ki LLine

+ RLine + Lf Cf RLine 2 )s2 + (2kp + 1) 2 LLine + 2 Lf + 2ki RLine s + (2kp + 1) 2 RLine (12)

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1713

Maintaining V D constant, however, gives rise to a large voltage

phasor (VD V sag ) across series inverter B and the distribution

Fig. 6. Open-loop Bode plot of zero-sequence control path.

line, resulting in large fault currents flowing along the line. If

these fault currents are allowed to flow through the line until

be written as (16) in the negative dq frame and (17) (shown at clearance of the sag or opening of the electromechanical circuit

the bottom of the page) along the 0-axis breaker, there is a risk of damaging semiconductor devices in

the inverters.

kp s + ki A possible ride-through scheme for the above-mentioned

GIcl = . (16)

LLine s2 + (RLine + kp )s + ki complications would be to control series inverter B to act as

a virtual current-limiting inductor L0 immediately after the

Using (16) and setting kp = 1.5 and ki = 80, the outer sensing of a voltage sag. Sensing of voltage sag is indirectly

control loop gain margin, phase margin, and settling time are done here by measuring the local three-phase line currents since

specified as infinity, 114 , and 0.2 s, respectively, with the long in actual cases, the PCC can be located far away from the

settling time inherently caused by the half fundamental cycle power compensator, and, therefore, its voltages are inaccessible

response time needed for outer loop filtering. For the 0-axis, to the compensator. Upon the instantaneous current value of a

setting kp0 = 16, ki0 = 200, and cut = 10 rad/s, and using the phase exceeding a specified threshold IT , inverter B is invoked

open-loop bode plot in Fig. 6 for the zero-sequence control path to inject a large virtual inductance L0 in series with the line

with the neutral line impedance included (see Table II for the impedance {RLine , LLine } to limit the current flowing along the

line, maintaining V E V sag . By keeping V E V sag , smooth

neutral impedance parameters), the gain and phase margins are

set to infinity and 89.7 , respectively. Together, these selected recovery from a voltage sag can also be ensured by simply

sensing V E , which will rise with V sag back to its nominal

control parameters ensure the stability of series inverter B.

value. The fault current limiting action of inverter B can then

be inhibited and the power algorithms of inverter A can be

V. C ONTROL OF C OMPENSATOR D URING U TILITY reenabled.

V OLTAGE S AGS (F AULT C URRENT L IMITATION ) One way of controlling inverter B as a virtual inductor

is to use the flux-model control concept reported in [9] and

The control schemes, presented in the earlier two sections, [10]. In passing, it is commented that the predictive flux-

regulate the compensator well during normal operating condi- model control presented in [9] and [10] is highly sensitive to

tions, but not during utility voltage sags. Referring to Fig. 7, system parameter variations, which is a common feature for

sag drops below its nominal value, and

at the start of a sag, V most predictive schemes. An alternative robust fluxcharge-

shunt inverter A should now disable its external power control model control, with an outer flux-model and an inner charge-

algorithms and set its voltage references ({V , V } in Fig. 2) to model loop, is therefore proposed in this paper for controlling

some appropriate values according to the load sensitivity level. inverter B, as shown in Fig. 7. The control variable used for the

As an example, consider the (ideal) case where {V , V } and, outer flux

model is the inverter filtered terminal flux, defined

hence, the shunt inverter terminal voltage phasor V D , are kept as = VC dt, where VC is the filter capacitor voltage of

constant at their nominal values with their phase-angles locked the series inverter. This flux variable is compared against a

kp0 s2 + 2cut kp0 + ki0 s + 2 kp0

GIcl = (17)

LLine s3 + 2cut LLine + RLine + kp0 s2 + 2 LLine + 2cut RLine + 2cut kp0 + 2cut ki0 )s + 2 (RLine + kp0

1714 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

was implemented by sensing the capacitor voltage, and Q can

then be calculated directly from VC (noting that Q = iC dt =

Cf VC ) without requiring additional current sensors. Although

sharing common control principles, the fluxcharge control

does have an implementation advantage over voltagecurrent

control. The additional integration in fluxcharge control would

allow its outer loop flux reference to be easily computed by

multiplying L0 and iLine without differentiation (differentiation

of iLine is needed for voltagecurrent control). The resulting

flux reference is therefore more accurately calculated (without

phase delay and noise amplification associated with differen-

tiation), and the fluxcharge-controlled series inverter would

emulate virtual inductor L0 more closely.

The calculated charge error is then fed to the charge regulator

with a designed transfer function of kTd s/(1 + (Td s/N )).

Note from this expression that a derivative term is found in

its numerator. Intuitively, this derivative term neutralizes the

effects of voltage and current integrations at the inputs of

the fluxcharge model, resulting in the proposed algorithm

having the same regulation performance as the multiloop

voltagecurrent feedback control. This similarity in perfor-

mance is confirmed by plotting the closed-loop response of

the charge model in Fig. 8(a) with kTd = 1000 and Td /N =

0.00002. As anticipated, the resulting bode plots have band-

pass characteristics with a near-unity gain at the fundamental

frequency, similar to those of an inner capacitor current loop

(example bode plots of an inner capacitor current loop can be

found in [11]).

Lastly, to confirm the stability of the proposed fluxcharge-

model control, its open-loop Bode plots are plotted in Fig. 8(b)

with 2kp = 0.08 and 2ki = 160. The plotted figure clearly

shows the system exhibiting good performance at the fun-

damental frequency with all high-frequency switching com-

ponents effectively attenuated. (Closed-loop response of the

Fig. 8. Bode plots of (a) closed charge loop and (b) open flux loop. fluxcharge-model control is very similar to that of shunt

inverter A in Fig. 4 and is therefore not explicitly shown.)

VI. S IMULATION R ESULTS

current and the negative sign is to indicate that iLine is drawn

flowing out of the series inverter in this paper. The flux error Simulation results using Matlab/Simulink are provided to

is then fed to the flux regulator, implemented using the P + verify the effectiveness of the proposed system. The system

resonant compensator given in (9). parameters used for simulation are given in Table II. These

It can be shown through classical control analysis that this represent typical distribution system parameters as given in

single flux model cannot damp out the resonant peak of the [7]. Fig. 9(a) shows the voltage profile used for simulation

inductancecapacitance (LC) filter connected to the output of where the grid voltages are initially balanced. From t = 1.2 s

inverter B (analytical details are not shown here due to space onwards, negative sequence voltages of 0.1 per unit (p.u.) and

limitation). To stabilize the system, an inner charge model is zero-sequence voltages of 0.1 p.u. are added to the original

therefore

added to force the filter capacitor charge, defined as balanced voltages.

Q = iC dt = Cf VC , where iC and Cf are the current through With the proposed grid-interfacing compensator added,

and capacitance of the filter capacitor, to track the reference Fig. 9(b) and (c) shows that the sensitive load voltages in

charge output Qref of the flux regulator. the microgrid are kept well balanced even under unbalanced

Intuitively, the presented fluxcharge model can be derived utility voltage conditions. This clearly verifies the performance

from the voltagecurrent control presented in Section III-A of shunt inverter A in maintaining good power quality within

for shunt inverter A by integrating the voltage and current the microgrid. Fig. 10(a) and (b) shows the extremely unbal-

variables. The minor difference is that the capacitor current is anced line currents under grid voltage unbalance and without

to be integrated for the fluxcharge model rather than the filter the functioning of series inverter B, which can cause system

inductor current. Integrating the capacitor current would also complications, as described in Section I. By operating series

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1715

Fig. 11. Simulated filtered voltages generated by series inverter B. (a) abc

Fig. 9. Simulated waveforms of (a) mains grid voltages, (b) abc frame frame. (b) 0 frame (zoomed-in view in the steady state).

sensitive load voltages in the microgrid, and (c) 0 frame sensitive load

voltages in the microgrid.

Fig. 12. Simulated line currents with series inverter B. (a) abc frame.

(b) Negative dq0 frame.

Fig. 10. Simulated line currents without series inverter B. (a) abc frame.

(b) Negative dq0 frame.

as illustrated in Figs. 11 and 12. Fig. 11(a) shows the filtered

voltages [VCan , VCbn , and VCcn ; see Fig. 1(a)] generated by

series inverter B during the transient period of inverter B acti-

vation (from 1.15 to 1.5 s), while Fig. 11(b) shows the zoomed-

in view of the voltages in steady state (from 1.9 s onwards),

which clearly show the presence of only negative- and zero-

sequence components. The performance of series inverter B

is further verified by observing the line currents shown in

Fig. 12(a) and (b), where the initial unbalanced line currents

become balanced again after 0.2 s later. This 0.2-s time lapse

is anticipated due to the half fundamental cycle averaging

process used in inverter B outer control loop, as described in

Section IV-B.

Fig. 13(a)(d) shows the power generated by the two invert-

ers. As illustrated in these figures, shunt inverter A dispatches a Fig. 13. Simulated waveforms of (a) real power supplied by shunt inverter A,

constant real power of 300 W and a reactive power of 160 Var (b) reactive power supplied by shunt inverter A, (c) real power supplied by

series inverter B, and (d) reactive power supplied by series inverter B.

in steady state, while series inverter B constantly maintains zero

real and reactive power output. The zero power output of series

inverter B is expected since it injects only negative- and zero- The current-limiting action of the compensator is also con-

sequence voltages into a system where only positive-sequence firmed by simulating an unbalanced utility voltage sag (VGa =

line currents flow. 32 44.7 , VGb = 66.4 170 , and VGc = 54.5 38.6 )

1716 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

Fig. 14. Simulated waveforms of (a) mains grid voltages and (b) abc

frame sensitive load voltages in the microgrid.

Fig. 16. Simulated waveforms of (a) real power supplied by shunt inverter A,

(b) reactive power supplied by shunt inverter A, (c) real power supplied by

series inverter B, and (d) reactive power supplied by series inverter B.

confirmed in Fig. 16(c), series inverter B absorbs no real active

power since it acts as a fictitious inductor during the sag period.

To verify the performance of the proposed compensator

experimentally, a hardware prototype that has the same system

parameters as in the simulation has been built in the laboratory

(Table II). For the experimental system, a stiff programmable ac

source connected to a resistanceinductance (RL) load is used

to represent the utility grid and is connected to an emulated mi-

Fig. 15. Simulated waveforms of (a) abc frame voltages injected by series crogrid through a three-phase back-to-back silicon-controlled

inverter B and (b) abc frame line currents.

rectifier (SCR) isolation switch. The microgrid consists of the

proposed compensator [a shunt four-leg insulated gate bipolar

at t = 1.2 s in Fig. 14(a). From the load viewpoint, shunt transistor (IGBT) inverter and a series four-leg IGBT inverter

inverter A should ideally maintain the microgrid voltages at with an injection transformer] and a connected RL load. The

their nominal values (power control algorithms of inverter A compensator is controlled using a dSPACE DS1103 controller

are disabled during the sag, as mentioned earlier). This ideal card with a relatively low sampling frequency fsa of 5 kHz

case, however, does not give the worst scenario for performance used due to the long computational time needed for control-

evaluation of the compensator since it would mean a step ling two inverters simultaneously and the use of Simulink

voltage disturbance only on the utility side of the compensator. auto-code generation without optimization. (Note that the in-

An alternative case where the shunt inverter regulates its volt- verter PWM pulses are generated by embedded peripherals

ages at 90% of nominal is therefore assumed here to test the in the slave TMS320F240 processor mounted on the DS1103

compensator performance when voltage steps are introduced on card. The inverter switching frequency fsw can thus be set at

both its utility grid and microgrid sides while still drawing high 10 kHz even though the sampling frequency of the main

line currents. Fig. 14(b) shows the corresponding simulated DS1103 processor is only 5 kHz.) According to digital con-

waveforms for inverter A, where, as anticipated, the microgrid trol theory, an immediate impact of using a lower sampling

voltages are maintained at 90% of their desired nominal values frequency would then be the poorer experimental response as

during the sag. compared to its simulated counterpart (this has been verified

With the proposed fluxcharge algorithm implemented, the in simulation, but the simulated waveforms with distortions are

series inverter now acts like a large virtual inductor connected not shown here due to space limitation).

in series with the distribution feeder, limiting the line currents To ensure proper starting of the experimental system, the

to a specified peak value of 6 A. The voltages across this utility grid and the microgrid are powered up separately. After

inserted virtual inductor and the limited line currents are shown synchronizing the voltages at both ends of the SCR switch,

in Fig. 15(a) and (b), respectively. Lastly, Fig. 16(a) and (b) the switch is closed to connect the micro- and utility grids,

shows the increase in real and reactive power supplied by shunt allowing the system to transit smoothly into the grid-connected

inverter A during the sag, while Fig. 16(c) and (d) shows the mode of operation. Fig. 17(a)(c) shows the utility voltages and

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1717

Fig. 19. Experimental line currents with series inverter B. (a) abc frame.

Fig. 17. Experimental waveforms of (a) mains grid voltages, (b) abc (b) Negative dq0 frame.

frame sensitive load voltages in the microgrid, and (c) 0 frame sensitive

load voltages in the microgrid.

(a) abc frame. (b) 0 frame (zoomed-in view in the steady state). Fig. 20. Experimental waveforms of (a) real power supplied by shunt inverter

A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by

series inverter B, and (d) reactive power supplied by series inverter B.

3.775 s, the utility voltages become unbalanced with 0.1-p.u. The effectiveness of series inverter B in balancing the line

negative-sequence and 0.1-p.u. zero-sequence voltage compo- currents by suppressing negative- and zero-sequence current

nents added. Despite this unbalance in utility voltages, the load components is shown in Fig. 19(a) and (b). These experimental

voltages in the microgrid are kept balanced by controlling shunt waveforms are less damped as compared to their simulated

inverter A. Similarly, to balance the currents flowing between counterparts in Fig. 12, and the cause is identified in simulation

the micro- and utility grids, series inverter B is operated with to be the less accurate half fundamental cycle averaging as-

its injected negative- and zero-sequence voltages shown in sociated with a low experimental sampling rate. Fig. 20(a)(d)

Fig. 18(a) and (b). shows the real and reactive power supplied by the shunt and

As compared to their simulated counterparts in Fig. 11, the series inverters. These figures clearly show the shunt inverter

experimental waveforms in Fig. 18(b) are observed to supplying its specified dispatched power of 300 W and 160 var,

be oscillatory, whereas the 0-axis waveform is (nearly) undis- and the series inverter injecting zero real and reactive power, as

torted. As mentioned earlier, the relatively low experimental anticipated.

sampling frequency (fsa = 5 kHz = 0.5fsw ) used can cause The performance of the compensator during a voltage sag

oscillatory response in the system. Along the control is also verified experimentally by programming the ac source

path for series inverter B (see Section IV-A), this oscillatory to emulate a voltage sag (similar to that used for simulation)

distortion is averaged out by the half fundamental cycle filter at t = 0.807 s, as shown in Fig. 21(a). Fig. 21(b) shows the

and is therefore not eliminated by the PI controllers. On the microgrid load voltages kept constant at 90% of the nominal

other hand, along the 0-axis control path where no filtering is value during the transition from normal to sag condition, while

performed, this distortion is directly compensated and therefore Fig. 22(a) and (b) shows the voltages across and limited line

has lesser effect on the system. currents through series inverter B, which now acts as a large

1718 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6, NOVEMBER/DECEMBER 2005

Fig. 21. Experimental waveforms of (a) mains grid voltages and (b) abc

frame sensitive load voltages in the microgrid.

Fig. 23. Experimental waveforms of (a) real power supplied by shunt inverter

A, (b) reactive power supplied by shunt inverter A, (c) real power supplied by

series inverter B, and (d) reactive power supplied by series inverter B.

power during compensation. During utility voltage sags, the

series inverter can also be controlled to limit the flow of large

fault currents using the proposed fluxcharge control algorithm.

The proposed system has been tested in simulations and exper-

imentally using a laboratory prototype with satisfactory results

obtained for confirming the effectiveness of the compensator.

R EFERENCES

[1] M. Prodanovic and T. C. Green, Control and filter design of three-phase

Fig. 22. Experimental waveforms of (a) abc frame voltages injected by inverters for high power quality grid connection, IEEE Trans. Power

series inverter B and (b) abc frame line currents. Electron., vol. 18, no. 1, pp. 373380, Jan. 2003.

[2] A. Ghosh and G. Ledwich, Power Quality Enhancement Using Custom

virtual inductor. These waveforms again exhibit some transient Power Devices. Boston, MA: Kluwer, 2002.

[3] Y. W. Li, D. M. Vilathgamuwa, and P. C. Loh, Design, analysis and real-

oscillations, which can be eliminated by setting fsa = fsw or time testing of controllers for multi-bus micro-grid system, IEEE Trans.

2fsw (commonly adopted for optimized digital implementa- Power Electron., vol. 19, no. 5, pp. 11951204, Sep. 2004.

tion), as verified in the simulation. Lastly, the corresponding [4] M. J. Ryan, R. W. De Doncker, and R. D. Lorenz, Decoupled control of

a four-leg inverter via a new 4 4 transformation matrix, IEEE Trans.

increase in real and reactive power supplied by shunt inverter Power Electron., vol. 16, no. 5, pp. 694701, Sep. 2001.

A during the sag are shown in Fig. 23(a) and (b), while the real [5] C. B. Jacobina, M. B. de R. Correa, T. M. Oliveiro, A. M. N. Lima, and

and reactive power absorbed by series inverter B are shown in E. R. C. da Silva, Current control of unbalanced electrical systems,

IEEE Trans. Ind. Electron., vol. 48, no. 3, pp. 517525, Jun. 2001.

Fig. 23(c) and (d). Fig. 23(c) again shows the zero real power [6] D. N. Zmood, D. G. Holmes, and G. H. Bode, Frequency-domain analy-

flow to inverter B. sis of three-phase linear current regulators, IEEE Trans. Ind. Appl.,

vol. 37, no. 2, pp. 601610, Mar./Apr. 2001.

[7] P. Heine, A. Lehtonen, and E. Lakervi, Voltage sag analysis taken into

VIII. C ONCLUSION account in distribution network design, in Proc. IEEE Power Tech. Conf.,

Porto, Portugal, 2001.

This paper presents a three-phase four-wire grid-interfacing [8] H. Awad and J. Svensson, Compensation of unbalanced voltage dips

power quality compensator for compensating the two most using vector-controlled static series compensator with LC-filter, in

Conf. Record IEEE Industry Applications Society (IAS) Annu. Meeting,

common voltage quality problems, namely voltage unbalance Pittsburgh, PA, 2002, pp. 904910.

and voltage sag, in a microgrid. During grid voltage unbalance, [9] H. Funato, T. Ishikawa, and K. Kamiyama, Transient response of three

the proposed compensator, using a shunt and a series four- phase variable inductance realized by variable active-passive reactance

(VAPAR), in Proc. IEEE Applied Power Electronics Conf. (APEC),

phase-leg inverter, can enhance both the quality of power within Anaheim, CA, 2001, vol. 2, pp. 12811286.

the microgrid and the quality of currents flowing between the [10] H. Funato, K. Kamiyama, and A. Kawamura, Transient performance of

microgrid and utility system. Functionally, the shunt four-leg power circuit including virtual inductance realized by fully digital con-

trolled variable active-passive reactance (VAPAR), in Proc. IEEE Power

inverter is controlled to maintain a set of balanced distortion- Electronics Specialists Conf. (PESC), Galway, Ireland, 2000, vol. 3,

free voltages within the microgrid and to regulate power sharing pp. 11951200.

among the parallel-connected distributed generation (DG) sys- [11] N. M. Abdel-Rahim and J. E. Quaicoe, Analysis and design of a multi-

ple feedback loop control strategy for single-phase voltage-source UPS

tems. To complement, the series four-leg inverter is controlled inverters, IEEE Trans. Power Electron., vol. 11, no. 4, pp. 532541,

to inject negative- and zero-sequence voltages in series to Jul. 1996.

LI et al.: MICROGRID POWER QUALITY ENHANCEMENT USING A GRID-INTERFACING COMPENSATOR 1719

Yunwei Li (S04) received the B.Eng. degree in elec- Poh Chiang Loh (S01M03) received the B.Eng.

trical engineering from Tianjin University, Tianjin, (Hons.) and M.Eng. degrees from the National Uni-

China, in 2002. He is currently working toward the versity of Singapore, Singapore, in 1998 and 2000,

Ph.D. degree in the School of Electrical and Elec- respectively, and the Ph.D. degree from Monash Uni-

tronic Engineering, Nanyang Technological Univer- versity, Monash, Australia, in 2002, all in electrical

sity, Singapore. engineering.

From February to July 2005, he was with the During the summer of 2001, he was a Visiting

Institute of Energy Technology, Aalborg University, Scholar at the Wisconsin Electric Machine and Pow-

Aalborg, Denmark, as a Visiting Scholar. er Electronics Consortium, University of Wisconsin,

Mr. Li is a member of the IEEE Industry Applica- Madison, where he worked on the synchronized

tions Society (IAS). implementation of cascaded multilevel inverters and

reduced common-mode carrier-based and hysteresis control strategies for

multilevel inverters. From 2002 to 2003, he was a Project Engineer at the

D. Mahinda Vilathgamuwa (S90M93SM99) Defence Science and Technology Agency, Singapore, managing major defense

received the B.Sc. and Ph.D. degrees in electri- infrastructure projects and exploring new technology for intelligent defense

cal engineering from the University of Moratuwa, applications. Since 2003, he has been an Assistant Professor at Nanyang

Katubedda Moratuwa, Sri Lanka, and Cambridge Technological University, Singapore.

University, Cambridge, U.K., in 1985 and 1993,

respectively.

He joined the School of Electrical and Elec-

tronic Engineering, Nanyang Technological Univer-

sity, Singapore, in 1993, as a Lecturer, where he is

now an Associate Professor. His research interests

are power electronic converters, electrical drives, and

power quality. He has published more than 80 research papers in refereed

journals and conference proceedings.

Dr. Vilathgamuwa is the Co-Chairman of The Power Electronics and Drives

Systems Conference 2005 (PEDS05).

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