Putting FPGAs to Work in Software Radio Systems

®

Putting FPGAs to Work in Software Radio Systems
Fifth Edition
Technology FPGA Resources Products Applications Links
by

Rodger H. Hosking
Vice-President & Cofounder of Pentek, Inc.

Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458 Tel: (201) 818-5900 • Fax: (201) 818-5904 Email: info@pentek.com • http://www.pentek.com

Copyright © 2005, 2007, 2008, 2009, 2010 Pentek Inc. Last Updated: June 2010 All rights reserved. Contents of this publication may not be reproduced in any form without written permission. Specifications are subject to change without notice. Pentek, GateFlow, ReadyFow, SystemFlow and RTS are registered trademarks of Pentek, Inc.

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Putting FPGAs to Work in Software Radio Systems

Preface
FPGAs have become an increasingly important resource for software radio systems. Programmable logic technology now offers significant advantages for implementing software radio functions such as DDCs (Digital Downconverters). Over the past few years, the functions associated with DDCs have seen a shift from being delivered in ASICs (Application-Specific ICs) to operating as IP (Intellectual Property) in FPGAs. For many applications, this implementation shift brings advantages that include design flexibility, higher precision processing, higher channel density, lower power, and lower cost per channel. With the advent of each new, higher-performance FPGA family, these benefits continue to increase. This handbook introduces the basics of FPGA technology and its relationship to SDR (Software Defined Radio) systems. A review of Pentek’s GateFlow FPGA Design Resources is followed by a discussion of features and benefits of FPGA-based DDCs. Pentek SDR products that utilize FPGA technology and applications based on such products are also presented. For a more in-depth discussion of SDR systems, the reader is referred to Pentek’s Software Defined Radio Handbook, now in its 7th Edition.

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Putting FPGAs to Work in Software Radio Systems

Technology

Typical Software Radio System

Software Radio Tasks

DDC Digital Downconverter
Analog RF Signal
RF TUNER

Analog IF Signal

A/D CONV

Digital IF Samples

DIGITAL MIXER

LOWPASS FILTER

Digital Baseband Samples

DSP

DIGITAL LOCAL OSC

Figure 1

Figure 2

We begin our discussion with the basic elements of a software radio receiver system. The front end usually contains an analog RF amplifier and often an analog RF translator. This translates the high frequency RF signals down to a frequency that an A/D converter can handle. This is usually below 200 MHz and is often an IF output. The A/D output feeds the DDC (Digital Downconverter) stage, which is typically contained in a monolithic chip which forms the heart of a software radio system. Notice, that after the signal is digitized by the A/D converter, all further operations are performed by digital signal processing hardware.

Here we’ve ranked some of the popular signal processing tasks associated with SDR systems on a two axis graph, with compute Processing Intensity on the vertical axis and Flexibility on the horizontal axis. What we mean by process intensity is the degree of highly-repetitive and rather primitive operations. At the upper left are dedicated functions like A/D converters and DDCs that require specialized hardware structures to complete the operations in real time. ASICs are usually chosen for these functions. Flexibility pertains to the uniqueness or variability of the processing and how likely the function may have to be changed or customized for any specific application. At the lower right are tasks like analysis and decisionmaking which are highly variable and often subjective. Programmable general purpose processors or DSPs are usually chosen for these tasks since these tasks can be easily changed by software. Now let’s temporarily step away from the software radio tasks and take a deeper look at programmable logic devices.

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Putting FPGAs to Work in Software Radio Systems

Technology

Early Roles for FPGAs

Legacy FPGA Design Methodologies

§ Used primarily to replace discrete digital hardware circuitry for:
Ÿ Control logic Ÿ Glue logic Ÿ Registers and gates Ÿ State machines Ÿ Counters and dividers

§ Tools were oriented to hardware engineers
Ÿ Schematic processors Ÿ Boolean processors Ÿ Gates, registers, counters, multipliers

§ Successful designs required high-level hardware engineering skills for:
Ÿ Ÿ Ÿ Ÿ Ÿ Critical paths and propagation delays Pin assignment and pin locking Signal loading and drive capabilities Clock distribution Input signal synchronization and skew analysis

§ Devices were selected by hardware engineers § Programmed functions were seldom changed after the design went into production
Figure 3

Figure 4

As true programmable gate functions became available in the 1970’s, they were used extensively by hardware engineers to replace control logic, registers, gates and state machines which otherwise would have required many discrete, dedicated ICs. Often these programmable logic devices were onetime factory-programmed parts that were soldered down and never changed after the design went into production.

These programmable logic devices were mostly the domain of hardware engineers and the software tools were tailored to meet their needs. You had tools for accepting boolean equations or even schematics to help generate the interconnect pattern for the growing number of gates. Then, programmable logic vendors started offering predefined logic blocks for flip-flops, registers and counters, that gave the engineer a leg up on popular hardware functions. Nevertheless, the hardware engineer was still intimately involved with testing and evaluating the design using the same skills he needed for testing discrete logic designs. He had to worry about propagation delays, loading, clocking and synchronizing—all tricky problems that usually had to be solved the hard way—with oscilloscopes or logic analyzers.

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Putting FPGAs to Work in Software Radio Systems

Technology

FPGAs: New Device Technology
§ § § § § § § § § § § § § § 500+ MHz DSP Slices and Memory Structures Over 1000 dedicated on-chip hardware multipliers On-board GHz Serial Transceivers Partial Reconfigurability Maintains Operation During Changes Switched Fabric Interface Engines Over 330,000 Logic Cells Gigabit Ethernet media access controllers On-chip 405 PowerPC RISC micro-controller cores Memory densities approaching 15 million bits Reduced power with core voltages at 1 volt Silicon geometries to 65 nanometers High-density BGA and flip-chip packaging Over 1200 user I/O pins Configurable logic and I/O interface standards
Figure 5

FPGAs: New Development Tools

§ High Level Design Tools
Ÿ Block Diagram System Generators Ÿ Schematic Processors Ÿ High-level language compilers for VHDL & Verilog Ÿ Advanced simulation tools for modeling speed, propagation delays, skew and board layout Ÿ Faster compilers and simulators save time Ÿ Graphically-oriented debugging tools

§ IP (Intellectual Property) Cores
Ÿ FPGA vendors offer both free and licensed cores Ÿ FPGA vendors promote third party core vendors Ÿ Wide range of IP cores available
Figure 6

It’s virtually impossible to keep up to date on FPGA technology, since new advancements are being made every day. The hottest features are processor cores inside the chip, computation clocks to 500 MHz and above, and lower core voltages to keep power and heat down. About five years ago, dedicated hardware multipliers started appearing and now you’ll find literally hundreds of them on-chip as part of the DSP initiative launched by virtually all FPGA vendors. High memory densities coupled with very flexible memory structures meet a wide range of data flow strategies. Logic slices with the equivalent of over ten million gates result from silicon geometries shrinking down to 0.1 micron. BGA and flip-chip packages provide plenty of I/O pins to support on-board gigabit serial transceivers and other user-configurable system interfaces. New announcements seem to be coming out every day from chip vendors like Xilinx and Altera in a neverending game of outperforming the competition.

To support such powerful devices, new design tools are appearing that now open up FPGAs to both hardware and software engineers. Instead of just accepting logic equations and schematics, these new tools accept entire block diagrams as well as VHDL and Verilog definitions. Choosing the best FPGA vendor often hinges heavily on the quality of the design tools available to support the parts. Excellent simulation and modeling tools help to quickly analyze worst case propagation delays and suggest alternate routing strategies to minimize them within the part. This minimizes some of the tricky timing work for hardware engineers and can save one hours of tedious troubleshooting during design verification and production testing. In the last few years, a new industry of third party IP (Intellectual Property) core vendors now offer thousands of application-specific algorithms. These are ready to drop into the FPGA design process to help beat the time-to-market crunch and to minimize risk.

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FPGAs have significantly invaded the application task space as shown by the center bubble in the task diagram above. However. FPGA memory can now be configured with the design tool to implement just the right structure for tasks that include dual port RAM.com • http://www. these considerations are often secondary to the performance and capabilities of these remarkable devices. These memories can be distributed along the signal path or interspersed with the multipliers and math blocks. As a result. FPGAs now have specialized serial and parallel interfaces to match requirements for high.pentek. Inc. which normally have just a handful of multipliers that must be operated sequentially. • One Park Way. and you can now get over 500 of them on a single FPGA. These advantages may come at the expense of increased power dissipation and increased product costs. shift registers. buses and interface standards § High Speed § Available IP cores optimized for special functions Figure 7 Figure 8 Like ASICs. This is in sharp contrast to programmable DSPs. As we said.Putting FPGAs to Work in Software Radio Systems Technology FPGAs for SDR § Parallel Processing § Hardware Multipliers for DSP Ÿ FPGAs can now have over 500 hardware multipliers FPGAs Bridge the SDR Application Task Space § Flexible Memory Structures Ÿ Dual port RAM. Upper Saddle River. shift registers and other popular memory types. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 6 Pentek. all the logic elements in FPGAs can execute in parallel. Again.com . This includes the hardware multipliers. FIFOs. this is dramatically different from sequential execution and data fetches from external memory as in a programmable DSP. etc.speed peripherals and buses. § Parallel and Pipelined Data Flow Ÿ Systolic simultaneous data movement § Flexible I/O Ÿ Supports a variety of devices. They offer the advantages of parallel hardware to handle some of the high process intensity functions like DDCs and the benefit of programmability to accommodate some of the decoding and analysis functions of DSPs. look up tables. FIFOs. so that the whole signal processing task operates in parallel in a systolic pipelined fashion.

304 DSP48E 480–2. Upper Saddle River. more processing power. The Virtex-II Pro family dramatically increased the number of hardware multipliers and also added embedded PowerPC microcontrollers. Virtex-6 tops out at an impressive 2016 DSP slices. The Virtex-4 LX family delivers maximum logic and I/O pins while the SX family boasts of 512 DSP slices for maximum DSP performance.784 DSP48E 48–640 12–16 – 480–640 Virtex-6 LXT.Putting FPGAs to Work in Software Radio Systems FPGA Resources FPGA Resource Comparison Virtex-II Pro VP50.504–38. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. SXT 46K–156K 7K–24K 150K–207K 2. The Virtex-5 family LXT devices offer maximum logic resources.4 Logic Cells Figure 9 The above chart compares the available resources in the four Xilinx FPGA families that are used in most of the Pentek products.0 in x1 through x8 configurations. The Virtex-4 family is offered as three subfamilies that dramatically boost clock speeds and reduce power dissipation over previous generations.768 DSP48 64–512 0–20 – 448–768 Virtex-5 FXT. LXT. Virtex-6 supports PCI Express 2. Increases in operating speed from 500 MHz in V-4 to 550 MHz in V-5 to 600 MHz in V-6 and increasing density allows more DSP slices to be included in the same-size package. The FX family is a generous mix of all resources and is the only family to offer RocketIO.176–5. The Virtex-5 devices offer lower power dissipation. The Virtex-6 devices offer higher density. PowerPC cores. demodulators and FFTs—a major benefit for software radio signal processing. lower power consumption. LXT and SXT ● Virtex-6: LXT and SXT The Virtex-II family includes hardware multipliers that support digital filters. and updated interface features to match the latest technology I/O requirements including PCI Express. LX and SX ● Virtex-5: FXT. They also improve the clocking features to handle faster memory and gigabit interfaces. faster clock speeds and enhanced logic slices. They support faster single-ended and differential parallel I/O buses to handle faster peripheral devices.com . Inc. • One Park Way. SXT 128K–476K 20K–74K 160K–595K 9.25 Logic Cells. The ample DSP slices are responsible for the majority of the processing power of the Virtex-6 family.160–8.728–6.pentek. The SXT devices push DSP capabilities with all of the same extras as the LXT. The FXT devices follow as the embedded system resource devices. and Ethernet media access controllers. As shown in the chart. VP70 Logic Cells Slices* CLB Flip-Flops Block RAM (kb) DSP Hard IP DSP Slices Serial Gbit Transceivers PCI Express Blocks SelectIO 53K–74K 24K–33K 47K–66K 4. and the newly added gigabit Ethenet ports. averagers. 7 Pentek. gigabit serial transceivers. LX. SX 41K–152K 18K–68K 49K–93K 1. Virtex-5 and Virtex-6 Slices actually require 6.com • http://www.904 18x18 Multipliers 132–328 – – – Virtex-4 FX.016 20 2 600 *Virtex-II Pro and Virtex-4 Slices actually require 2. ● Virtex-II Pro: VP50 and VP70 ● Virtex-4: FX.

Inc. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. timing and sync functions. If you want to add your own algorithms to Pentek catalog products. interrupt support. timing functions. This includes control and status registers.Putting FPGAs to Work in Software Radio Systems FPGA Resources GateFlow® FPGA Design Resources GateFlow FPGA Design Kit § Allows FPGA design engineers to easily add functions to standard factory configuration GateFlow FPGA Design Kit GateFlow Factory Installed IP Cores § Includes VHDL source code for all standard functions: Ÿ Control and status registers Ÿ A/D and Digital receiver interfaces Ÿ Mezzanine interfaces Ÿ Triggering. The GateFlow line is compatible with the Xilinx Virtex products and is available as two separate offerings: If you want to add your own custom algorithms. 8 Pentek. These algorithms are designed expressly for Xilinx FPGAs and Pentek hardware products Installed Cores are delivered to you preinstalled in your Pentek FPGA-based product of choice and are fully supported with Pentek ReadyFlow® Board Support Packages. as well as several different data formatting options. Let’s start with the GateFlow FPGA Design Kit. The GateFlow Design Kit includes the VHDL source code for every software module we use to create these standard factory features of the product. channel selection. VHDL is one of the most popular languages used in the FPGA design tools. • One Park Way. Upper Saddle River.com . data formatting. We also include a special User Block. positioned right in the data stream. These are also fully supported with our ReadyFlow Board Support Package. clocking.com • http://www. and data tagging. sync and gating functions Ÿ Data packing and formatting Ÿ Channel selection Ÿ A/D / Receiver multiplexing Ÿ Interrupt generation Ÿ Data tagging and channel ID § User Block for inserting custom code Figure 10 Figure 11 GateFlow® is Pentek’s flagship collection of FPGA Design Resources.pentek. we offer the GateFlow FPGA Design Kit. We also offer popular high-performance signal-processing algorithms with the GateFlow factory-installed IP Cores. peripheral interfaces. The standard factory configuration supports a wide range of operating modes. so you can easily drop in your own custom signal processing algorithms. mezzanine interfaces. we offer the GateFlow FPGA Design Kit that includes VHDL source code for all the standard factory functions.

These include configuration and definition files. status. The GateFlow Design Kit is intended to be used with the Xilinx ISE Foundation Tool Suite and customers should be trained and familiar with this tool and FPGA design principles. The design kit installs as a complete project file within the ISE environment and includes all the project files that Pentek engineers used to create the standard factory product. the FPGA designer. can create an IP core or a custom algorithm inside the User Block so that it conforms to the pin definition. control. control. and clocks. And remember. 9 Pentek. in general. since we provide source code for all the mezzanines. Upper Saddle River.com . you can also make changes outside the User Block. the User Block is configured as a straight wire between input and output. status.Putting FPGAs to Work in Software Radio Systems FPGA Resources GateFlow Design Kit User Block § Simplified view of typical VHDL source code modules § User Block pins defined for input. but one important resource is the FPGA Loader Utility. The User Block is a VHDL module that sits in the data path with pin definitions for input. & clocks § Data path is factory configured as a “straight wire” § Low risk strategy for custom IP development and insertion DIGITAL INPUT ANALOG INPUT A/D FPGA USER BLOCK MEZZANINE INTERFACE GateFlow Design Kit Project Files § Project files for Xilinx Foundation ISE Tools Ÿ Archived project files for default factory configuration for standard factory product operation Ÿ VHDL source code for all project files Ÿ Software module interconnect block diagram Ÿ JTAG chain definition files Ÿ User Block I/O connections diagram DATA SOURCE SELECT INPUT Customer OUTPUT Installed DEFAULT BYPASS Algorithm OUTPUT DATA FORMATTER DDC CONTROL STATUS DMA CONTROL & COUNTERS § Complete Pentek Project Directory Ÿ Ready to start development EXT CLK LVDS CLK & SYNC XTAL OSC CLOCK & SYNC DRIVERS CLOCK CONTROL SYNC / GATE / TRIGGER GENERATOR STATUS & CONTROL INTERRUPT GENERATOR § Other files Ÿ Pentek FPGA Design Kit User’s Manual Ÿ FPGA manufacturers data sheet and user’s guide § FPGA Loader Utility Figure 12 Figure 13 Here’s a simplified block diagram of a typical software radio mezzanine showing the FPGA as the large green box and external hardware devices connected to it.com • http://www. If you. Inc. The design kit also includes several utilities. The yellow blocks inside the FPGA are VHDL code modules that handle the standard factory functions and interfaces. output. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. output. In the standard product. • One Park Way.pentek. VHDL source. you will have a very lowrisk experience in recompiling and installing the custom code. JTAG definition files and I/O block diagrams.

These include image processing. telecom. Purchasing these popular factory-installed cores saves you the time and costs of acquiring FPGA tools and developing custom FPGA code. The FPGA Loader Utility allows the processor associated with the FPGA product to reconfigure the FPGA as a software task. D/A. They are delivered to you preinstalled in your Pentek FPGA-based product of choice and are fully tested and supported with the Pentek ReadyFlow Board Support Packages. effectively overwriting the factory configuration code. execution and throughput speed. Upper Saddle River.com . This can be done without turning off power. 10 Pentek. The Loader Utility is especially useful as a runtime resource. etc Custom FPGA Factory Configuration Custom Configuration DATA STREAM Power Up Load EEPROM Factory FPGA Configuration § Pentek Installs IP Cores in Pentek Products § Cores are tailored and optimized for: Ÿ Specific devices and I/O found on Pentek products Ÿ Efficient FPGA resource utilization Ÿ Execution and throughput speed MEZZANINE BASEBOARD CONTROL Bi-FIFO Processor Node Global I/O GLOBAL RESOURCES Backplane I/O SYSTEM BACKPLANE § Eliminates need for customer FPGA development § Fully supported with ReadyFlow Board Support Libraries Figure 14 Figure 15 Normally. signal intelligence. It can also facilitate product upgrades and enhancements to dramatically extend product longevity. These algorithms are designed expressly for Xilinx FPGAs and Pentek harware products. the FPGA can be reconfigured during initialization to install custom operational modes and features.Putting FPGAs to Work in Software Radio Systems FPGA Resources GateFlow Design Kit Loader Utility Front Panel I/O GateFlow Installed IP Cores High Performance I/O DDCs.com • http://www. telemetry. to implement that mode as part of the runtime executable code. and many other disciplines. In this way. communications. FPDP. FPGAs. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The cores take full advantage of the numerous hardware multipliers to achieve highlyparallel processing structures that can dramatically outperform programmable RISC and DSP processors. The user can select a new mode of operation and cause a new FPGA configuration upload. Digital I/O. without disassembling the board or system and without attaching any special cables or harnesses to the board. when the product is powered up. A/D. wireless communications. a third party program sponsored by Xilinx for companies that specialize in specific areas of expertise in developing FPGA algorithms for niche application areas. wireless networking. Pentek is an AllianceCore Member. the FPGA is loaded from a nonvolatile EEPROM with the standard factory configuration code. Inc. Installed Cores are optimized for efficient FPGA resource utilization. Pentek offers popular high-performance signal processing algorithms installed in Pentek products.pentek. • One Park Way.

Regardless of whether it’s implemented in an ASIC or an FPGA. It uses a CIC (Cascaded Integrator Comb) filter to decimate the data. This function enables the user to tune the receiver to the desired frequency of interest. It thus becomes apparent how the DDC might map into current FPGA families. A second CIC filter provides a coarse gain adjustment stage.Putting FPGAs to Work in Software Radio Systems FPGA Resources Digital Downconverter Fundamentals Tuning Stage COMPLEX DIGITAL MIXER Signal In Data Reduction Gain Adjustment Additional Data Reduction and Signal Shaping I Q CIC Initial Downsample CIC Coarse Gain CFIR Polyphase Decimator PFIR Polyphase Decimator Rounding Signal Out SIN Tuning Frequency COS Filter Coefficients Filter Coefficients DDS NCO Figure 16 Over the past few years. • One Park Way. this implementation shift brings advantages that include: design flexibility.com • http://www. The second stage of the DDC reduces the sampling frequency of the signal to match the desired output bandwidth. For many applications. The signal is then passed to a pair of additional polyphase filters. this is the common architecture of the DDC function. The general purpose logic resource and on-chip memory of FPGAs also match the requirements of the DDC for implementing the required FIR filters and filter coefficient tables. As part of their IP library series. Most new FPGAs include a wealth of DSP function blocks which are primarily multipliers. and lower cost per channel. This filter pair provides additional decimation and final signal shaping prior to the rounding stage and final output. lower power. the functions associated with DDCs have seen a shift from being delivered in ASICs (Application-Specific ICs) to operating as IP (Intellectual Property) in FPGAs. The block diagram shows a classic DDC. higher precision processing. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. higher channel density. 11 Pentek. When we get past all the acronyms. The first stage of the DDC uses a complex digital mixer to translate the frequency of interest down to baseband.pentek. following the classic DDC architecture shown here. these benefits continue to increase. Xilinx provides a free DDC core. To understand how FPGAs play a key role in implementing DDCs that perform the function of a receiver. It uses a pair of multipliers and a DDS (Direct Digital Synthesizer) as the NCO (Numerically Controlled Oscillator). Inc. the real advantages of an IP-based implementation can be best seen in optimized custom cores that are designed to match the requirements of a specific application. The core serves as a good general reference design. With the advent of each new higher performance FPGA family during the past few years.com . While this core can be used as a building block for general purpose DDCs. Upper Saddle River. First a CFIR (Compensation Finite Impulse Response) filter then to a PFIR (Programmable Finite Impulse Response) filter. we realize that most of the individual function blocks of the DDC are implemented using multipliers. it’s important to break the DDC down into its individual functional blocks.

984 2–65.5 41 204 2 102 6 44 29 57 Note 1 : Area per Channel = IC area ÷ number of channels. PCI and PCI Express form factors. For each core.0 0. the number of channels that can be fit into a single FPGA is limited. Figure 17 Pentek offers a series of high-performance IP-based DDCs. Inc.384 2–64 1.024 16–8.pentek. it becomes apparent that narrowband.01 2. is included as a reference. These cores range from the high-channel count/narrow bandwidth of the 430 Core installed in the Model 7141. high channel-count DDC cores can be very efficiently implemented in FPGAs. Implementation of wideband DDCs consumes many more FPGA DSP and logic resources. All products are available in industry standard PMC/XMC modules as well as 3U and 6U CompactPCI. The improved SFDR of the Pentek 420 core is an example of such a requirement. • One Park Way.192 2–256 2–65.536 160 110 110 125 200 200 200 200 115 118 110 108 105 105 120 120 1 Binary 256 1 64 8 1 1 72.7 38. As a result.024–9.5 0. the GC4016.Putting FPGAs to Work in Software Radio Systems FPGA Resources IP Enables Software Radio Products DDC Number Decimation Input Rate SFDR Decimation Area per Power per Cost per Implementation of Channels Range (MHz) (dBFS) Steps Channel (mm2)1 Channel (W)2 Channel ($)3 TI GC4016 ASIC Pentek 7141-420 Pentek 7141-430 Pentek 7142-428 Pentek 7151 Pentek 7152 Pentek 7153 Pentek 7153 4 2 256 4 256 32 4 2 32–16. Even with less costeffective wideband DDCs. The above table lists the range of DDC cores available from Pentek as software radio modules. a popular ASIC-based DDC solution from Texas Instruments. Note 2 : GC4016 Power per Channel = Total IC power ÷ number of channels.25 2.04 0.2 4.25 2. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com . pertinent specifications are listed.7 206. Each is optimized to match a specific range of application requirements.536 128–1.3 206. 12 Pentek.25 1. Note 3 : GC4016 Cost per Channel = cost of IC ÷ number of channels. Upper Saddle River. IP core Cost per Channel = cost of FPGA resources used ÷ number of channels.5 0.com • http://www. In addition to the IP-based solutions. to the wider bandwidths and excellent SFDR (Spurious Free Dynamic Range) of the core installed in the Model 7153. When compared on a size/power/cost per channel basis. the custom IP approach can sometimes provide the only viable solution when a specific performance characteristic is required.2 612. IP Core Power per Channel = (FPGA power with IP core – FPGA power without IP core) ÷ number of channels.5 4.3 612. available preinstalled in software radio modules.

13 Pentek. Similarly.Putting FPGAs to Work in Software Radio Systems FPGA Resources Flexible Implementation Figure 18 An additional benefit of IP based solutions is the flexible nature of their implementation. Such applications can benefit greatly by IP based solutions. need to operate across a wide spectrum to handle the diverse signal types. shows the six optimized Pentek cores across a range of applications and the number of channels and bandwidth they typically require.pentek. to achieve with ASIC-based solutions. optimized IP cores. if not impossible. The Models 7141-420 and 7141-430 are created by using the same hardware base with different installed IP cores. 16-bit A/D PMC/XMC with different FPGA IP cores. • One Park Way. 7152 and 7153 are all based on the same 4-channel. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com . Again. All share the same software base allowing migration between different applications to be accomplished with minimum software porting. 200 MHz. the Models 7151. some applications like JTRS (Joint Tactical Radio System). This is one of the fundamental concepts of SDR (Software Defined Radio).com • http://www. This Figure. this wide range of applications can be satisfied by using a small set of hardware with different. Additionally. and it’s difficult. Upper Saddle River. Inc.

com • http://www. Inc. A visual comparison of these two solutions is shown in the above Figure. 14 Pentek. it’s easy to understand how packing many channels of DDCs into one or two FPGAs can reduce the board count.com . • One Park Way. This enables IP-based DDCs to outperform their ASIC-based cousins with specifications like better SFDR. a viable solution would have used the TI/Graychip 4-channel GC4016 ASIC-based DDCs. An E-GMS receiver requires 174 channels spaced 200 kHz apart. power requirements and cost over a solution that requires 30 or 40 individual ASIC DDC chips. One PMC can house two 100MHz A/Ds and four GC4016s and all of the required interface and support circuitry. typically. processing precision continues to increase. Again.Putting FPGAs to Work in Software Radio Systems FPGA Resources System Level Savings Comparing FPGAs and ASICs Figure 19 Figure 20 Let’s now take a look at a complete receiver system.pentek. narrower bandwidths. FPGA solutions are extremely flexible since they can support vastly different signals with the simple loading of a different IP core while using the same hardware platform. As shown in this Figure. ultimately the technical requirements may require the choice of an ASIC or FPGA solution. size and power are important factors in designing a receiver system. One common application is GSM 2G. A common board form factor for these types of application is PMC. such as the Pentek Model 7131. With each new generation of higher performance FPGAs. low bandwidth system. In systems with just one or two channels and bandwidths in the range of 100 MHz or greater. an IP DDC with 174 channels and similar performance to the 4016 can fit in a single Virtex-5 XC5VSX95T FPGA that can be housed in a single PMC. while cost. Just three or four years ago. Upper Saddle River. the higher cost of the FPGAs needed can quickly exceed the cost of designing the system with a single multichannel DDC ASIC. FPGA solutions are not a perfect match for all requirements. FPGAs continue to offer new possibilities and performance when addressing processing tasks like digital downconversion. along with four channels of 200MHz A/Ds and all support circuitry such as the Pentek Model 7151. Additionally. By comparison. They show the greatest advantages in systems with high channel densities and. a high channel count. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. For a 174-channel system this would require 11 Model 7131’s.

All Pentek software radio products include multiboard synchronization that facilitates the design of multichannel systems with synchronous clocking.Putting FPGAs to Work in Software Radio Systems Products PMC. Inc. PCI Express. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. VPX. Pentek’s comprehensive software support includes the ReadyFlow® Board Support Package. Some of these products are software radio receivers in that they include only DDCs. Upper Saddle River. and VMEbus Software Radio 3U VPX Board Half-length PCI Express Board PMC/XMC Module 6U CompactPCI Board PCI Board Full-length PCI Express Board VMEbus Board Figure 21 The Pentek family of board-level software radio products is the most comprehensive in the industry. Others are software radio transceivers and they include DDCs as well as DUCs with output D/A converters. Pentek software radio recording systems are supported with SystemFlow® recording software that features a graphical user interface. A complete listing of these products with active links to their datasheets on Pentek’s website is included at the end of this handbook. In addition to their commercial versions. PMC/XMC. CompactPCI.pentek. many software radio products are available in ruggedized and conduction-cooled versions. In addition. Most of these products are available in several formats to satisfy a wide range of requirements. All of the software radio products include input A/D converters. These come with independent input and output clocks. the GateFlow® FPGA Design Kit and high-performance factoryinstalled IP cores that expand the features and range of many Pentek software radio products. gating and triggering. 15 Pentek. • One Park Way.com . PCI.com • http://www.

a 16-Channel Multiband Receiver. triggering and frequency switching signals.com . is a PMC module. Two 14-bit 105 MHz A/D Converters accept transformer-coupled RF inputs through two front panel SMA connectors. Both inputs are connected to four TI/GC4016 quad DDC chips. Four parallel outputs from the four DDCs deliver data into the Virtex-II FPGA which can be either the XC2V1000 or XC2V3000. 16 Pentek. All these products have similar features. The 7131 PMC may be attached to a wide range of industry processor platforms equipped with PMC sites. The sampling clock can be sourced from an internal 100 MHz crystal oscillator or from an external clock supplied through an SMA connector or the LVDS clock/sync bus on the front panel. Versions of the 7131 are also available as a PCI board (Model 7631A). respectively. • One Park Way.5 MHz channels can be combined for output bandwidths of 5 MHz or 10 MHz. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Custom interfaces can be implemented by using the 64 user-defined FPGA I/O pins on the P4 connector. Up to 80 modules can be synchronized with the Model 9190 Clock and Sync Generator. Inc.com • http://www. The outputs of the two A/D converters are also connected directly to the FPGA to support the DDC bypass path to the PCI bus and for direct processing of the wideband A/D signals by the FPGA. Upper Saddle River. so that all 16 DDC channels can independently select either A/D.pentek.Putting FPGAs to Work in Software Radio Systems Products Multiband Receivers Model 7131 PMC ● Model 7231 6U cPCI ● Model 7331 3U cPCI ● Model 7631A PCI ● Model 5331 3U VPX Model 7631A PCI Model 7131 PMC Model 5331 3U VPX Figure 22 Model 7331 3U cPCI Model 7231D 6U cPCI The Model 7131. gating. 3U cPCI (Model 7331) and 3U VPX (Model 5331). The unit supports the channel combining mode of the 4016s such that two or four individual 2. 6U cPCI (Models 7231 and 7231D dual density). The LVDS bus allows multiple modules to be synchronized with the same sample clock.

512 MB DDR SDRAM delay memory and the PCI bus. The front end of the module accepts two RF inputs and transformer-couples them into two 14-bit A/D converters running at 105 MHz. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com .com • http://www. and SDRAM memory control.Putting FPGAs to Work in Software Radio Systems Products Multiband Transceivers with Virtex-II Pro FPGA Model 7140 PMC/XMC ● Model 7240 6U cPCI Sample Clock A In TIMING BUS GENERATOR A XTL OSC A ● Model 7340 3U cPCI RF In RF XFORMR RF In RF XFORMR ● Model 7640 PCI RF Out RF XFORMR RF Out RF XFORMR LVDS Clock A LVDS Sync A LVDS Gate A TTL Gate/ Trigger TTL Sync LVDS Gate B LVDS Sync B LVDS Clock B Clock/Sync/Gate Bus A SYNC INTERRUPTS & CONTROL Clock/Sync/Gate Bus B 16-bit D/A AD6645 105 MHz 14-bit A/D 14 AD6645 105 MHz 14-bit A/D 14 16 16 16 16-bit D/A DAC5686 DIGITAL UPCONVERTER GC4016 4-CHANNEL DIGITAL RECEIVER 14 32 FLASH 16 MB 16 24 TIMING BUS GENERATOR B Sample Clock B In XTL OSC B To All Sections Control/ Status 32 DDR SDRAM 128 MB VIRTEX-II Pro FPGA XC2VP50 DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.2 INTERFACE (64 Bits / 66 MHz) 8X 64 PCI BUS (64 Bits / 66 MHz) P15 XMC P4 PMC VITA 42. In addition to acting as a simple transceiver.0 FPGA I/O (Serial RapidIO. 17 Pentek. gating. Inc. All these products have similar features. Factory-installed FPGA functions include data multiplexing. These resources include a quad digital downconverter. The FPGA also serves as a control and status engine with data and programming interfaces to each of the on-board resources.pentek. The digital upconverter can be bypassed for two interpolated D/A outputs with sampling rates to 500 MHz. • One Park Way.) Figure 23 The Model 7140 PMC module combines both receive and transmit capability with a high-performance Virtex II-Pro FPGA and supports the VITA 42 XMC standard with optional switched fabric interfaces for high-speed I/O. data packing. The upconverter translates a real or complex baseband signal to any IF center frequency from DC to 160 MHz and can deliver real or complex (I + Q) analog outputs through its two 16-bit D/A converters. Versions of the 7140 are also available as a PCI board (Model 7640). 6U cPCI (Models 7240 and 7240D dual density). triggering. etc. (Option –104) PCI-Express. The digitized output signals pass to a Virtex-II Pro FPGA for signal processing or routing to other module resources. developed using Pentek’s GateFlow and ReadyFlow development tools. Each channel in the downconverter can be set with an independent tuning frequency and bandwidth. the module can perform user-defined DSP functions on the baseband signals. The module includes a TI/GC4016 quad digital downconverter along with a TI DAC5686 digital upconverter with dual D/A converters. or 3U cPCI (Model 7340). 32 DDR SDRAM 128 MB 32 DDR SDRAM 256 MB Model 7140 PMC/XMC 64 PCI 2. a digital upconverter with dual D/A converters. Upper Saddle River. channel selection.

all the standard features of the 7140 are retained.25 MHz for an A/D sampling of 100 MHz. An output decimator and formatter deliver either complex or real data. expands the interpolation factor from 2 to 32. A multiplexer in front of the Core 420 DDCs allows data to be sourced from either the A/Ds or the GC4016. 8. The FIR filter is capable of storing and utilizing up to four independent sets of 18-bit coefficients for each decimation value. 18 Pentek. 6U cPCI (Models 7240-420 and 7240D-420 dual density). Upper Saddle River. An input gain block scales both I and Q data streams by a 16-bit gain term. These coefficients are user-programmable by using RAM structures within the FPGA. extending the maximum cascaded decimation range to 1. In addition to the Core 420. A complex FIR low pass filter removes any out-of-band frequency components. the maximum interpolation factor is 32. and 64 provide output bandwidths from 40 MHz down to 1.768 which is comparable to the maximum decimation of the GC4016 narrowband DDC. • One Park Way. Versions of the 7140-420 are also available as a PCI board (Model 7640-420).com • http://www. Including the DUC.com .Putting FPGAs to Work in Software Radio Systems Products Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores Model 7140-420 PMC/XMC ● Model 7240-420 6U cPCI Model 7340-420 3U cPCI ● Model 7640-420 PCI CH A RF In RF XFORMR AD6645 105 MHz 14-bit A/D WIDEBAND DDC CORE CH B RF In RF XFORMR AD6645 105 MHz 14-bit A/D DDC C DDC D MEMORY D/A A CONTROL D/A B & A/D A DATA ROUTING A/D B 128 MB DDR SDRAM 128 MB DDR SDRAM 256 MB DDR SDRAM Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D MEMORY MEMORY A/D A A/D B DDC A DDC B A/D A A/D B DDC A DDC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION: 2 – 64 MEM W FIFO MEM W FIFO A/D A FIFO A/D B FIFO WB DDC A DDC A WB DDC B DDC B MUX MUX DDC A FIFO DDC B FIFO DDC C FIFO PCI BUS 64 bit / 66 MHz CLOCK & SYNC GENERATOR XTAL OSC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION:.2 INTERFACE CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A DAC 5686 DIGITAL 16-bit UPCONVERTER 500 MHZ D/A MUX CIC FILTER CFIR FILTER MUX MEMORY D/A A FIFO MEMORY D/A B FIFO DDC D FIFO D/A A FIFO D/A B FIFO INTERPOLATION CORE XC2VP50 Figure 24 The Pentek IP Core 420 includes a dual highperformance wideband DDC and an interpolation filter. or 3U cPCI (Model 7340-420). each of the core 420 DDCs translates any frequency band within the input bandwidth range down to zero frequency. The mixer utilizes four 18x18-bit multipliers to handle the complex inputs from the NCO and the complex data input samples.576. 16.pentek. Like the GC4016. 32.2 – 64 PCI 2. Inc. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 4.768 programmable in steps of 2.048. All these products have similar features. Factory-installed in the Model 7140 FPGA. and relieves the host processor from performing upsampling tasks. The interpolation filter included in the 420 Core. they extend the range of both the GC4016 ASIC DDC and the DAC5686 DUC. The decimation settings of 2.

Inc. Versions of the 7140-430 are also available as a PCI board (Model 7640-430). It differs from others in that the channel center frequen- cies need not be at fixed intervals. 19 Pentek. Filter 2 DDC 1 Local Oscillator. Mixer.pentek. • One Park Way. a multiplexer allows the 7140430 to route either the output of the GC4016 or the Core 430 DDC to the PCI Bus. Mixer. Core 430 creates a flexible. and 18-bit user programmable FIR decimating filter coefficients for the DDCs. A TI DAC5686 digital upconverter and dual D/A accepts baseband real or complex data streams from the PCI Bus with signal bandwidths up to 40 MHz. Added flexibility comes from programmable global decimation settings ranging from 1024 to 8192 in steps of 256. Unlike classic channelizer methods. or 3U cPCI (Model 7340-430). NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Filter M U X 255 DDC 255 Local Oscillator. A multiplexer in front of the core allows data to be sourced from either A/D converter A or B. CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A 16-bit 500 MHZ D/A DAC 5686 DIGITAL UPCONVERTER D/A A FIFO D/A B FIFO XC2VP50 Figure 25 For applications that require many channels of narrowband downconverters. All these products have similar features. Default DDC filter coefficient sets are included with the core for all possible decimation settings. Upper Saddle River. Filter 256 DDC 256 Local Oscillator. Filter OUT A DDC A OUT B DDC B OUT C DDC C OUT D DDC D DDC A FIFO DDC B FIFO DDC C FIFO DDC D FIFO PCI 2.Putting FPGAs to Work in Software Radio Systems Products Transceivers with 256-Channel Narrowband DDC Installed Core Model 7140-430 PMC/XMC ● Model 7240-430 6U cPCI Model 7340-430 3U cPCI ● Model 7640-430 PCI CH A RF In RF XFORMR AD6645 105 MHz 14-bit A/D MEM W FIFO MEM W FIFO CH B RF In RF XFORMR AD6645 105 MHz 14-bit A/D 256 CHANNEL DIGITAL DOWNCONVERTER BANK CORE 1 DDC 1 Local Oscillator.com • http://www. Factory installed in the Model 7140 FPGA. In addition to the DDC outputs. Core 430 utilizes a unique method of channelization.2 INTERFACE INT PCI BUS 64 bit / 66 MHz Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A MUX A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D M U X CLOCK & SYNC GENERATOR XTAL OSC B . Mixer. Mixer. 6U cPCI (Models 7240-430 and 7240D-430 dual density). and are independently programmable to any value. Core 430 DDC comes factory installed in the Model 7140-430. the Pentek 430 core allows for completely independent programmable tuning of each individual channel with 32-bit resolution as well as filter characteristics comparable to many conventional ASIC DDCs. Pentek offers the GateFlow IP Core 430 256-channel digital downconverter bank. very high-channel count receiver system in a small footprint.com . At the output. data from both A/D channels are presented to the PCI Bus at a rate equal to the A/D clock rate divided by any integer value between 1 and 4096.

2 INTERFACE (64 Bits / 66 MHz) 64 P4 PMC P15 XMC FPGA I/O VITA 42. Model 7141-703 is a conduction-cooled version. Inc. 20 Pentek. The front end of the module accepts two RF inputs and transformer-couples them into two 14-bit A/D converters running at 125 MHz. 6U cPCI (Models 7241 and 7241D dual density). The upconverter translates a real or complex baseband signal to any IF center frequency from DC to 160 MHz and can deliver real or complex (I + Q) analog outputs through its two 16-bit D/A converters. 32 DDR SDRAM 128 MB 32 DDR SDRAM 256 MB Model 7141 PMC/XMC 64 PCI 2. Factory-installed FPGA functions include data multiplexing. channel selection.com • http://www. and SDRAM memory control. the module can perform user-defined DSP functions on the baseband signals. PCIe half-length board (Model 7841). Each channel in the downconverter can be set with an independent tuning frequency and bandwidth. Versions of the 7141 are also available as a PCIe full-length board (Models 7741 and 7741D dual density). a digital upconverter with dual D/A converters. etc.com . PCI board (Model 7641).pentek. • One Park Way. data packing.Putting FPGAs to Work in Software Radio Systems Products Multiband Transceivers with Virtex-II Pro FPGA Model 7141 PMC/XMC ● Model 7241 6U cPCI ● Model 7341 3U cPCI ● Model 7641 PCI ● Model 7741 Full-length PCIe ● Model 7841 Half-length PCIe ● Model 5341 3U VPX Sample Clock A In TIMING BUS GENERATOR A XTL OSC A RF In RF XFORMR RF In RF XFORMR RF Out RF XFORMR RF Out RF XFORMR LVDS Clock A LVDS Sync A LVDS Gate A TTL Gate/ Trigger TTL Sync LVDS Gate B LVDS Sync B LVDS Clock B FRONT PANEL CONNECTOR SYNC Clock/Sync/Gate Bus A 16-bit D/A LTC2255 AD6645 105 MHz 125 14-BITA/D 14-bit A/D 14 LTC2255 AD6645 105 MHz 125 14-BITA/D 14-bit A/D 14 16 16 16 GC4016 4-CHANNEL DIGITAL RECEIVER 14 24 32 16-bit D/A INTERRUPTS & CONTROL Clock/Sync/Gate Bus B DAC5686 DIGITAL UPCONVERTER FLASH 16 MB 16 TIMING BUS GENERATOR B Sample Clock B In XTL OSC B To All Sections Control/ Status 32 DDR SDRAM 128 MB VIRTEX-II Pro FPGA XC2VP50 DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc. 3U VPX board (Model 5341). NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The FPGA also serves as a control and status engine with data and programming interfaces to each of the on-board resources. gating. and 3U cPCI (Model 7341).) PCI BUS (64 Bits / 66 MHz) Figure 26 The Model 7141 PMC/XMC module combines both receive and transmit capabilities with a highperformance Virtex II-Pro FPGA and supports the VITA 42 XMC standard with optional switched fabric interfaces for high-speed I/O. developed using Pentek’s GateFlow and ReadyFlow development tools. Upper Saddle River. These resources include a quad digital downconverter. The module includes a TI/GC4016 quad digital downconverter along with a TI DAC5686 digital upconverter with dual D/A converters. In addition to acting as a simple transceiver. The digital upconverter can be bypassed for two interpolated D/A outputs with sampling rates to 500 MHz. The digitized output signals pass to a Virtex-II Pro FPGA for signal processing or routing to other module resources. triggering. 512 MB DDR SDRAM delay memory and the PCI bus.0 (Serial RapidIO. (Option –104) PCI-Express.

NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 21 Pentek. PCI board (Model 7641-420). The decimation settings of 2. • One Park Way.pentek. A multiplexer allows data to be sourced from either the A/Ds or the GC4016. or 3U cPCI (Model 7341-420). These coefficients are user-programmable by using RAM structures within the FPGA. Inc. PCIe full-length board (Models 7741-420 and 7741D-420 dual density).768 which is comparable to the maximum decimation of the GC4016 narrowband DDC. PCIe half-length board (Model 7841-420). and relieves the host processor from performing upsampling tasks. The mixer utilizes four 18x18-bit multipliers to handle the complex inputs from the NCO and the complex data input samples. Factory-installed in the Model 7141 FPGA.048. 6U cPCI (Models 7241-420 and 7241D-420 dual density). the maximum interpolation factor is 32.2 INTERFACE CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A DAC 5686 DIGITAL 16-bit UPCONVERTER 500 MHZ D/A MUX CIC FILTER CFIR FILTER MUX MEMORY D/A A FIFO MEMORY D/A B FIFO DDC D FIFO D/A A FIFO D/A B FIFO INTERPOLATION CORE XC2VP50 Figure 27 The Pentek IP Core 420 includes a dual highperformance wideband DDC and an interpolation filter. they extend the range of both the GC4016 ASIC DDC and the DAC5686 DUC.2 – 64 PCI 2. An input gain block scales both I and Q data streams by a 16-bit gain term. 8.25 MHz for an A/D sampling of 100 MHz. A complex FIR low pass filter removes any outof-band frequency components.576. The interpolation filter included in the 420 Core.com • http://www. 4.com . expands the interpolation factor from 2 to 32. Upper Saddle River.768 programmable in steps of 2. extending the cascaded decimation range to 1. and 64 provide output bandwidths from 40 MHz down to 1. 16. Including the DUC. Model 7141703-420 is a conduction-cooled version. Versions of the 7141-420 are also available as a 3U VPX board (Model 5341-420). 32. Each of the core 420 DDCs translates any frequency band within the input bandwidth range down to zero frequency. An output decimator and formatter deliver either complex or real data.Putting FPGAs to Work in Software Radio Systems Products Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores Model 7141-420 PMC/XMC ● Model 7241-420 6U cPCI ● Model 7341-420 3U cPCI Model 7641-420 PCI ● Model 7741-420 Full-length PCIe Model 7841-420 Half-length PCIe ● Model 5341-420 3U VPX CH A RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D WIDEBAND DDC CORE CH B RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D DDC C DDC D MEMORY D/A A CONTROL D/A B & A/D A DATA ROUTING A/D B 128 MB DDR SDRAM 128 MB DDR SDRAM 256 MB DDR SDRAM Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D MEMORY MEMORY A/D A A/D B DDC A DDC B A/D A A/D B DDC A DDC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION: 2 – 64 MEM W FIFO MEM W FIFO A/D A FIFO A/D B FIFO WB DDC A DDC A WB DDC B DDC B MUX MUX DDC A FIFO DDC B FIFO DDC C FIFO PCI BUS 64 bit / 66 MHz CLOCK & SYNC GENERATOR XTAL OSC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION:. The FIR filter is capable of storing and utilizing up to four independent sets of 18-bit coefficients for each decimation value.

a multiplexer allows for routing either the output of the GC4016 or the 430 DDC to the PCI Bus. Versions of the 7141-430 are also available as a PCIe full-length board (Models 7741-430 and 7741D-430 dual density). Factory installed in the Model 7141 FPGA.Putting FPGAs to Work in Software Radio Systems Products Transceivers with 256-Channel Narrowband DDC Installed Core Model 7141-430 PMC/XMC ● Model 7241-430 6U cPCI ● Model 7341-430 3U cPCI Model 7641-430 PCI ● Model 7741-430 Full-length PCIe Model 7841-430 Half-length PCIe ● Model 5341-430 3U VPX CH A RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D MEM W FIFO MEM W FIFO CH B RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D 256 CHANNEL DIGITAL DOWNCONVERTER BANK CORE 1 DDC 1 Local Oscillator.com . Filter 256 DDC 256 Local Oscillator. Filter OUT A DDC A OUT B DDC B OUT C DDC C OUT D DDC D DDC A FIFO DDC B FIFO DDC C FIFO DDC D FIFO PCI 2. Filter 2 DDC 1 Local Oscillator. PCI board (Model 7641430). very high-channel count receiver system in a small footprint.com • http://www. • One Park Way. A multiplexer allows data to be sourced from either A/D. data from both A/D channels are presented to the PCI Bus at a rate equal to the A/D clock rate divided by any integer value between 1 and 4096. Upper Saddle River. Mixer. Pentek offers the GateFlow IP Core 430 256-channel digital downconverter bank. Mixer. Inc. and are independently programmable to any value. Filter M U X 255 DDC 255 Local Oscillator. the Pentek 430 core allows for completely independent programmable tuning of each individual channel with 32-bit resolution as well as filter characteristics comparable to many conventional ASIC DDCs.pentek. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. A TI DAC5686 digital upconverter and dual D/A accepts baseband real or complex data streams from the PCI Bus with signal bandwidths up to 50 MHz. Model 7141-703430 is a conduction-cooled version. Added flexibility comes from programmable global decimation settings ranging from 1024 to 8192 in steps of 256. 3U VPX board (Model 5341-430). and 18-bit user programmable FIR decimating filter coefficients for the DDCs. It differs from others in that the channel center frequen- cies need not be at fixed intervals. Mixer.2 INTERFACE INT PCI BUS 64 bit / 66 MHz Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A MUX A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D M U X CLOCK & SYNC GENERATOR XTAL OSC B . In addition to the DDC outputs. Mixer. 22 Pentek. Core 430 creates a flexible. PCIe half-length board (Model 7841-430). Default DDC filter coefficient sets are included with the core for all possible decimation settings. CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A DAC 5686 DIGITAL 16-bit UPCONVERTER 500 MHZ D/A D/A A FIFO D/A B FIFO XC2VP50 Figure 28 For applications that require many channels of narrowband downconverters. Unlike classic channelizer methods. 6U cPCI (Models 7241-430 and 7241D-430 dual density). Core 430 utilizes a unique method of channelization. At the output. or 3U cPCI (Model 7341-430). Core 430 DDC comes factory installed in the Model 7141-430.

Upper Saddle River. A high-performance 160 MHz IP core wideband digital downconverter may be factory-installed in the first FPGA. Inc. It includes four 125 MHz 14-bit A/D converters and one upconverter with a 500 MHz 16-bit D/A converter to support wideband receive and transmit communication channels.com • http://www. implemented with the Xilinx Rocket I/O interfaces. A 9-channel DMA controller and 64 bit / 66 MHz PCI interface assures efficient transfers to and from the module. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. PCIe half-length board (Model 7842).pentek. A dual bus system timing generator allows separate clocks.2 INTERFACE PCI BUS (64 Bits / 66 MHz) P15 XMC VITA 42.5 GB/sec data links to the carrier board.0 64 LOCAL BUS 32 32 32 HI-SPEED BUSES Model 7142 PMC/XMC VIRTEX-4 FPGA XC4VFX60 or XC4VFX100 SERIAL INTERFACE 64 P4 PMC FPGA I/O (Option –104) Figure 29 The Model 7142 is a Multichannel PMC/XMC module. 23 Pentek. Two Xilinx Virtex-4 FPGAs are included: an XC4VSX55 or LX100 and an XC4VFX60 or FX100. The first FPGA is used for control and signal processing functions. It also features 768 MB of SDRAM for implementing up to 2. gates and synchronization signals for the A/D and D/A converters. connect the second FPGA to the XMC connector with two 2. 6U cPCI (Models 7242 and 7242D dual density). Two 4X switched serial ports. multichannel applications where the relative phases must be preserved.Putting FPGAs to Work in Software Radio Systems Products Multichannel Transceivers with Virtex-4 FPGAs Model 7142 PMC/XMC ● Model 7242 6U cPCI ● Model 7342 3U cPCI ● Model 7642 PCI Model 7742 Full-length PCIe ● Model 7842 Half-length PCIe ● Model 5342 3U VPX Sample Clock In TIMING BUS GENERATOR A XTL OSC A RF In RF XFORMR RF In RF XFORMR RF In RF XFORMR RF In RF XFORMR RF Out RF XFORMR LVDS Clock A LVDS Sync A LVDS Gate A TTL Gate/ Trigger TTL Sync LVDS Gate B LVDS Sync B LVDS Clock B LTC2255 125MHz INTERRUPTS & CONTROL Clock/Sync/Gate 14-bit A/D Bus B 14 SYNC Clock/Sync/Gate Bus A LTC2255 125MHz 14-bit A/D 14 LTC2255 125MHz 14-bit A/D 14 LTC2255 125MHz 14-bit A/D 14 16-bit D/A DAC5686 DIGITAL UPCONVERTER 32 TIMING BUS GENERATOR B XTL OSC B To All Sections Control/ Status VIRTEX-4 FPGA XC4VSX55 DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc. It also supports large. while the second one is used for implementing board interface functions including the XMC interface. Versions of the 7142 are also available as a PCIe fulllength board (Models 7742 and 7742D dual density).com . A 16 MB flash memory supports the boot code for the two on-board IBM 405 PowerPC microcontroller cores within the FPGA. 32 DDR 2 SDRAM 256 MB 32 DDR 2 SDRAM 256 MB 32 DDR 2 SDRAM 256 MB PCI 2. and 3U cPCI (Model 7342). PCI board (Model 7642). 3U VPX (Model 5342). • One Park Way.0 sec of transient capture or digital delay memory for signal intelligence tracking applications at 125 MHz.

6U cPCI (Models 7242-428 and 7242D-428 dual density). The DDCs consist of two cascaded decimating FIR filters.52 kHz for an A/D sampling rate of 125 MHz and assuming an 80% filter. for a maximum interpolation of 32.2 INTERFACE PCI BUS 64 bit / 66 MHz 256 MB DDR SDRAM MEMORY CONTROL & DATA ROUTING 256 MB DDR SDRAM 256 MB DDR SDRAM CH B RF In RF XFORMR LTC2255 125 MHz 14-bit A/D CH C RF In RF XFORMR LTC2255 125 MHz 14-bit A/D CH D RF In RF XFORMR LTC2255 125 MHz 14-bit A/D M U X M U X Sample Clock In Clock/Sync Bus CLOCK & SYNC GENERATOR XTAL OSC A XTAL OSC B M U X DIGITAL DOWNCONVERTER CORE RF Out RF XFORMR 16-bit 500 MHZ DAC 5686 16-bit D/A 500 MHZ DIGITAL D/A UPCONVERTER CIC FILTER CFIR FILTER MUX MEMORY D/A FIFO D/A FIFO INTERPOLATION CORE XC4VSX55 Figure 30 The Pentek IP Core 428 includes four highperformance multiband DDCs and an interpolation filter. Factory-installed in the Model 7142 FPGA.768. Versions of the 7142-428 are also available as a PCIe full-length board (Models 7742-428 and 7742D-428 dual density). Inc. and 3U VPX (Model 5342-428). After each filter stage is a post filter gain stage. provides output bandwidths from 50 MHz down to 1. The decimation of each DDC can be set independently. 24 Pentek. The Core 428 interpolation filter increases the sampling rate of real or complex baseband signals by a factor of 16 to 2048. STAGE 2 DECIMATION: 1 – 256 DIGITAL DOWNCONVERTR D STAGE 2 DECIMATION: 1 – 256 MEM W FIFO MEM W FIFO A/D A DDC A A/D B DDC B A/D C DDC C A/D D DDC D MUX MUX MUX MUX A/D A FIFO A/D B FIFO A/D C FIFO A/D D FIFO PCI 2. PCI board (Model 7642-428).com • http://www. The overal decimation range from 2 to 65.536. Four identical Core 428 DDCs are factory installed in the 7142-428 FPGA. programmable in steps of 4.pentek.Putting FPGAs to Work in Software Radio Systems Products Transceivers with Four Multiband DDCs and Interpolation Filter Installed Cores Model 7142-428 PMC/XMC ● Model 7242-428 6U cPCI ● Model 7342-428 3U cPCI Model 7642-428 PCI ● Model 7742-428 Full-length PCIe Model 7742-428 Half-length PCIe ● Model 5342-428 3U VPX CH A RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D D/A M U X DIGITAL DOWNCONVERTR A STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR B STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR C STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR D STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR A STAGE 2 DECIMATION: 1 – 256 DIGITAL DOWNCONVERTR B STAGE 2 DECIMATION: 1 – 256 DIGITAL DOWNCONVERTR C . These coefficients are user-programmable by using RAM structures within the FPGA. they add DDCs to the Model 7142 and extend the range of its DAC5686 DUC. The FIR filter is capable of storing and utilizing two independent sets of 18-bit coefficients. NCO tuning frequency. The Core 428 downconverter translates any frequency band within the input bandwidth range down to zero frequency.com . decimation and filter coefficients can be changed dynamically. • One Park Way. PCIe half-length board (Model 7842-428). This gain may be used to amplify small signals after out-of-band signals have been filtered out. Upper Saddle River. and relieves the host processor from performing upsampling tasks. programmable in steps of 1. The NCO provides over 108 dB spurious-free dynamic range (SFDR). The interpolation filter can be used in series with the DUC’s built-in interpolation. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 3U cPCI (Model 7342-428). An input multiplexer allows any DDC to independently select any of the four A/D sources.

NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024.1024 I&Q DDC BANK 1 MUX A/D A FIFO PCI BUS 64 bit / 66 MHz M U X I&Q A/D B DDC BANK 2 MUX A/D B FIFO Sample Clock In PPS In TTL In TIMING BUS GENERATOR Clock / Gate / Sync / PPS M U X I&Q A/D C DDC BANK 3 PCI 2. The front end of the module accepts four RF inputs and transformer-couples them into four 16-bit A/D converters running at 200 MHz. 3U cPCI (Model 7351).8*ƒs/N.com .1024 DIGITAL DOWNCONVERTR BANK 4: CH 193 . For example. formatting and DDC signal processing. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. selectable from 0 to 64.1024 DIGITAL DOWNCONVERTR . The digitized output signals pass to a Virtex-5 FPGA for routing. where N is the decimation setting. with a sampling rate of 200 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. Inc. 6U cPCI (Models 7251 and 7251D dual density). PCIe half-length board (Model 7851). 25 Pentek. 16-bit A/D Model 7151 PMC ● Model 7251 6U cPCI ● Model 7351 3U cPCI ● Model 7651 PCI Model 7751 Full-length PCIe ● Model 7851 Half-length PCIe ● Model 5351 3U VPX CH A RF In RF XFORMR ADS5485 AD6645 200 MHz 105 16-bit A/D 14-bit ADS5485 200 MHz 16-bit A/D ADS5485 200 MHz 16-bit A/D CH B RF In RF XFORMR CH C RF In RF XFORMR CH D RF In RF XFORMR ADS5485 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D M U X DIGITAL DOWNCONVERTR BANK 1: CH 1 . The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Upper Saddle River.64 DECIMATION: 128 . The Model 7151 employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks.Putting FPGAs to Work in Software Radio Systems Products 256-Channel DDC Installed Core with Quad 200 MHz.128 DECIMATION: 128 .256 DECIMATION: 128 . The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. Each of the 256 DDCs has an independent 32-bit tuning frequency setting. and 3U VPX (Model 5351). Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.192 DECIMATION: 128 . programmable in steps of 64. the available output bandwidths range from 156. • One Park Way. The 80% default filters deliver an output bandwidth of 0.2 INTERFACE MUX A/D C FIFO M U X I&Q A/D D DDC BANK 4 MUX A/D D FIFO Sync Bus XTAL OSC DIGITAL DOWNCONVERTER CORE XC5VSX95T Figure 31 The Model 7151 PMC module is a 4-channel highspeed digitizer with a factory-installed 256-channel DDC core.pentek.25 kHz to 1.25 MHz.com • http://www. PCI board (Model 7651). Any number of channels can be enabled within each bank. Versions of the 7151 are also available as a PCIe full-length board (Models 7751 and 7751D dual density). BANK 2: CH 65 .1024 DIGITAL DOWNCONVERTR BANK 3: CH 129 . Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples.

com • http://www. the available output bandwidths range from 19.2 INTERFACE A/D C FIFO Sync Bus XTAL OSC A/D A A/D B A/D C A/D D M U X A/D D BANK 4 MUX A/D D FIFO XC5VSX95T Figure 32 The Model 7152 PMC module is a 4-channel highspeed digitizer with a factory-installed 32-channel DDC core. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. The 80% default filters deliver an output bandwidth of 0. with a sampling rate of 200 MHz.pentek. Inc. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.Putting FPGAs to Work in Software Radio Systems Products 32-Channel DDC Installed Core with Quad 200 MHz. Gain and phase control.8 POWER DEC: 16 . DEC: 16 .24 DEC: 16 . 26 Pentek. Each 8-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. 6U cPCI (Models 7252 and 7252D dual density).16 POWER.53 kHz to 10.8192 METER & THRESHOLD DETECT DIGITAL DOWNCONVERTR I & Q BANK 3: CH 17 . selectable from 0 to 8. programmable in steps of 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank. For example. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192. formatting and DDC signal processing.0 MHz. The rejection of adjacent-band components within the 80% output band-width is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples.8192 METER & THRESHOLD DETECT 8x4 CHANNEL SUMMATION SUM A/D B BANK 1 MUX A/D A FIFO CH C RF In RF XFORMR ADS5485 200 MHz 16-bit A/D M U X CH D RF In RF XFORMR ADS5485 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D M U X A/D B BANK 2 MUX A/D B FIFO PCI BUS 64 bit / 66 MHz Sample Clock In PPS In TTL In TIMING BUS GENERATOR Clock / Gate / Sync / PPS A/D A A/D B A/D C A/D D M U X A/D C BANK 3 MUX PCI 2. power meters and threshold detectors are included. Any number of channels can be enabled within each bank. Upper Saddle River. PCI board (Model 7652).8*ƒs/N. and 3U VPX (Model 5352). Versions of the 7152 are also available as a PCIe fulllength board (Models 7752 and 7752D dual density).8192 METER & THRESHOLD DETECT DIGITAL DOWNCONVERTR I & Q BANK 2: CH 9 . PCIe half-length board (Model 7852). • One Park Way.com . The digitized output signals pass to a Virtex-5 FPGA for routing. where N is the decimation setting. 3U cPCI (Model 7352). Each of the 32 DDCs has an independent 32-bit tuning frequency setting.8192 POWER METER & THRESHOLD DETECT DIGITAL DOWNCONVERTR I & Q BANK 4: CH 25 . 16-bit A/D Model 7152 PMC ● Model 7252 6U cPCI ● Model 7352 3U cPCI ● Model 7652 PCI Model 7752 Full-length PCIe ● Model 7852 Half-length PCIe ● Model 5352 3U VPX CH A RF In RF XFORMR ADS5485 AD6645 200 MHz 105 16-bit A/D 14-bit CH B RF In RF XFORMR ADS5485 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D DIGITAL DOWNCONVERTER CORE DIGITAL DOWNCONVERTR I & Q BANK 1: CH 1 .32 POWER DEC: 16 . The Model 7152 employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. The front end of the module accepts four RF inputs and transformer-couples them into four 16-bit A/D converters running at 200 MHz.

high-speed software radio module designed for processing baseband RF or IF signals. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. Each of the 4 DDCs has an independent 32-bit tuning frequency setting. PCI board (Model 7653). and 3U VPX (Model 5353).256 Gain & Phase Adj I&Q A/D B M U X Timing Clock Sync A/D A A/D B A/D C A/D D M U X POWER METER & THRESHOLD DETECTOR DDC 3 DEC: 2 . 6U cPCI (Models 7253 and 7253D dual density).256 Gain & Phase Adj A/D C I&Q M U X PCI-X Bus 64-bits 100 MHz A/D A A/D B A/D C A/D D M U X DDC 4 DEC: 2 . In addition to the DDCs. Versions of the 7153 are also available as a PCIe fulllength board (Models 7753 and 7753D dual density). The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. Upper Saddle River. the 7153 features a complete beamforming subsystem. The 80% default filters deliver an output bandwidth of 0.pentek. • One Park Way. All four DDCs have a decimation setting that can range from 2 to 256.Putting FPGAs to Work in Software Radio Systems Products 4-Channel DDC and Beamformer Installed Core with four 200 MHz. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The Model 7153 employs an advanced FPGA-based DDC engine consisting of four identical multiband banks. The rejection of adjacent-band components within the 80% output band-width is better than 100 dB.256 Gain & Phase Adj A/D A M U X Sample Clock Gate / Trigger PPS Clock & SYNC Bus XTAL OSC A/D A A/D B A/D C A/D D POWER METER & THRESHOLD DETECTOR M U X DDC 2 DEC: 2 . 27 Pentek. The time constant of the averaging interval for each meter is programmable up to 8 ksamples. It features four 200 MHz 16-bit A/Ds supported by a highperformance 4-channel DDC (digital downconverter) installed core and a complete set of beamforming functions. 3U cPCI (Model 7353). Each channel also includes a threshold detector that sends an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold. Inc. With built-in multiboard synchronization and an Aurora gigabit serial interface. 16-bit A/Ds Model 7153 PMC/XMC ● Model 7253 6U cPCI ● Model 7353 3U cPCI ● Model 7653 PCI Model 7753 Full-length PCIe ● Model 7853 Half-length PCIe ● Model 5353 3U VPX CH A RF In CH B RF In CH C RF In CH D RF In 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D P15 XMC A/D A A/D B A/D C A/D D DIGITAL DOWN CONVERTER CORE M U X Sum In Sum Out POWER METER & THRESHOLD DETECTOR I&Q Aurora Gigabit Serial Interface 4X 4X SUMMER S DDC 1 DEC: 2 . PCIe half-length board (Model 7853).com • http://www. where N is the decimation setting.256 Gain & Phase Adj POWER METER & THRESHOLD DETECTOR I&Q A/D D M U X PCI-X I/F XC5VSX50T FPGA Figure 33 Model 7153 is a 4-channel. programmable independenly in steps of 1. it provides everything needed for implementing multichannel beamforming systems.8*ƒs/N. The power meters present average power measurements for each channel in easy-to-read registers. Each channel contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output.com .

PCI board (Model 7656). data packing. etc. A high-performance IP core wideband DDC may be factory-installed in the processing FPGA. • One Park Way. 6U cPCI (Models 7256 and 7256D dual density).Putting FPGAs to Work in Software Radio Systems Products Dual SDR Transceivers with 400 MHz A/D. gating. SX95T or FX100T LVDS GTP GTP GTP 64 4X GTP 4X 4X Model 7156 PMC/XMC P4 PMC FPGA I/O 32 32 PCI-X BUS (64 Bits 133 MHz) 64 4X P15 XMC VITA 42. and two Virtex-5 FPGAs. Model 7156 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces. The first FPGA is used primarily for signal processing while the second one is dedicated to board interfaces. The Model 7156 architecture includes two Virtex-5 FPGAs.) Figure 34 Model 7156 is a dual high-speed data converter suitable for connection as the HF or IF input of a communications system. SX50T or FX70T LVDS PCI-X GTP RF In RF XFORMR RF Out RF XFORMR RF Out RF XFORMR A/D Clock Bus TIMING BUS GENERATOR Clock/ Sync / Gate / PPS ADS5474 400 MHz 14-bit A/D ADS5474 400 MHz 14-bit A/D 800 MHz 16-bit D/A 800 MHz 16-bit D/A D/A Clock Bus DIGITAL UPCONVERTER 14 Control/ Status 14 32 VCXO To All Sections PROCESSING FPGA VIRTEX –5: LX50T. Two 4X switched serial ports implemented with the Xilinx Rocket I/O interfaces.com . Upper Saddle River. SX50T.and post-triggering. Versions of the 7156 are also available as a PCIe fulllength board (Models 7756 and 7756D dual density). Built-in memory functions include an A/D data transient capture mode with pre. All these products have similar features. It also supports large. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Two independent 512 MB banks of DDR2 SDRAM are available to the signal processing FPGA. triggering and SDRAM memory control. 800 MHz D/A. channel selection.x (PCIe.pentek. 3U cPCI (Model 7356). 28 Pentek. a DUC with two 800 MHz 16-bit D/As.com • http://www. Inc.5 GB/sec data links to the carrier board. and 3U VPX (Model 5356). and Virtex-5 FPGAs Model 7156 PMC/XMC ● Model 7256 6U cPCI ● Model 7356 3U cPCI ● Model 7656 PCI Model 7756 Full-length PCIe ● Model 7856 Half-length PCIe ● Model 5356 3U VPX RF In RF XFORMR Sample Clock In PPS In TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS Timing Bus 32 DDR 2 SDRAM 512 MB 32 DDR 2 SDRAM 512 MB 16 FLASH 32 MB INTERFACE FPGA VIRTEX-5: LX30T. enabling factory installed functions such as data multiplexing. All memory banks can be easily accessed through the PCI-X interface. It features two 400 MHz 14-bit A/Ds. A dual bus system timing generator allows for sample clock synchronization to an external system reference. multichannel applications where the relative phases must be preserved. connect the FPGA to the XMC connector with two 2. PCIe half-length board (Model 7856). All of the board’s data and control paths are accessible by the FPGAs. A 5-channel DMA controller and 64 bit/100 MHz PCI-X interface assures efficient transfers to and from the module.

LX155T.and post-triggering. connect the FPGA to the XMC connector with two 2. Two 4X switched serial ports implemented with the Xilinx Rocket I/O interfaces. All of the board’s data and control paths are accessible by the FPGAs.x (PCIe. gating. It features two 500 MHz 12-bit A/Ds. A 5-channel DMA controller and 64 bit / 100 MHz PCI-X interface assures efficient transfers to and from the module. and Virtex-5 FPGAs Model 7158 PMC/XMC ● Model 7258 6U cPCI ● Model 7358 3U cPCI ● Model 7658 PCI Model 7758 Full-length PCIe ● Model 7858 Half-length PCIe ● Model 5358 3U VPX RF In RF XFORMR Sample Clock / Reference Clock In PPS In TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS Timing Bus 32 DDR 2 SDRAM 256 MB 32 DDR 2 SDRAM 256 MB 16 FLASH 32 MB INTERFACE FPGA VIRTEX-5: LX30T.pentek. PCI board (Model 7658).) Figure 35 Model 7158 is a dual high-speed data converter suitable for connection as the HF or IF input of a communications system. etc. All memory banks can be easily accessed through the PCI-X interface. Model 7158 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces. multichannel applications where the relative phases must be preserved. Two independent 256 MB banks of DDR2 SDRAM are available to the signal processing FPGA. SX50T. and two Virtex-5 FPGAs. 3U cPCI (Model 7358). 29 Pentek. A dual bus system timing generator allows for sample clock synchronization to an external system reference.5 GB/sec data links to the carrier board.com • http://www. Built-in memory functions include an A/D data transient capture mode with pre. 800 MHz D/A. triggering and SDRAM memory control. enabling factory installed functions such as data multiplexing. The first FPGA is used primarily for signal processing while the second one is dedicated to board interfaces. Inc.Putting FPGAs to Work in Software Radio Systems Products Dual SDR Transceivers with 500 MHz A/D. 6U cPCI (Models 7258 and 7258D dual density). NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com . All these products have similar features. channel selection. SX50T or FX70T LVDS PCI-X GTP RF In RF XFORMR RF Out RF XFORMR RF Out RF XFORMR A/D Clock Bus TIMING BUS GENERATOR Clock/ Sync / Gate / PPS ADS5463 500 MHz 12-bit A/D ADS5463 500 MHz 12-bit A/D 800 MHz 16-bit D/A 800 MHz 16-bit D/A D/A Clock Bus DIGITAL UPCONVERTER 14 Control/ Status 14 32 PROCESSING FPGA VCXO To All Sections VIRTEX –5: LX50T. It also supports large. data packing. Versions of the 7158 are also available as a PCIe fulllength board (Models 7758 and 7758D dual density). PCIe half-length board (Model 7858). The Model 7158 architecture includes two Virtex-5 FPGAs. SX95T or FX100T LVDS GTP GTP GTP 64 4X GTP 4X 4X Model 7158 PMC/XMC P4 PMC FPGA I/O 32 32 PCI-X BUS (64 Bits 100 MHz) 64 4X P15 XMC VITA 42. a digital upconverter with two 800 MHz 16-bit D/As. • One Park Way. and 3U VPX (Model 5358). Upper Saddle River.

pentek.com • http://www. • One Park Way. DDR3 SDRAM or QDRII+ SRAM memory. Inc. 2-Channel 800 MHz D/A. gate. triggering and memory control. 16-bit A/Ds. LX240T.x Figure 36 Model 71620 is the first member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. The Model 71620 includes an industry-standard interface fully compliant with PCI Express Gen. Virtex-6 FPGA Model 71620 . 30 Pentek.Putting FPGAs to Work in Software Radio Systems Products 3-Channel 200 MHz A/D. or SX475T. it is suitable for connection to HF or IF ports of a communications and radar system. Multiple 71620’s can be driven from the LVPECL bus master. LX365T. data packing. high-speed data converter. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. or as combination of two banks of each type of memory. SX95T or SX475T LVDS GTP GTP GTP 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 16 16 FLASH 32 MB 40 x8 x4 x4 Model 71620 XMC QDRII+ SRAM 8 MB Optional memory configurations DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB P14 PMC FPGA I/O P15 XMC PCIe P16 XMC VITA 42. It includes three 200 MHz. 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. The FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. and synchronization circuits.0 XMC format and supports PCI Express Gen. enabling factory installed functions including data multiplexing. programmable LVDS I/O and clock. SX315T. channel selection.XMC RF In RF XFORMR TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D RF Out RF XFORMR RF Out RF XFORMR Sample Clk / Reference Clk In A/D Clock Bus 800 MHz 16-BIT D/A 800 MHz 16-BIT D/A TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS Timing Bus DIGITAL UPCONVERTER D/A Clock Bus 14 To All Sections 14 14 32 VCXO Control / Status FPGA VIRTEX-6 LX130T. DDR3 SDRAM. LX240T. two 800 MHz 16-bit D/As. The Model 71620 Cobalt architecture features a Virtex-6 FPGA. and four banks of memory. LX365T. Supported FPGAs include: Virtex-6 LX130T. All of the board’s data and control paths are accessible by the FPGA. Upper Saddle River.com . In addition to the built-in functions. The FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters. users can install their own custom IP for data processing. gating. The 71620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM. DUC. PCIe interface. A multichannel. one DUC. 2. The Model 71620 is compatible with the VITA 42. supporting synchronous sampling and sync functions across all connected boards. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.

channel selection. high-speed data converter. data packing. • One Park Way. The Model 71660 Cobalt architecture features a Virtex-6 FPGA. gate. The Model 71660 is compatible with the VITA 42. In addition to the built-in functions. 31 Pentek. Inc.0 XMC format and supports PCI Express Gen. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. All of the board’s data and control paths are accessible by the FPGA. triggering and memory control. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. DDR3 SDRAM or QDRII+ SRAM memory. The FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters.com • http://www. DDR3 SDRAM. 2. enabling factory installed functions including data multiplexing. LX240T. etc. users can install their own custom IP for data processing. The 71660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM. PCIe. or SX475T. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. SX95T or SX475T LVDS GTX GTX GTX 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 FLASH 32 MB 40 x8 x4 x4 Model 71660 XMC FPGA I/O PCIe VITA 42. 2 bus specifications.com . programmable LVDS I/O and clock. SX315T.Putting FPGAs to Work in Software Radio Systems Products 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA Model 71660 . it is suitable for connection to HF or IF ports of a communications and radar system. and synchronization circuits.XMC RF In RF XFORMR TIMING BUS GENERATOR Clock / Sync / Gate / PPS 16 To All Sections RF In RF XFORMR 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D Sample Clk / Reference Clk In Gate / Trigger Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Aux Clk Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus A/D Clock / Sync Bus 200 MHz 16-BIT A/D 16 16 16 VCXO Control / Status FPGA VIRTEX-6 LX130T. Multiple 71660’s can be driven from the LVPECL bus master. and four banks of memory. gating.x (Aurora.pentek. It includes four 200 MHz 16-bit A/Ds. LX240T. LX365T. or as combination of two banks of each type of memory. supporting synchronous sampling and sync functions across all connected boards. LX365T. PCIe interface. The Model 71660 includes an industry-standard interface fully compliant with PCI Express Gen. Upper Saddle River. The FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. A multichannel.) P16 XMC Optional memory configurations P14 PMC DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB P15 XMC Figure 37 Model 71660 is a member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. Supported FPGAs include: Virtex-6 LX130T.

32 Pentek. it is ideal for wideband applications including radar and spread spectrum communication systems.VME/VXS Model 6821-422 RF Input 50 ohms 215 MHz 12-Bit A/D AD9430 Fs LVDS I/O 128 MB SDRAM 16 MB FLASH Fs/2 Front Panel LVDS Timing Bus CLOCK. 215 MHz A/D converter.25 GB/sec 32 32 FPDP-II Out B Slot 1 FPDP-II Out D Slot 2 32 32 32 32 FPDP-II Out A Slot 1 FPDP-II Out C Slot 2 128k FIFO 128k FIFO Ext Clock In 50 ohms XTAL OSC 16 128k FIFO 128k FIFO 16 VME Slave Interface VMEbus 4x Switched Serial Fabric 1. 12-bit A/D with Wideband DDCs . A VXS interface is optionally available.pentek. Inc. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. memory boards or storage devices.Putting FPGAs to Work in Software Radio Systems Products 215 MHz. DSP algorithms. Upper Saddle River.25 GB/sec Model 6821 VXS Switched Backplane Figure 38 The Model 6821 is a 6U single slot board with the AD9430 12-bit. Instead. Capable of digitizing input signal bandwidths up to 100 MHz. Either two or four FPDP-II ports connect the FPGAs to external digital destinations such as processor boards. The size of the FPGAs can range from the XC2VP20 to the XC2VP50. SYNC & TRIGGER GENERATOR 128 MB SDRAM 16 MB FLASH Control and Status To All Sections 32 XILINX VIRTEX-II PRO FPGA XC2VP50 32 XILINX VIRTEX-II PRO FPGA XC2VP50 64 LVDS I/O 32 32 4x Switched Serial Fabric 1. none are included on the board. the Pentek GateFlow IP Core 422 Ultra Wideband Digital Downconverter can be factory- installed in one or both of the FPGAs to perform this function. one for each FPGA. This Model is available in commercial as well as conduction-cooled versions. Two 128 MB SDRAMs. A VMEbus interface supports configuration of the FPGAs over the backplane and also provides data and control paths for runtime applications.com . • One Park Way. Because the sampling rate is well beyond conventional ASIC digital downconverters. support large memory applications such as swinging buffers. digital filters. The sampling clock can be supplied either from a front panel input or from an internal crystal oscillator. Data from the A/D converter flows into two Xilinx Virtex-II Pro FPGAs where optional signal processing functions can be performed. and digital delay lines for tracking receivers.com • http://www.

com • http://www. This Model is available in commercial as well as conduction-cooled versions.Putting FPGAs to Work in Software Radio Systems Products Dual 215 MHz. it is ideal for wideband applications including radar and spread spectrum communication systems. Because the sampling rate is well beyond conventional ASIC digital downconverters. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. DSP algorithms. Inc.VME/VXS Model 6822-422 RF Input 50 ohms LVDS I/O 128 MB SDRAM 16 MB FLASH 32 XILINX VIRTEX-II PRO FPGA XC2VP50 64 CLOCK GEN Fs/2 RF Input 50 ohms 215 MHz 12-Bit A/D AD9430 128 MB SDRAM 16 MB FLASH Control and Status To All Sections 32 LVDS I/O 32 32 4x Switched Serial Fabric 1. 12-bit A/D with Wideband DDCs .pentek. A VMEbus interface supports configuration of the FPGAs over the backplane and also provides data and control paths for runtime applications. Either two or four FPDP-II ports connect the FPGAs to external digital destinations such as processor boards.25 GB/sec 32 32 FPDP-II Out B Slot 1 FPDP-II Out D Slot 2 32 32 32 32 FPDP-II Out A Slot 1 FPDP-II Out C Slot 2 215 MHz 12-Bit A/D AD9430 Fs LVDS Clock & Sync Bus 128k FIFO 128k FIFO Ext Clock In 50 ohms XTAL OSC 16 16 XILINX VIRTEX-II PRO FPGA XC2VP50 128k FIFO 128k FIFO VME Slave Interface VMEbus 4x Switched Serial Fabric 1. The sampling clock can be supplied either from a front panel input or from an internal crystal oscillator. Upper Saddle River. digital filters. Data from each A/D converter flows into a Xilinx Virtex-II Pro FPGA where optional signal processing functions can be performed. one for each FPGA. • One Park Way. Two 128 MB SDRAMs. and digital delay lines for tracking receivers. the Pentek GateFlow IP Core 422 Ultra Wideband Digital Downconverter can be factory- installed in one or both of the FPGAs to perform this function. none are included on the board. Capable of digitizing input signal bandwidths up to 100 MHz. support large memory applications such as swinging buffers. The size of the FPGAs can range from the XC2VP20 to the XC2VP50.25 GB/sec Model 6822 VXS Switched Backplane Figure 39 The Model 6822 is a 6U single slot VME board with two AD9430 12-bit 215 MHz A/D converters. 33 Pentek. memory boards or storage devices. A VXS interface is optionally available.com . Instead.

NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.Putting FPGAs to Work in Software Radio Systems Products Dual 2 GHz. 34 Pentek. DSP algorithms. 10-bit A/D with Very High-Speed DDCs . This advanced circuit features the Atmel AT84CS001 demultiplexer which represents a significant improvement over previous technology.VME/VXS Model 6826 RF INPUT 50 OHMS 2 GHz 10-Bit A/D AT84AS008 Fs 10 4:1 DEMUX AT84CS001 40 2:1 DEMUX V4 FPGA 512 MB DDR RAM 80 32 128k FIFO 128k FIFO 16 MB FLASH 128k FIFO 128k FIFO 32 FPDP-II 400 MB/sec FPDP-II 400 MB/sec EXT CLOCK INPUT XTAL OSC 64 Fs/4 Fs Fs/8 512 MB DDR RAM 64 XILINX VIRTEX-II PRO FPGA XC2VP70 32 32 16 RF INPUT 50 OHMS 2 GHz 10-Bit A/D AT84AS008 10 4:1 DEMUX AT84CS001 Fs/4 40 2:1 DEMUX V4 FPGA Fs/8 80 32 32 FPDP-II 400 MB/sec FPDP-II 400 MB/sec 32 Fs/8 IN Fs/8 OUT FPGA SYNC IN GATE A IN GATE B IN GATE TRIGGER & SYNC 32 VME SLAVE INTERFACE VMEbus 4x SWITCHED SERIAL FABRIC 1. memory boards or storage devices. Inc. • One Park Way. Because the sampling rate is well beyond conventional digital downconverters. The customer will be able to incorporate this core into the Model 6826 by ordering it as a factory-installed option.25 GB/SEC Model 6826 VXS SWITCHED BACKPLANE Figure 40 The Model 6826 is a 6U single slot VME board with two Atmel AT84AS008 10-bit 2 GHz A/D converters. support large memory applications such as swinging buffers. Capable of digitizing input signals at sampling rates up to 2 GHz. Either two or four FPDP-II ports connect the FPGA to external digital destinations such as processor boards. A VXS interface is optionally available. digital filters. Two 512 MB or 1 GB SDRAMs. none are included on the board. The sampling clock is an externally supplied sinusoidal clock at a frequency from 200 MHz to 2 GHz. and digital delay lines for tracking receivers. This Model is also available in a single-channel version and in commercial as well as conduction-cooled versions.pentek.25 GB/SEC 4x SWITCHED SERIAL FABRIC 1.com .com • http://www. A VMEbus interface supports configuration of the FPGA over the backplane and also provides data and control paths for runtime applications. A very high-speed digital downconverter IP core for the Model 6826 can be developed for a customer who is interested in one. Data from each of the two A/D converters flows into an innovative dual-stage demultiplexer that packs groups of eight data samples into 80-bit words for delivery to the Xilinx Virtex-II Pro XC2VP70 FPGA at one eighth the sampling frequency. it is ideal for extremely wideband applications including radar and spread spectrum communication systems. Upper Saddle River.

com .com • http://www. Sync and Gate Distribution Board Model 6890 . The 6890 features separate inputs for gate/trigger and sync signals with user-selectable polarity. 35 Pentek. The second output of the 1:2 power splitter feeds a 1:2 buffer which distributes the clock signal to both the gate and synchronization circuits. Upper Saddle River. The first output of this power splitter sends the clock signal to a 1:8 splitter for distribution to up to eight boards using SMA connectors. Inc. A 2:1 multiplexer in each circuit allows the gate/ trigger and sync signals to be registered with the input clock signal before output. or from one supported board set to act as the master.2 GHz along with timing signals that can be used for synchronizing.pentek. Separate Gate Enable and Sync Enable inputs allow the user to enable or disable these circuits using an external signal.Putting FPGAs to Work in Software Radio Systems Products 2.2 GHz Clock. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Sets of input and output cables for two to eight boards are available from Pentek. • One Park Way. The 6890 accepts clock input at +10 dBm to +14 dBm with a frequency range from 800 MHz to 2. Clock signals are applied from an external source such as a high performance sine wave generator. Up to eight boards can be synchronized using the 6890. Each of these inputs can be TTL or LVPECL. DSP and software radio applications. A bank of eight MMCX connectors at the output of each buffer delivers signals to up to eight boards. A programmable delay allows the user to make timing adjustments on the gate and sync signals before they are sent to an LVPECL buffer. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition. if desired. Gate and sync signals can come from an external source.VME Front Panel Gate Enable Front Panel Gate Input TTL / PECL SELECTOR GATE CONTROL TTL / PECL SELECTOR PROG DELAY BUFFER 1:2 REG MUX 2:1 LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Gate Ch 6 Output Ch 7 Ch 8 Front Panel Clock Input POWER SPLITTER 1:2 POWER SPLITTER BUFFER 1:2 1:8 Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Clock Ch 6 Output Ch 7 Ch 8 Front Panel Sync Enable Front Panel Sync Input TTL / PECL SELECTOR SYNC CONTROL TTL / PECL SELECTOR REG PROG DELAY BUFFER 1:2 MUX 2:1 LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Sync Ch 6 Output Ch 7 Ch 8 Model 6890 VME Figure 41 Model 6890 Clock. each receiving a common clock of up to 2.2 GHz and uses a 1:2 power splitter to distribute the clock. Sync and Gate Distribution Board synchronizes multiple Pentek I/O boards within a system. triggering and gating functions.

It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition. 36 Pentek.com • http://www. The Sync Bus is distributed through ribbon cables. simplifying system design. The 6891 accepts clock input at +10 dBm to +14 dBm with a frequency range from 1 kHz to 800 MHz.VME Gate Clock Sync Gate to Sync Bus Outputs 2-8 Sync Bus Output 1 Front Panel Gate Enable Front Panel GateInput GATE CONTROL MUX 2:1 PROG DELAY BUFFER 1:2 REG MUX 2:1 GATE LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Clock Sync Gate Clock Sync Gate Clock Sync Sync Bus Output 2 Sync Bus Output 3 Front Panel Clock Input MUX 2:1 CLOCK LVPECL BUFFER 1:10 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Sync Bus Output 4 to Sync Bus Outputs 2-8 Gate Clock Sync Gate Sync Bus Output 5 Front Panel Sync Enable Front Panel Sync Input SYNC CONTROL MUX 2:1 PROG DELAY BUFFER 1:2 REG MUX 2:1 SYNC LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Clock Sync Gate to Sync Bus Outputs 2-8 Sync Bus Output 6 Clock Sync Gate Clock Sync Sync Bus Output 7 Gate Sync Bus Input Clock Sync Sync Bus Output 8 Figure 42 Model 6891 VME Model 6891 System Synchronizer and Distribution Board synchronizes multiple Pentek I/O modules within a system. • One Park Way. Model 6891 accepts three TTL input signals from external sources: one for clock. triggering and gating functions. For larger systems. Up to eight modules can be synchronized using the 6891.Putting FPGAs to Work in Software Radio Systems Products System Synchronizer and Distribution Board Model 6891 . compatible with a wide range of Pentek I/O modules. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Gate/trigger and sync signals can come from an external system source. Two additional inputs are provided for separate gate and sync enable signals. This clock is used to register all sync and gate/trigger signals as well as providing a sample clock to all connected I/O modules. Inc. one for gate or trigger and one for a synchronization signal. DSP and software radio applications. A programmable delay allows the user to make timing adjustments on the gate and sync signals before they are sent to an LVPECL buffer for output through the Sync Bus connectors. sync and gate/trigger signals.pentek. Upper Saddle River. Clock signals can be applied from an external source such as a high performance sine-wave generator. a Sync Bus connector accepts LVPECL inputs from any compatible Pentek products to drive the clock. each receiving a common clock up to 500 MHz along with timing signals that can be used for synchronizing. Alternately.com . up to eight 6891’s can be linked together to provide synchronization for up to 64 I/O modules producing systems with up to 256 channels. The 6891 provides eight front panel Sync Bus output connectors.

thereby allowing any combination of output signals from the four CDC7005s. The five clock output signals from each of the four CDC7005s are joined into five clock buses. Once configured. The 7190 is equipped with a non-volatile memory. 3U VPX board (Model 5390). Each CDC7005 generates five output signals. Each device includes phase-locking circuitry that locks the frequency of its associated quad VCXO (Voltage Controlled Crystal Oscillator) to the input reference clock. Inc. The 7190 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices. 6U cPCI (Models 7290 and 7290D dual density). 4. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. numerous other combinations are possible. PCIe half-length board (Model 7890). Each quad VCXO is programmed to generate one of four base frequencies. 8 or 16. Upper Saddle River. or 3U cPCI (Model 7390). • One Park Way. These clocks are synthesized from an input reference signal using phase-locked oscillators. This supports a single identical clock to all eight outputs or five different clocks to various outputs. Versions of the 7190 are also available as a PCIe fulllength board (Models 7790 and 7790D dual density). as shown in the block diagram. Each output can be independently enabled to drive each bus. PCI board (Model 7690).Putting FPGAs to Work in Software Radio Systems Products Multifrequency Clock Synthesizer Model 7190 PMC ● Model 7290 6U cPCI ● Model 7390 3U cPCI ● Model 7690 PCI Model 7790 Full-length PCIe ● Model 7890 Half-length PCIe ● Model 5390 3U VPX Reference In QUAD VCXO A CLOCK SYNTHESIZER AND JITTER CLEANER A Clock Out 1 Clock Out 2 Clock Out 3 Clock Out 4 Clock Out 5 QUAD VCXO B CLOCK SYNTHESIZER AND JITTER CLEANER B QUAD VCXO C CLOCK SYNTHESIZER AND JITTER CLEANER C Clock Out 6 Clock Out 7 QUAD VCXO D CLOCK SYNTHESIZER AND JITTER CLEANER D NON-VOLATILE CONFIGURATION MEMORY Clock Out 8 Model 7190 PMC Control PCI INTERFACE 32 PCI BUS (32 Bits / 66 MHz) Figure 43 Model 7190 generates up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock buses.pentek. the settings return to the saved configuration upon power up. 37 Pentek.com • http://www. 2. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. This reference is a 5 or 10 MHz signal supplied to a front panel SMC connector.com . Each signal is independently programmable as a submultiple of the associated VCXO base frequency using divisors of 1.

Up to 80 I/O modules can be driven from the Model 9190. triggering and gating functions. 40 to the card cage above and 40 to the card cage below.75 in. Clock LVDS DIFF. Model 9190 is housed in a line-powered.com . multichannel data acquisition. RECEIVER Timing Signals To Module No. Clock and timing signals can come from six front panel SMA user inputs or from one I/O module set to act as the timing signal master.) Alternately.Rack-mount Model 9190 LVDS DIFF. Upper Saddle River. (In this case. • One Park Way. 38 Pentek. Separate cable assemblies extend from openings in the front panel of the 9190 to the front panel clock and sync connectors of each I/O module. Model 9190 can drive a maximum of 80 clock and sync cables. 1. Buffered versions of the clock and five timing signals are available as outputs on the 9190’s front panel SMA connectors. DRIVERS From Module Master Source Front Panel Input SMA Connectors LVDS DIFF. DRIVERS To Module No. the master clock can come from a socketed. high metal chassis suitable for mounting in a standard 19 in.com • http://www. equipment rack. user-replaceable crystal oscillator within the Model 9190. each receiving a common clock and up to five different timing signals which can be used for synchronizing. Inc.pentek. DRIVERS Timing Signals LINE RCVRS Multiplexer Switches Clock Ext. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.Putting FPGAs to Work in Software Radio Systems Products Clock and Sync Generator for I/O Modules Model 9190 . 1 To Module No. 2 Timing Signals LVDS DIFF. Fewer cables may be installed for smaller systems. Mounted between two standard rack-mount card cages. 80 OPTIONAL INTERNAL OSCILLATOR LINE DRIVERS Front Panel Output SMA Connectors Figure 44 Model 9190 Clock and Sync Generator synchronizes multiple Pentek I/O modules within a system to provide synchronous sampling and timing for a wide range of high-speed. DSP and software radio applications. the master I/O module will not be synchronous with the slave modules due to delays through the 9190. either above or below the cage holding the I/O modules.

Built on the Windows XP professional workstation. signal processing. 6. 1. The Pentek RTS 2701 serves equally well as a development platform for advanced research projects and proofof-concept prototypes. Included with this instrument is Pentek’s SystemFlow recording software. 5.pentek. Inc. • One Park Way.com • http://www. The core also includes an interpolation filter that expands the interpolation factor of the ASIC DUC. it utilizes the Model 7641-420 multiband transceiver PCI module with two 14-bit 125 MHz A/Ds. including 0. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Multiple RAID levels. A high-performance PCI Express SATA RAID controller connects to multiple SATA hard drives to support storage to 4 terabytes and real-time sustained recording rates to 480 MB/sec. 39 Pentek. and waveform generation. The factory-installed IP core 420 provides a dual wideband DDC and expands the decimation range of the ASIC DDC. and DUC with two 16-bit 500 MHz D/As. or as a cost-effective strategy for deploying high-performance. ASIC DDC.The RTS 2701 uses a native NTFS record/playback file format for easy access by user applications for analysis. Upper Saddle River.0 CH 1 OUT 500 MHz 16-BIT D/A DIGITAL UP CONVERTER PS/2 KEYBOARD RAID CONTROLLER PS/2 MOUSE CLK A IN CLK B IN TTL GATE/ TRIG IN SAMPLE CLOCK AND SYNC GENERATOR MODEL 7641-420 TRANSCEIVER AUX VIDEO OUT XTAL OSC A XTAL OSC B CLOCK SYNC BUS DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES RAID ARRAY PENTEK RTS 2701 RECORDER - Figure 45 The Pentek RTS 2701 is a highly scalable recording and playback system in an industrial rack-mount PC server chassis. provide a choice for the required level of redundancy.com . File headers include recording parameter settings and time stamping so that the signal viewer correctly formats and annotates the displayed signals. The Model 7641-420 combines downconverter and upconverter functions in one PCI module and offers recording and playback capabilities. 10 and 50.Putting FPGAs to Work in Software Radio Systems Products Rack-mount Real-Time Recording and Playback Transceiver Instrument Model RTS 2701 CH 1 IN 125 MHz 14-BIT A/D DIGITAL DOWN CONVERTER DIGITAL DOWN CONVERTER DDR SDRAM INTEL SYSTEM DRIVE PROCESSOR GIGABIT ENET CH 2 IN 125 MHz 14-BIT A/D USB 2. multichannel embedded systems.

2 TB arrays. Inc. • One Park Way. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com . A total of 4 TB of RAID storage is provided. Built on a Windows XP Professional workstation. The RTS 2703 provides sustained. The total drive capacity is 4 TB using 10 drives. 40 Pentek. The front end of the RTS 2703 consists of two Pentek Model 7850 PCIe modules each equipped with 200 MHz 16-bit A/D converters. one array for each A/D channel. aggregate recording rates of up to 800 MB/sec. including 0. users can install post processing and analysis tools to operate on the recorded data. Reference TIMING BUS GENERATOR Model 7850 DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES VCXO RAID Array PENTEK RTS 2703 Figure 46 The Pentek RTS 2703 is a turnkey recording instrument that allows the user to record and analyze two highbandwidth signals. forming a powerful dual-channel 4U rack-mount recording system. The RTS 2703 features a Windows- based GUI (graphical user interface) providing a simple means to configure and control the instrument. Pentek’s RTS 2703 provides a flexible architecture that can be easily customized to meet user needs. providing immediate access to the recorded data. provide a choice for the required level of redundancy. 1 and 5. recording two signals at up to 200 MSamples/sec. allowing sustained 2 TB recordings at 200 MSamples/sec simultaneously on each of two channels for over one hour. Multiple RAID levels. Custom configurations can be stored as profiles and later retrieved for easy selection of pre-configured settings with a single click. Upper Saddle River.com • http://www. Included with this instrument is Pentek’s SystemFlow Recording Software. The RTS 2703 records data to the native NTFS file system. The RTS 2703 retains all 16 bits of each A/D sample (2 bytes).Putting FPGAs to Work in Software Radio Systems Products 2-Channel 200 MSample/sec Real-Time Recorder Instrument Model RTS 2703 CH 1 IN 200 MHz 16-BIT A/D INTEL GIGABIT ETHERNET Sample Clock In Ext. Reference TIMING BUS GENERATOR PROCESSOR USB Model 7850 SYSTEM DRIVE VCXO PS/2 MOUSE DDR SDRAM PS/2 KEYBOARD Host Processor VIDEO OUT CH 2 IN 200 MHz 16-BIT A/D Sample Clock In Ext. which are organized as two 5-drive.pentek.

allowing sustained 2 TB recordings at 500 megasamples per second simultaneously on each of two channels for over one hour.Putting FPGAs to Work in Software Radio Systems Products 2-Channel 500 MSample/sec Real-Time Recorder Instrument Model RTS 2711 CH 1 IN 500 MHz 12-BIT A/D INTEL GIGABIT ETHERNET Sample Clock In Ext. Custom configurations can be stored as profiles and later retrieved for easy selection of preconfigured settings with a single click. The total drive capacity is 4 TB using 16 drives which are organized as two 8-drive. Reference TIMING BUS GENERATOR PROCESSOR USB Model 7858 SYSTEM DRIVE VCXO PS/2 MOUSE DDR SDRAM PS/2 KEYBOARD Host Processor VIDEO OUT CH 2 IN 500 MHz 12-BIT A/D Sample Clock In Ext. Pentek’s RTS 2711 provides a flexible architecture that can be easily customized to meet user needs. The RTS 2711 features a Windows- based GUI (graphical user interface) that provides a simple means to configure and control the instrument. Reference TIMING BUS GENERATOR Model 7858 DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES VCXO RAID Array PENTEK RTS 2711 Figure 47 The Pentek RTS 2711 is a turnkey recording instrument that allows the user to record and analyze two highbandwidth signals. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. users can install post-processing and analysis tools to operate on the recorded data. Included with this instrument is Pentek’s SystemFlow Recording Software. 2-TB arrays. A total of 4 TB of RAID storage is provided. The RTS 2711 retains the eight most significant bits of each A/D sample to record two signals at 500 megasamples per second. including 0. The front end of the RTS 2711 consists of two Pentek Model 7858 PCIe modules equipped with 500 MHz 12-bit A/D converters. providing immediate access to the recorded data.pentek.com . Built on a Windows XP Professional workstation. Inc. one for each A/D channel. The RTS 2711 records data to the native NTFS file system. 1. Multiple RAID levels. The RTS 2711 provides sustained. 10 and 50 provide a choice for the required level of redundancy. Upper Saddle River. • One Park Way. 41 Pentek.com • http://www. 5. aggregate recording rates of up to 1 GB/sec forming a powerful dual-channel 4U rack-mount recording system. 6.

A high-performance PCI Express SATA RAID controller connects to multiple SATA hard drives to support storage to 3 terabytes and real-time sustained recording rates up to 480 MB/sec. Fully supported by Pentek’s SystemFlow recording software. • One Park Way. The factory-installed IP core 420 provides a dual wideband DDC and expands the decimation range of the ASIC DDC. signal processing. 10 and 50. The Model 7641-420 combines downconverter and upconverter functions in one PCI module and offers real-time recording capabilities. 1. File headers include recording parameter settings and time stamping so that the signal viewer correctly formats and annotates the displayed signals. Inc.pentek. ASIC DDC.Putting FPGAs to Work in Software Radio Systems Products Portable Real-Time Recording and Playback Transceiver Instrument Model RTS 2721 CH 1 IN 125 MHz 14-BIT A/D DIGITAL DOWN CONVERTER DIGITAL DOWN CONVERTER GIGABIT ENET HIGH RESOLUTION VIDEO DISPLAY USB 2. it includes a dual-core Xeon processor. 6. Multiple RAID levels. and waveform generation. The core also includes an interpolation filter that expands the interpolation factor of the ASIC DUC.0 DDR SDRAM INTEL SYSTEM DRIVE PROCESSOR PS/2 MOUSE PS/2 KEYBOARD CH 2 IN 125 MHz 14-BIT A/D CH 1 OUT 500 MHz 16-BIT D/A DIGITAL UP CONVERTER CLK A IN CLK B IN TTL GATE/ TRIG IN TTL SYNC IN SAMPLE CLOCK AND SYNC GENERATOR MODEL 7641-420 TRANSCEIVER RAID CONTROLLER AUX VIDEO OUT XTAL OSC A XTAL OSC B CLOCK SYNC BUS DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES RAID ARRAY PENTEK RTS 2721 RECORDER - Figure 48 The Pentek RTS 2721 is a turnkey real-time recording and playback instrument supplied in a convenient briefcase-size package that weighs just 30 pounds. provide a choice for the required level of redundancy. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 42 Pentek. a high-resolution 17-inch LCD monitor and a high-performance SATA RAID controller. the RTS 2721 uses a native NTFS record/playback file format for easy access by user applications for analysis. Built on the Windows XP professional workstation. 5. Pentek’s portable recorder instrument provides a flexible architecture that is easily customized to meet special needs.com . With its wide range of programmable decimation and interpolation. the system supports signal bandwidths from 8 kHz to 60MHz. The RTS 2721 utilizes the Model 7641 multiband transceiver PCI module with two 14-bit 125 MHz A/Ds.com • http://www. including 0. Upper Saddle River. and DUC with two 16-bit 500 MHz D/As.

Inc. and for monitoring signals as they are being recorded to help ensure successful recording sessions. With time and frequency zoom. 43 Pentek. second and third harmonic components. decimation. the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field. The user can easily move between screens to set configuration parameters.com . as well as gate and trigger information.com • http://www. Upper Saddle River. THD (total harmonic distortion) and SINAD (signal to noise and distortion). record. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency.pentek. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. panning modes and dual annotated cursors to mark and measure points of interest. play back a recorded signal and monitor board temperatures and voltage levels.Putting FPGAs to Work in Software Radio Systems Products Pentek SystemFlow® Recording Software Model 4990 Recorder Interface Hardware Configuration Interface Signal Viewer Figure 49 The Model 4990 SystemFlow Recording Software provides a rich set of function libraries and tools for controlling all Pentek RTS real-time data acquisition and recording instruments. each with intuitive controls and indicators. The Hardware Configuration Interface provides entries for input source. SystemFlow software allows developers to configure and customize system interfaces and behavior. control and monitor a recording. The viewer can also be used to inspect and analyze the recorded files after the recording is complete. center frequency. It is extremely useful for previewing live inputs prior to recording. playback and status screens. • One Park Way. The Recorder Interface includes configuration.

DDC. Direction finding and beamforming are ideal applications for digital receivers because of their excellent channel-to-channel phase and gain matching and consistent delay characteristics. Cellular phone applications are one of the strongest high-volume applications because of the high density of tightly-packed frequency division multiplexed voice channels. DUC.com . and DSP functions to process wideband signals.com • http://www. any system requiring a tunable bandpass filter should be considered a candidate for using DDCs. Take a look at the following application examples to give you some more details. Signal intelligence applications and radar benefit from the tight coupling of the A/D.Putting FPGAs to Work in Software Radio Systems Applications Applications of FPGAs in Software Radio Systems ● ● ● ● ● Tracking Receiver System Software Radio Transceiver System 512-Channel SDR System in a single VMEbus Slot Radar Signal Processing System 8-Channel Beamforming System Software Radio can be used in many different systems: Tracking receivers can be highly automated because software radio allows DSPs to perform the signal identification and analysis functions as well as the adaptable tuning functions. Upper Saddle River. 44 Pentek. Inc.pentek. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. • One Park Way. As a general capability.

As shown above. across a VXS link.com • http://www. This Model is also available in a dual-channel version as Model 6822. The digital delay can be set to match the time it takes for the FFT energy detection and the processor algorithm for the tuning frequency decision. Inc. The PowerPC microcontroller of the FPGA digests this frequency list and decides which signals to track. optionally. 45 Pentek. The dehopped baseband output is delivered to the rest of the system through the FPDP port or. The delayed data from the circular buffer feeds the input of this DDC core. locks onto them and tracks them if their frequency changes. so that frequency-agile or transient signals can be recovered from their onset. It then tunes the Pentek DDC core. accordingly. also implemented in the FPGA.Putting FPGAs to Work in Software Radio Systems Applications Tracking Receiver System 215 MHz 12-Bit A/D AD9430 128 MB SDRAM Delayed Data FPGA FFT IP CORE Peaks Power PC Controller Tuning DDC CORE 32 FIFO 32 16 MB FLASH Model 6821 215 MHz A/D Converter with FPGA System Highlights ● ● ● ● ● ● ● A/D data delivered into SDRAM acts as a digital delay memory A/D data also delivered into a Pentek FFT IP core in FPGA FFT core detects the strength of signals at each analysis frequency PowerPC controller in FPGA sorts signals according to peak strenth PowerPC controller also tunes DDC IP core in FPGA to the strongest signal frequencies Delayed data from SDRAM feeds DDC IP core to compensate for FFT calculation time DDC captures these moving signals in real time and downconverts them to baseband Figure 50 Model 6821 commercial (left) and conduction-cooled version A tracking receiver locates unknown signals. • One Park Way. The spectral peaks of the FFT indicate the frequencies of signals of interest present at the input. Upper Saddle River.pentek. to implement this receiver. Both Models are available in commercial and conduction-cooled versions.com . Samples from the A/D are sent into a circular buffer within the SDRAM and also to a Pentek FFT IP core implemented in the FPGA. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. we use the 128 MB SDRAM of the Model 6821 to create a delay memory function.

Inc. Upper Saddle River. plus a Virtex-II VP-50 FPGA on each PMC module. It can also be used as a pre. Signal processing resources include the Freescale MPC8641 AltiVec processor and an FX60 or FX100 Virtex-4 FPGA on the Model 4207 I/O processor.Putting FPGAs to Work in Software Radio Systems Applications 4-Channel Software Radio Transceiver System CH A OUT 500 MHz 16bit D/A CH B OUT PENTEK Model 7141 320 MHz DUC 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 PENTEK Model 7141 125 MHz 14bit A/D 125 MHz 14bit A/D CH A IN CH B IN CH A IN CH B IN 125 MHz 14bit A/D 125 MHz 14bit A/D 320 MHz DUC 32 CH A OUT 500 MHz 16bit D/A CH B OUT 32 XILINX VIRTEX-II PRO VP50 4 CLK A DUAL TIMING BUS GEN CLK A CLK B CLOCK & SYNC BUS DUAL TIMING BUS GEN CLK B CLOCK & SYNC BUS XILINX VIRTEX-II PRO VP50 4 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 32 32 64 4 QUAD DDC GC4106 16 MB FLASH QUAD DDC GC4106 16 MB FLASH 4 64 PCI INTERFACE PCI 32 32 PCI INTERFACE PCI P14 PENTEK Model 4207 Front Panel Optical Interface To VME P2 XMC // XMC PMC Site PMC Site MPC8641 Single/Dual Core FLASH 32 MB FLASH 256 MB DDR2 SDRAM 1 GB Dual 1000BT Enet Quad RS232C XMC XMC // PMC Site PMC Site PCI-X Bus 0 (64 Bits. 46 Pentek.and post-processing I/O front end for sending and receiving data to other system boards connected over the VMEbus or through switched fabric links using the VXS interface. Ruggedized and conduction-cooled versions of the boards used in this system are available. A total of eight DDC channels are independently tunable across the input band and can deliver downconverted output signal bandwidths from audio up to 2.pentek.5 MHz. The system supports four independent D/A channels or two upconverted channels with real or quadrature outputs.com • http://www.com . 100 MHz) SRIO 4x 8x PCI-X Bus 1 (64 Bits. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Four analog outputs can deliver baseband or IF signals with bandwidths up to about 50 MHz and IF center frequencies up to 100 MHz. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller Dual 4x 2x Zero Latency Crossbar Switch Dual 4x 2x Dual 4x VME64x 2eSST Gigabit ENET-x Dual 4x Virtex-4 FPGA XC4VFX60 / FX100 FLASH 32 MB DDR2 SDRAM 1 GB 2x VME64x VXS VITA 41 FLASH 128 MB Figure 51 This system accepts four analog inputs from baseband or IF signals with bandwidths up to 50 MHz and IF center frequencies up to 150 MHz. Using these on-board processing resources this powerful system can process analog input data locally and deliver it to the analog outputs. • One Park Way.

A SystemFlow signal viewer on the PC allows previewing of data prior to recording and viewing of recorded data files in both time and frequency domains.Putting FPGAs to Work in Software Radio Systems Applications 512-Channel Software Radio Recording System in a Single VMEbus Slot CH A OUT 500 MHz 16bit D/A CH B OUT PENTEK Model 7141-430 320 MHz DUC 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 PENTEK Model 7141-430 125 MHz 14bit A/D 125 MHz 14bit A/D CH A IN CH B IN CH A IN CH B IN 125 MHz 14bit A/D 125 MHz 14bit A/D 320 MHz DUC 32 CH A OUT 500 MHz 16bit D/A CH B OUT XILINX VIRTEX-II PRO VP50 IP CORE IP CORE 430 430 256-CHAN 256-CHAN DIGITAL DIGITAL DOWN DOWN CONVERTER CONVERTER 4 4 CLK A DUAL TIMING BUS GEN CLK A CLK B CLOCK & SYNC BUS DUAL TIMING BUS GEN XILINX VIRTEX-II PRO VP50 IP CORE 430 4 4 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 CLK B CLOCK & SYNC BUS 32 32 32 64 QUAD DDC GC4106 16 MB FLASH JBOD Disk Array QUAD DDC GC4106 16 MB FLASH PCI INTERFACE PCI 256-CHAN DIGITAL DOWN CONVERTER 64 PCI INTERFACE 32 32 PCI P14 2x Front Panel Optical Interface PENTEK Model 4207 MPC8641 Single/Dual Core Dual 1000BT Enet Quad RS232C To VME P2 XMC // XMC PMC Site PMC Site FLASH 32 MB FLASH 256 MB DDR2 SDRAM 1 GB XMC XMC // PMC Site PMC Site PCI-X Bus 0 (64 Bits.com . Inc.com • http://www. • One Park Way. The GUI executes on a Windows host PC connected to the 4207 via Ethernet.pentek. This system is ideal for downconverting and capturing real time signal data from a very large number of channels in an extremely compact. Either one of the two 14-bit A/D converters operating at 125 MHz sample rate can feed this core producing a range of output bandwidths from 10 kHz to 100 kHz. 100 MHz) SRIO 8x 8x PCI-X Bus 1 (64 Bits. Upper Saddle River. Each channel provides independent tuning frequency with a global decimation from 1024 to 9984. Files can be moved between the Fibre Channel disk and the PC over Ethernet. Pentek’s SystemFlow® software presents an intuitive graphical user interface (GUI) to set up the DDC channels and recording mode. A dual 4-Gbit Fibre Channel copper interface allows wideband A/D data or DDC outputs from all 512 channels to be recorded in real time to a RAID or JBOD disk array at aggregate rates up to 640 MB/sec. low cost system. 47 Pentek. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller Dual 4x 2x Zero Latency Crossbar Switch Dual 4x 2x Dual 4x VME64x 2eSST Gigabit ENET-x Dual 4x Virtex-4 FPGA XC4VFX60 / FX100 32 MB FLASH FLASH 128 MB 2x DDR2 SDRAM 1 GB VME64x VXS VITA 41 Figure 52 Each Model 7141 PMC features the Xilinx Virtex-II Pro VP50 with a Pentek 256-Channel Digital Downconverter (DDC) IP Core 430. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.

com • http://www. Upper Saddle River. 48 Pentek. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller Dual 4x 2x Zero Latency Crossbar Switch Dual 4x 2x Dual 4x VME64x 2eSST Gigabit ENET-x Dual 4x Virtex-4 FPGA XC4VFX60 / FX100 32 MB FLASH 2x DDR2 SDRAM 1 GB VME64x VXS VITA 41 FLASH 128 MB Figure 53 Radar is well served by high-speed A/D converters and wideband digital downconverters.Putting FPGAs to Work in Software Radio Systems Applications Radar Signal Processing System PENTEK Model 7142-428 CH A IN CH B IN 125 MHz 14bit A/D 125 MHz 14bit A/D 125 MHz 14bit A/D 125 MHz 14bit A/D DUAL TIMING BUS GEN CH A OUT CH C IN CH D IN XILINX VIRTEX-4 FPGA With 4-chan. the A/D converters can digitize baseband signals with bandwidths up to 50 MHz. and spoofing deceives radars by making it seem that the target is a different shape. • One Park Way. This is especially useful for a jet or UAV to prevent it from getting shot down. data may be processed by custom user-defined algorithms before it is sent across the VXS interface for recording and off-line processing. After frequency translation and filtering. Jamming blasts energy that disables radars. direction or distance by using DSP techniques. The channelized system shown above. Factory-installed IP cores such as pulse compression and FFT are available and can be factory installed in this FPGA. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 100 MHz) SRIO 4x 8x PCI-X Bus 1 (64 Bits. Operating at sampling rates up to 125 MHz. Note that one more PMC/XMC site is available for installation of an additional module.com . DDC & Interpol. Filter 320 MHz DUC 32 500 MHz 16bit D/A 256 MB SDRAM 256 MB SDRAM 256 MB SDRAM 32 32 CLK A CLOCK & SYNC BUS 96 64 VIRTEX-4 FPGA FX60 or FX100 I/O PCI XMC 16 MB FLASH 32 PENTEK Model 4207 XMC // XMC PMC Site PMC Site Front Panel Optical Interface P14 Dual 4x Dual 1000BT Enet Quad RS232C MPC8641 Single/Dual Core FLASH 32 MB FLASH 256 MB DDR2 SDRAM 1 GB XMC XMC // PMC Site PMC Site To VME P2 PCI-X Bus 0 (64 Bits. The upconverter with the interpolation filter can be used to generate arbitrary radar pulse waveforms that can be used to calibrate the system. such as jamming or spoofing. takes advantage of a Model 7142-428 multichannel transceiver with an installed FPGA core that includes four wideband DDCs and an interpolation filter. Inc. Here. The D/A output can also be used for countermeasures. speed.pentek. the DDCs deliver complex (I & Q) data to the Model 4207 processor board. The optional GateFlow FPGA Design Kit can be used to install custom algorithms in the Model 4207 FPGA.

100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller 4x 4x 4x Virtex-4 FPGA 4x Gigabit ENET-x 2x Dual 4x VXS VITA 41 Aurora Engine FLASH 32 MB FLASH 128 MB 2x Zero Latency Crossbar Switch VME64x 2eSST PCI-X Interface DDR2 SDRAM 1 GB VME64x Figure 54 Two Model 7153 Beamformer PMC/XMC modules are installed on the Model 4207 I/O Processor board.pentek.25 GBytes/sec.com • http://www. The left 4-channel sum is connected through the crossbar switch and delivered into the summation input port of the right XMC module. The summation output from the left XMC module is delivered using the Aurora 4x link into one port of the crossbar switch. The Aurora summation from the left four channels is combined with the right four channels and then delivered to the crossbar switch from the right summation output port. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Upper Saddle River. • One Park Way. The eight signals to be beamformed are connected to the eight analog inputs of these modules. 100 MHz) Front Panel Serial I/O 2x 4x 4x SRIO 4x 8x PCI . The PCI-X interface in this FPGA presents the SDRAM memory as a mapped resource appearing on the processor PCI-X bus 1. The eight-channel combined sum is delivered through the crossbar switch into the Aurora engine implemented in the Virtex-4 FPGA of the 4207 processor board.X Bus 1 (64 Bits. This Aurora engine decodes the stream and delivers it to a designated block in the DDR2 memory attached to the FPGA. signals from the second four channels of the right 7153 are summed in the right summation block. Inc.com . The Power PC reads the data from the FPGA DDR2 memory across the PCI-X bus. Each red 4x link is capable of data rates up to 1. creates the beamformed pattern display and presents it via its front panel gigabit Ethernet port to an attached PC for display. 49 Pentek. Joining the two 7153 modules is a clock/sync cable that synchronizes the DDCs and guarantees synchronous sampling across all eight channels. Signals from the first four channels of the left 7153 module are summed in the left summation block.Putting FPGAs to Work in Software Radio Systems Applications 8-Channel Beamforming System PENTEK Model 7153 DDC 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D DUAL TIMING BUS GEN Clock/Sync Cable CH A IN CH B IN CH A IN CH B IN PENTEK Model 7153 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D DUAL TIMING BUS GEN DDC SUMMATION BLOCK DDC DDC S CH C IN CH D IN CH C IN SUMMATION BLOCK DDC DDC S CH D IN DDC DDC VIRTEX-5 FPGAs PCI-X Aurora P15 CLK A CLOCK & SYNC BUS CLK A CLOCK & SYNC BUS VIRTEX-5 FPGAs PCI-X Aurora PENTEK Model 4207 MPC8641 Single/Dual Core FLASH 32 MB FLASH 256 MB Dual 1000BT Enet P15 To VME P2 XMC // XMC PMC Site PMC Site XMC XMC // PMC Site PMC Site DDR2 SDRAM 1 GB PCI-X Bus 0 (64 Bits.

accept PMC mezzanines and include built-in Fibre Channel interfaces. facilitates system requirement changes and performance upgrades. 50 Pentek. We encourage you to contact your Pentek sales engineers today to discuss your system needs. FPGAs are truly an integral part of the latest generation of software radio products. decryption. such as Serial RapidIO.diversity receivers Analysis: FFTs. circular buffers Formatting and Packing: flexible data manipulation for special I/O. Furthermore. Upper Saddle River. phased array processing. PCI. The Models 4292 and 4293 processor boards feature the Texas Instruments latest TMS320C6000 family of fixed-point DSPs that represent a 10-fold increase in processing power over previous designs. triggering and timing aspects of high-performance real time systems.pentek. statistical analysis Triggering and Gating: radar aquisition and control Memory control: DMA engines. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. dramatic increases in system density have been coupled with a significantly lower cost per channel.Putting FPGAs to Work in Software Radio Systems Summary DSP Boards for VMEbus FPGAs and SDR ● ● ● ● ● ● Freescale Altivec G4 PowerPC Texas Instruments C6000 DSPs Single. PCI Express Figure 56 ● Pentek offers a comprehensive array of VMEbus DSP boards featuring the AltiVec G4 PowerPC from Freescale and the TMS320C6000 family of processor products from Texas Instruments. PCIe. • One Park Way. Inc. symbol recovery Beamforming: direction finding. decoding. Not only are they being used with traditional digital signal processing algorithms but also in the management of data acquisition. PMC/XMC. Pentek offers not only a wide range of hardware products featuring the latest FPGAs. Full software development tools are available for workstations running Windows and Linux with many different development system configurations available. The Models 4205 and 4207 I/O processor boards feature the latest G4 PowerPCs. the ability of the system designer to freely choose the most appropriate DSP processor for each software radio application. packet extraction and formation High-Speed Interfaces: switched serial fabric interfaces. The Models 4294 and 4295 processor boards feature four MPC74xx G4 PowerPC processors utilizing the AltiVec vector processor capable of delivering several GFLOPS of processing power. And be sure to visit our extensive web site for the latest product and technical information. but also the FPGA development resources and knowledgeable applications engineers to help you get the most out of these products. On-board processor densities range from one to eight DSPs with many different memory and interface options available. demodulation.com • http://www. buffering. As we have seen. Dual.com . and cPCI peripherals VME/VXS platforms Figure 55 ● ● ● ● ● Communications Algorithms: DDC. Quad and Octal Processor versions PMC. Once again. FPGA technology allows one to incorporate custom algorithms right at the front end of these systems. With the addition of FPGA technology. DUC.

3U VPX Page 16 16 16 16 16 17 17 17 17 18 18 18 18 19 19 19 19 20 20 20 20 20 20 20 20 21 21 21 21 21 21 21 22 22 22 22 22 22 22 More links on the next page ➤ 51 Pentek. Dual Wideband DDC and Interpolation Filter .Half-length PCIe Transceiver w.6U cPCI Transceiver w.3U VPX Transceiver w.6U cPCI Transceiver w.3U cPCI Multiband Receiver . 256-Channel Narrowband DDC .PMC/XMC Conduction-cooled Multiband Transceiver with Virtex-II FPGA . 256-Channel Narrowband DDC .6U cPCI Multiband Transceiver with Virtex-II Pro FPGA .PMC/XMC Transceiver w. Dual Wideband DDC and Interpolation .3U VPX Transceiver w. Links are also provided to other handbooks or brochures that may be of interest in your software radio development projects. Upper Saddle River.Putting FPGAs to Work in Software Radio Systems Links The following links provide you with additional information about the Pentek products presented in this handbook: just click on the Model number. 256-Channel Narrowband DDC . Dual Wideband DDC and Interpolation Filter .3U cPCI Transceiver w.6U cPCI Multiband Receiver . Inc.Full-length PCIe Multiband Transceiver with Virtex-II Pro FPGA .PCI Transceiver w. Dual Wideband DDC and Interpolation Filter .PMC/XMC Multiband Transceiver with Virtex-II Pro FPGA .6U cPCI Transceiver w.PMC/XMC Transceiver w. 256-Channel Narrowband DDC . Dual Wideband DDC and Interpolation Filter . Dual Wideband DDC and Interpolation .3U cPCI Multiband Transceiver with Virtex-II Pro FPGA . 256-Channel Narrowband DDC .PMC/XMC Multiband Transceiver with Virtex-II Pro FPGA .PCI Multiband Receiver .PCI Transceiver w.PCI Multiband Transceiver with Virtex-II Pro FPGA . Model 7131 7231 7331 7631A 5331 7140 7240 7340 7640 7140-420 7240-420 7340-420 7640-420 7140-430 7240-430 7340-430 7640-430 7141 7141-703 7241 7341 7641 7741 7841 5341 7141-420 7241-420 7341-420 7641-420 7741-420 7841-420 5341-420 7141-430 7241-430 7341-430 7641-430 7741-430 7841-430 5341-430 Description Multiband Receiver .PCI Multiband Transceiver with Virtex-II Pro FPGA .Half-length PCIe Multiband Transceiver with Virtex-II Pro FPGA . Dual Wideband DDC and Interpolation Filter .3U cPCI Transceiver w. Dual Wideband DDC and Interpolation Filter . 256-Channel Narrowband DDC . Dual Wideband DDC and Interpolation . 256-Channel Narrowband DDC . 256-Channel Narrowband DDC .com .Full-length PCIe Transceiver w.6U cPCI Transceiver w. 256-Channel Narrowband DDC . NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.PMC/XMC Transceiver w.3U cPCI Transceiver w.3U cPCI Transceiver w. • One Park Way.3U VPX Multiband Transceiver with Virtex-II Pro FPGA .PCI Transceiver w. 256-Channel Narrowband DDC .3U cPCI Multiband Transceiver with Virtex-II Pro FPGA .6U cPCI Multiband Transceiver with Virtex-II Pro FPGA . 256-Channel Narrowband DDC .Half-length PCIe Transceiver w. Dual Wideband DDC and Interpolation Filter .PMC Multiband Receiver .com • http://www.pentek.Full-length PCIe Transceiver w. Dual Wideband DDC and Interpolation Filter .PMC/XMC Transceiver w.PCI Transceiver w.

pentek.3U cPCI 32-Channel DDC with Quad 200 MHz. Virtex-5 FPGAs . Four Multiband DDCs and Interpolation Filter . 400 MHz A/D.Full-length PCIe Dual SDR Transceiver.6U cPCI Multichannel Transceiver w. 800 MHz D/A.Full-length PCIe 32-Channel DDC with Quad 200 MHz. 16-bit A/D .PCI Dual SDR Transceiver. 16-bit A/D .PMC/XMC Multichannel Transceiver with Virtex-4 FPGAs .PMC 32-Channel DDC with Quad 200 MHz.Full-length PCIe 256-Channel DDC with Quad 200 MHz.3U VPX 32-Channel DDC with Quad 200 MHz. 400 MHz A/D. 16-bit A/D . 400 MHz A/D.Half-length PCIe Multichannel Transceiver with Virtex-4 FPGAs .3U VPX 256-Channel DDC with Quad 200 MHz.3U VPX Dual SDR Transceiver. Virtex-5 FPGAs .3U cPCI Multichannel Transceiver with Virtex-4 FPGAs .PMC/XMC 4-Channel DDC with Quad 200 MHz. 16-bit A/D .PCI Multichannel Transceiver w. 400 MHz A/D.Full-length PCIe Multichannel Transceiver with Virtex-4 FPGAs . 400 MHz A/D. Virtex-5 FPGAs . 16-bit A/D .6U cPCI 256-Channel DDC with Quad 200 MHz. • One Park Way.Half-length PCIe Dual SDR Transceiver.PCI Multichannel Transceiver with Virtex-4 FPGAs . 16-bit A/D .6U cPCI 4-Channel DDC with Quad 200 MHz. 16-bit A/D . 16-bit A/D .Half-length PCIe 256-Channel DDC with Quad 200 MHz. 800 MHz D/A. 16-bit A/D . 16-bit A/D . 16-bit A/D . 16-bit A/D .3U VPX 4-Channel DDC with Quad 200 MHz.PMC/XMC Multichannel Transceiver w.PCI 32-Channel DDC with Quad 200 MHz. Virtex-5 FPGAs . 16-bit A/D .Full-length PCIe 4-Channel DDC with Quad 200 MHz.PMC/XMC Dual SDR Transceiver. 800 MHz D/A. Four Multiband DDCs and Interpolation Filter. Four Multiband DDCs and Interpolation Filter. 16-bit A/D . 16-bit A/D . 16-bit A/D . Upper Saddle River.6U cPCI Multichannel Transceiver with Virtex-4 FPGAs . 16-bit A/D .Half-length PCIe 32-Channel DDC with Quad 200 MHz. Virtex-5 FPGAs . 16-bit A/D . Four Multiband DDCs and Interpolation Filter. 16-bit A/D . Four Multiband DDCs and Interpolation Filter. Virtex-5 FPGAs . 400 MHz A/D.com • http://www.3U VPX More links on the next page ➤ 52 Pentek.PMC 256-Channel DDC with Quad 200 MHz.Half-length PCIe 4-Channel DDC with Quad 200 MHz. 800 MHz D/A.6U cPCI 32-Channel DDC with Quad 200 MHz. 400 MHz A/D.6U cPCI Dual SDR Transceiver.Half-length PCIe Multichannel Transceiver w.Full-length PCIe Multichannel Transceiver w.3U cPCI Dual SDR Transceiver. Four Multiband DDCs and Interpolation Filter.PCI 4-Channel DDC with Quad 200 MHz.PCI 256-Channel DDC with Quad 200 MHz. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 16-bit A/D .com .3U cPCI 256-Channel DDC with Quad 200 MHz. 16-bit A/D . Inc.Putting FPGAs to Work in Software Radio Systems Links Model 7142 7242 7342 7642 7742 7842 5342 7142-428 7242-428 7342-428 7642-428 7742-428 7842-428 5342-428 7151 7251 7351 7651 7751 7851 5351 7152 7252 7352 7652 7752 7852 5352 7153 7253 7353 7653 7753 7853 5353 7156 7256 7356 7656 7756 7856 5356 Description Page 23 23 23 23 23 23 23 24 24 24 24 24 24 24 25 25 25 25 25 25 25 26 26 26 26 26 26 26 27 27 27 27 27 27 27 28 28 28 28 28 28 28 Multichannel Transceiver with Virtex-4 FPGAs . 800 MHz D/A.3U cPCI 4-Channel DDC with Quad 200 MHz. 800 MHz D/A. 800 MHz D/A. Virtex-5 FPGAs .3U VPX Multichannel Transceiver w.3U cPCI Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter.

Virtex-5 FPGAs .VME/VXS Dual 2 GHz 10-bit A/D . Virtex-5 FPGAs . 12-bit A/D with Wideband DDCs .6U cPCI Multifrequency Clock Synthesizer . 500 MHz A/D.pentek. 500 MHz A/D. 500 MHz A/D. 500 MHz A/D.PMC Multifrequency Clock Synthesizer . 2-Channel 800 MHz D/A.com . Virtex-6 FPGA 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA .VME/VXS 2. Inc. 500 MHz A/D. 500 MHz A/D.6U cPCI Dual SDR Transceiver.3U VPX 3-Channel 200 MHz A/D. 800 MHz D/A.VME Multifrequency Clock Synthesizer .VME System Synchronizer and Distribution Board . 500 MHz A/D. Virtex-5 FPGAs .PCI Multifrequency Clock Synthesizer . NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 800 MHz D/A. 800 MHz D/A.Half-length PCIe Dual SDR Transceiver. Virtex-5 FPGAs . Virtex-5 FPGAs .Putting FPGAs to Work in Software Radio Systems Links Model 7158 7258 7358 7658 7758 7858 5358 71620 71660 6821-422 6822-422 6826 6890 6891 7190 7290 7390 7690 7790 7890 5390 9190 RTS 2701 RTS 2703 RTS 2711 RTS 2721 4990 4207 Description Dual SDR Transceiver.3U VPX Clock and Sync Generator for I/O Modules Rack-Mount Real-Time Recording and Playback Transceiver System 2-Channel 200 MSample/sec Real-Time Recorder Instrument 2-Channel 500 MSample/sec Real-Time Recorder Instrument Portable Real-Time Recording and Playback Transceiver Instrument Pentek SystemFlow Recording Software PowerPC and FPGA I/O Processor .3U cPCI Multifrequency Clock Synthesizer . • One Park Way.2 GHz Clock.com • http://www.VME/VXS Dual 215 MHz.XMC 215 MHz.VME/VXS Page 29 29 29 29 29 29 29 30 31 32 33 34 35 36 37 37 37 37 37 37 37 38 39 40 41 42 43 47 Handbooks and Brochures Click here Click here Click here Click here Software Defined Radio Hanbook Critical Techniques for High-Speed A/D Converters in Real-Time Systems Handbook High-Speed Switched Serial Fabrics Improve System Design Handbook Model 4207 PowerPC and FPGA I/O Processor Board Brochure 53 Pentek.3U cPCI Dual SDR Transceiver. 800 MHz D/A.PCI Dual SDR Transceiver.Half-length PCIe Multifrequency Clock Synthesizer . Upper Saddle River. Virtex-5 FPGAs . Virtex-5 FPGAs . 12-bit A/D with Wideband DDCs .PMC/XMC Dual SDR Transceiver. 800 MHz D/A. Sync and Gate Distribution Board . DUC. 800 MHz D/A.Full-length PCIe Multifrequency Clock Synthesizer . 800 MHz D/A.Full-length PCIe Dual SDR Transceiver.

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