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e-ISSN (O): 2348-4470

Scientific Journal of Impact Factor (SJIF): 4.72
p-ISSN (P): 2348-6406

International Journal of Advance Engineering and Research
Development
Volume 4, Issue 8, August -2017

Design of 5-bit Flash ADC through Domino Logic
in 180nm, 90nm, and 45nm Technology
1
V. komali1 ,2 G. Balaraju
1
Student, Dept of ECE, CVR college of Engineering, Hyderabad, India
2
Asst. Professor, Dept of ECE, CVR college of Engineering, Hyderabad, India

Abstract— In this paper high speed 5-bit Flash analog to digital converter (ADC) through Domino logic is designed in
180nm, 90nm, and 45nm CMOS technology with sampling rate of 4GS/s. Domino logic allows rail to rail logic swing. It
was developed to speed up the circuit. The physical circuit is more compact than previous design compare to power and
delay. This can be used for high speed applications. Flash analog to digital converter is ideal for applications requiring
very large bandwidth, but they consume more power than other ADC architectures and are generally limited to 8-bit
resolution.

Keywords— Comparator, Encoder, Domino logic, Power, Delay.

I. INTRODUCTION

To convert analog information into digital information Flash ADC is one of the fastest methods. Flash ADCS are
highly used in applications where large bandwidth is required such as radar processing, sampling oscilloscopes, data
acquisition and satellite communication applications. Flash analog to digital converter have the highest speed of any type
of ADC [1]. It is also called as parallel converter because of its parallel structure. It uses one comparator per quantization
level (2N-1) and 2N resistor string. The reference voltage is divided into 2N values, each of which is fed into a comparator.
The comparator compares the input voltage with the each reference voltage value and results the binary output in terms
of „0‟s and „1‟s at the output of the comparator that is called as thermometer code which consists of string of „0‟s and
„1‟s. A thermometer code exhibits all zeros for each resistor level if the value of input voltage is less than the reference
voltage and one‟s if the input voltage is greater than or equal to the reference voltage.
Block diagram of N-bit Flash ADC is shown in Fig. 1.

Figure 1:Block diagram of Flash ADC

The praposed Flash ADC is designed using Domino logic style for reducing the power consumption and increasing the
speed as compared to the current mode logic style. Domino logic is presented in section 2. The design of praposed
comparator using dominologic is presented in section 3. The design of praposed encoder using domino logic is presented
in section 4. The analysis of praposed Flash ADC and simulation results are showen in section 5 and finally conclusion in
section 6.

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International Journal of Advance Engineering and Research Development (IJAERD)
Volume 4, Issue 8, August-2017, e-ISSN: 2348 - 4470, print-ISSN: 2348-6406

2. DOMINO LOGIC

Domino logic was developed to speed up circuits. Domino logic is a CMOS-based assessment of the dynamic
logic techniques based on either PMOS or NMOS transistors. It allows a rail-to-rail logic oscillates. Cascade structure
consisting of several stages each stage ripples the next stage for assessment, similar to a domino falling one after the
other. The structure of Domino logic is shown in Fig.2.

Figure 2 Basic structure of Domino logic
In dynamic logic, a problem occurs when cascading one gate to the next. The precharge "1" state of the first gate may
cause the second gate to discharge prematurely, before the first gate has reached its correct state. This absorb the
"precharge" of the second gate, which cannot be replace until the next clock cycle, so there is no recapture from this
error. In order to cascade dynamic logic gates, one solution is Domino Logic, which inserts an ordinary static inverter
between stages.
Domino logic consisting of the two phase when CLK=0 it occurs the “Precharge” phase, when CLK=1 it occurs
“Evaluation” phase. In Domino logic input values is changed only during Precharge phase, if the value is changed during
the Evaluate phase it can interrupt the output voltage.

3. COMPARATOR

Comparator plays a essential role in the design of an analog to digital converter [4]. Power dissipation, offset
Speed, gain, and resolution are the important parameters of any type of comparators. The fundamental aim of the
comparator is to compare an input signal (V IN) with a reference signal (VREF) and to produce an output logic low or logic
high depending on whether the input signal is greater or smaller than reference. We have different architectures of
comparator for Flash ADC namely differential comparator, dynamic comparator, double tail dynamic comparator, etc. In
this paper we will take double tail dynamic comparator through domino logic as the reference model and try to optimize
in terms of transistors.
This comparator is an extension of double tail comparator [2]. At the output side Domino logic circuit is added
to the double tail comparator. Here the Out n is given to the one input and out p is given as another logic circuit.
Considering the two stages of the circuit, at each stage the output will be taken, inverted and given as next stage input.
The output of first stage and second stage considered as out1, out2 respectively. The proposed comparator is shown in
Fig. 3.

Figure 3 Double tail dynamic comparator through domino logic

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International Journal of Advance Engineering and Research Development (IJAERD)
Volume 4, Issue 8, August-2017, e-ISSN: 2348 - 4470, print-ISSN: 2348-6406

The operation consists of two phases i.e. reset phase and comparison or regenerative phase. When CLK=0, the
comparator is operated in Reset phase and CLK=VDD the comparator is in comparison phase.
During reset stage i.e. CLK =0, Mtail1 and Mtail2 are off which overcomes static power consumption, M 3 and M4
pulls both output nodes FP and FN to VDD, hence transistors Mc1 and Mc2 are going to cut off. The transistors between
input and latch stage (MR1 and MR2), reset inverter latch outputs to ground/V SS. While the comparator at decision
making/comparison stage i.e. CLK =VDD, then Mtail1 and Mtail2 are on and transistors M3 and M4 are turned off.
Furthermore, at the beginning of this stage, the control transistors are still off where output nodes F N and FP are charged
to VDD. Thus, the nodes FN and FP starts to down with different charging rates based on the applied input voltages (V INN
and VINP). Consider the case VINP>VINN, the node FN drops faster than FP, where transistor (M2) gives high current than the
transistor (M1). As the node FN continues to down for a long time, the corresponding PMOS or control transistor (M c1)
gets to turn on, and taking FP node gets back to the VDD. So, another PMOS control transistor (Mc2) remains turned off,
which allows the node FN to be completely discharge.

4. ENCODER

The comparators produce the output in a specific manner which is called thermometer code. The thermometer
code is converted into binary code with the help of thermometer code to binary code conversion. The speed of the
converter plays a vital role in the design of Flash ADC. For N-bit encoder requires 2N inputs. Error handling
capability and power dissipation are two vital parameters in the design of thermometer to binary code conversion [3].
Offset voltage in the comparator creates bubble error in the thermometer code. These bubble errors can reduce with the
help of majority of „0‟s and „1‟s. So convert the thermometer code to gray code is one of the popular methods to reduce
the bubble errors in thermometer code. We have different types of encoders for Flash ADC namely ROM encoder, fat
tree encoder, multiplexer based encoder, etc. with different logic styles In this paper we will take thermometer code to
binary code converter through domino lo as the reference model and try to optimize in terms of transistors . Block
diagram of 4-bit Thermometer to binary code converter is shown in Fig.4.

Figure 4 Block diagram of 5-bit Encoder

The equations between the thermometer codes to gray code is given below and derived from the truth table.

G4=T16 G3=T8T24‟
G2=T4T12‟+T20T28‟ G 1=T2T6‟+T10T14‟+T18T22‟+T26T30‟
G0=T1T3‟+T5T7‟+T9T11‟+T13T15‟+T17T19‟+T21T23‟+T25T27‟+T29T31‟

The equations between gray code to binary code is given
Below.

B4=G4 B3=G3 XOR B4
B2=G2 XOR B3
B1=G1 XOR B2 B5=G0 XOR B1

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International Journal of Advance Engineering and Research Development (IJAERD)
Volume 4, Issue 8, August-2017, e-ISSN: 2348 - 4470, print-ISSN: 2348-6406

5. IMPLEMENTATION AND RESULTS

5.1. Comparator implementation
Fig 5 shows schematic of proposed comparator. From the Fig.5 we can see that the output buffers used at the output
terminal is just to stabilize the output and bring it to logic level of either 0 or 1 depending on the output state.

Figure 5 double tail dynamic comparator through domino logic schematic.

Figure 6 wave form of proposed comparator

5.2. Implementation of 5-bit Flash ADC
Flash analog to digital converter has the highest speed of any type of ADC. It uses one comparator per quantization
level (2N-1) and 2N resistor string. The reference voltage is divided into 2 N values, each of which is fed into a comparator.
Fig 7 shows the implementation of 5-bit Flash ADC.

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International Journal of Advance Engineering and Research Development (IJAERD)
Volume 4, Issue 8, August-2017, e-ISSN: 2348 - 4470, print-ISSN: 2348-6406

Figure 7 Schematic of 5-bit Flash ADC

Figure 8 wave form of 5-bit Flash ADC

Table: Power and Delay of the Domino logic based 4-bit Flash ADC

Technology 180nm 90nm 45nm

Supply voltage 1.2v 1.2v 1.2v
Power 1.40uw 259.3nw 242.3nw
Delay 842.5ps 162.7ps 77.11ps
Sampling rate 250MHZ 250MHZ 250MHZ

6. CONCLUSION AND FUTURE SCOPE

Above circuits are implemented in 180 nm, 90nm, and 45nm technology using CADENCE Tool. The power
dissipation for the proposed Flash ADC is reduced from in 180nm with 1.40uw to 45nm with 242.3nw. Also the
propagation delay observed in proposed Flash ADC is 842.5ps with 180nm, which is further reduced in 45nm with
77.11ps. Offset voltage reduction can be a topic to work on in future to reduce the noise which gets incorporated to due
to mismatch errors. Also further optimization can be done in order to reduce the number of transistors used in comparator
design.

@IJAERD-2017, All rights Reserved 717
International Journal of Advance Engineering and Research Development (IJAERD)
Volume 4, Issue 8, August-2017, e-ISSN: 2348 - 4470, print-ISSN: 2348-6406

ACKNOWLEDGMENT

The authors extend their warm gratitude towards our college Principal Dr. Nayanatara K S,Head of department Prof. P.
Viswanath for their concern and support. They would also like to thank other faculties of CVR college of Engineering for
their assistance on various aspect of this work.

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