Design Vision User Guide

Version U-2003.03, March 2003

Comments? E-mail your comments about Synopsys documentation to

Copyright Notice and Proprietary Information
Copyright  2003 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

Right to Copy Documentation
The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: “This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.”

Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.


Registered Trademarks (®)
Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, Calaveras Algorithm, CoCentric, COSSAP, CSim, DelayMill, Design Compiler, DesignPower, DesignWare, Device Model Builder, Enterprise, EPIC, Formality, HSPICE, Hypermodel, I, in-Sync, InSpecs, LEDA, MAST, Meta, Meta-Software, ModelAccess, ModelExpress, ModelTools, PathBlazer, PathMill, Physical Compiler, PowerArc, PowerMill, PrimeTime, RailMill, Raphael, RapidScript, Saber, SmartLogic, SNUG, SolvNet, Stream Driven Simulator, Superlog, System Compiler, TestBench Manager, Testify, TetraMAX, TimeMill, TMA, VERA, and VeriasHDL are registered trademarks of Synopsys, Inc.

Trademarks (™)
Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, Cosmos SE, Cosmos-Scope, CosmosLE, Cyclelink, Davinci, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, DesignerHDL, DesignTime, DFM-Workbench, DFT Compiler SoCBIST, Direct RTL, Direct Silicon Access, DW8051, DWPCI, Dynamic Model Switcher, Dynamic-Macromodeling, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FormalVera, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Frameway, Gatran, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSPICE-Link, Integrator, Interactive Waveform Viewer, iQBus, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Libra-Visa, Library Compiler, LRC, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, NanoSim, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDLlint, OpenVera, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, Progen, Prospector, Proteus OPC, Protocol Compiler, PSMGen, Raphael-NES, RoadRunner, RTL Analyzer, Saber Co-Simulation, Saber for IC Design, SaberDesigner, SaberGuide, SaberRT, SaberScope, SaberSketch, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-Hspice, Star-HspiceLink, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-Sim XT, Star-Time, Star-XP, SWIFT, Taurus, Taurus-Device, Taurus-Layout, Taurus-Lithography, Taurus-OPC, Taurus-Process, Taurus-Topography, Taurus-Visual, Taurus-Workbench, Test Compiler, TestGen, TetraMAX TenX, The Power in Semiconductors, TheHDL, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice, TSUPREM-4, TymeWare, VCS, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Inc.

Service Marks (SM)
DesignSphere, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. All other product or company names may be trademarks of their respective owners.

Printed in the U.S.A. Document Order Number: 37175-000 PA Design Vision User Guide, vU-2003.03


What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. Introduction to Design Vision Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Vision and Other Synopsys Products . . . . . . . . . . . . . . . . . 2. Before You Start The Design Vision Documentation Set . . . . . . . . . . . . . . . . . . . . . . Design Compiler Tutorial Using Design Vision. . . . . . . . . . . . . . 2-2 2-2 1-2 1-3 1-3 1-4 1-5 1-6 1-7 xii xii xvi


. . . . . . . . 2-13 Using Scripts . . . Saving the Design Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exploring the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading In Your Design. . Working With Reports . . . . . . . . . . 3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-9 3-9 Generating Reports for Selected Objects . . . . . . Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Files for Design Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting and Exiting the Graphical User Interface . . . . . . . . . . . . . . . 2-3 2-4 2-5 2-7 2-9 Changing the Appearance of Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Basic Tasks Specifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 iv . . Setting Design Constraints . . . . . . . . . . . . . . . . . Setting the Current Design . . . . . . . . . . . . . Design Vision Online Help . . . . . . . . . . . . . . . . . . . . . . . 2-14 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining the Design Environment . . . . . . Setting Optimization Constraints . . . Setting Design Rule Constraints . . . . . . . . . . . . 3-10 Printing Schematics. .Design Vision User Guide . . . . . . . . .

. . . . . . . . . . . .4. . . . . . . . Assessing the Relative Size of Your Timing Violations . . . . . . . . . . . . . . . Creating a Timing Overview . . . . . . . . . . . . . . . Working Locally to Fix Small Violations . . Working Globally to Fix Small Violations . . . . . . . . . . . . . . . . When Timing Violations Are Small. . . . . . . . . . . . . . . . . . . . . . . . . . Choosing a Strategy for Timing Closure . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2 4-4 4-4 4-5 4-6 4-6 4-8 When Timing Violations Are Large . . . . . . . . . . . . . . . . . . . . Solving Timing Problems Before You Analyze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Index v . . . . . . . . . . . . . . . . When Timing Violations Are Medium Size. . . . . . .

vi .

. . . . . . . . . Endpoint Slack Histogram. . . . . . . . . . Design With Medium Timing Violations . . . . . . . . . . . . . . 4-12 vii . . . . . . . . .Figures Figure 2-1 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 The Design Vision Window . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 4-3 4-5 4-9 Design With Large Timing Violations . . . . . Design With Small Timing Violations . . . . . . . . . . . . . . . . . . .

viii .

. . . . . . . . . . . . . . Design Vision Supported Platforms . 2-15 ix . . . .Tables Table 1-1 Table 1-2 Table 2-1 Supported File Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-6 Commands for Scripting . . . . . . . . . . . . .

x .

Preface This preface includes the following sections: • • • What’s New in This Release About This User Guide Customer Support FIX ME! xi .

and resolved Synopsys Technical Action Requests (STARs) is available in the Design Vision Release Notes in SolvNet.synopsys. enhancements. follow the instructions to register with SolvNet. About This User Guide This section contains information about the target audience of this document. enter your user name and password. then open the Design Vision Release Notes. 1. Preface xii . (If you do not have a Synopsys user name and and click SolvNet. and changes. and documentation conventions used in this manual.What’s New in This Release Information about new features. known problems and limitations. If prompted. To see the Design Vision Release Notes.03 Release Notes. Go to the Synopsys Web page at http://www. 2. find the U-2003. Click Release Notes in the Main Navigation section. where to find other pertinent publications.) 3.

com • • You might also want to refer to the documentation for the following related Synopsys products: • • • Design Compiler DFT Compiler BSD Compiler About This User Guide xiii . see • Synopsys Online Documentation (SOLD). from which you can order printed copies of Synopsys documents.Audience This user guide is for logic design engineers who have some experience using Design Compiler and who want to use the visualization features of Design Vision for synthesis and analysis. you should be familiar with • • • Synthesis using Design Compiler VHDL or Verilog HDL The UNIX operating system Related Publications For additional information about Design Vision. at http://mediadocs. which is included with the software for CD users or is available to download through the Synopsys Electronic Software Transfer (EST) system Documentation on the Web. which is available through SolvNet at http://solvnet. To use this user The Synopsys MediaDocs Shop.

• Power Compiler Preface xiv .

such as set_annotated_delay Control-c Indicates a keyboard combination.) Denotes optional parameters.. such as object_name. is indicated by regular text font italic. medium. Indicates a user-defined value in Synopsys syntax. such as holding down the Control key and pressing c. (User input that is not Synopsys syntax. such as pin1 [pin2 . pinN] Courier bold [] | Indicates a choice among alternatives. such as opening the Edit menu and choosing Copy.) Indicates user input—text you type verbatim— in Synopsys syntax and examples. Indicates levels of directory structure.. such as a user name or password you enter in a GUI. or high.) _ Connects terms that are read as a single term by the system. such as a user-defined value in a Verilog or VHDL statement.Conventions The following conventions are used in Synopsys documentation. Indicates a path to a menu command. Indicates a continuation of a command line. (A user-defined value that is not Synopsys syntax. Convention Description Courier Courier italic Indicates command syntax. \ / Edit > Copy About This User Guide xv . is indicated by regular text font bold. such as low | medium | high (This example indicates that you can enter one of three possible values for an option: low.

follow the instructions to register with SolvNet. Preface xvi .Customer Support Customer support is available through SolvNet online customer support and through contacting the Synopsys Technical Support Center.) If you need help using Accessing SolvNet SolvNet includes an electronic knowledge base of technical articles and answers to frequently asked questions about Synopsys tools. 2. Go to the SolvNet Web page at http://solvnet.synopsys. enter your user name and password. (If you do not have a Synopsys user name and password. documentation on the Web. click SolvNet Help in the Support Resources section. SolvNet also gives you access to a wide range of Synopsys online services including software downloads. If prompted.” To access SolvNet. and “Enter a Call to the Support Center. 1.

questions.Call (800) 245-8005 from within the continental United (Synopsys user name and password required).Contacting the Synopsys Technical Support Center If you have problems.” Send an e-mail message to support_center@synopsys. .Find other local support center telephone numbers at http://www.synopsys. then clicking “Enter a Call to the Support Center. . Telephone your local support center. . you can contact the Synopsys Technical Support Center in the following ways: • Open a call to your local support center from the Web by going to http://solvnet.Call (650) 584-4200 from or suggestions. • • Customer Support xvii

Preface xviii .

1 Introduction to Design Vision 1 Design Vision is a graphical user interface (GUI) to the Synopsys synthesis environment and an analysis tool for viewing and analyzing your design at the generic technology (GTECH) level and the gate level. This chapter contains the following sections: • • • • • • • Features and Benefits User Interfaces Methodology Supported Formats Licensing Supported Platforms Design Vision and Other Synopsys Products 1-1 .

for example slack and capacitance .Path schematic generation for visual examination of any paths or selected logic you choose • • Command-line interface integrated in the GUI Scripting support for all Design Compiler shell (dcsh) commands and Design Compiler tool command language (dctcl) commands Using the features of Design Vision.A logic hierarchy view for easy visualization and navigation of your design hierarchy (including viewing area attributes) .Design schematic generation for examining high-level and low-level design connectivity .and menu-driven interface to Synopsys synthesis (Design Compiler) Analysis visualization capabilities that include .Histograms for visualizing trends in various metrics.Features and Benefits Design Vision has these features: • • Window. you can • • • • • Invoke Design Compiler synthesis and reporting Explore design structure Perform timing analysis for blocks you are synthesizing Visualize overall timing with Design Vision graphical analysis Perform detailed visual analysis of timing paths Chapter 1: Introduction to Design Vision 1-2 .

Menus also offer visual analysis features and other design viewing features that are not Design Compiler functions. All Design Compiler functions are available through the Design Vision command-line interface. with or without test points User Interfaces Design Vision offers menus and dialog boxes for important Design Compiler functions. and dc_shell (dcsh) mode. Many of the Design Compiler functions are available through Design Vision menus. Design Vision includes a command-line interface that provides access to all the capabilities of Synopsys synthesis tools. The Design Vision GUI and command-line interface operate in both Tcl (dctcl) mode. Methodology Design Vision allows you to use the same design methodology and scripts you currently use and to extend your methodology with Design Vision visual analysis.• Insert scan cells and logic into a design. the default. User Interfaces 1-3 .

Tcl Physical Design Exchange Format (PDEF) Synopsys internal library format (.db) Tegas Design Language (TDL) Verilog VHDL Xilinx Netlist Format (XNF) Timing Command Script Cell Clustering Library Standard Delay Format (SDF) dcsh. Table 1-1 Supported File Formats Formats Data Netlist EDIF LSI Logic Corporation netlist format (LSI) Mentor Intermediate Format (MIF) Programmable logic array (PLA) Synopsys equation Synopsys state table Synopsys database format (.lib) Synopsys database format (.Supported Formats With Design Vision you can access all the files supported by Design Compiler.db) Parasitics dc_shell command scripts Chapter 1: Introduction to Design Vision 1-4 . Table 1-1 shows the supported design file formats.

To use Design Vision, you need the Design-Vision license. Synopsys licensing software and the documentation describing it are now separate from the tools that use it. You install, configure, and use a single copy of Synopsys Common Licensing (SCL) for all Synopsys tools. Because it provides a single, common licensing base for all Synopsys tools, SCL reduces licensing administration complexity, minimizing the effort you expend in installing, maintaining, and managing licensing software for Synopsys tools. For complete Synopsys licensing information, see the following documents: • Licensing Quick Start This booklet provides instructions on how to obtain an electronic copy of your license key file and how to install and configure SCL on UNIX and Windows NT operating systems. • Licensing Installation and Administration Guide This guide provides detailed information on SCL installation and configuration, including examples of license key files and troubleshooting guidelines.

Licensing 1-5

Supported Platforms
Design Vision runs on the platforms listed in Table 1-2. Table 1-2

Design Vision Supported Platforms
Operating system Default window manager

HP9000 IBM RS/6000 Sun SPARC Intel IA-32

HP-UX 11.0, 11.11 (11i) AIX 4.3.31 Solaris 8 Red Hat Linux 7.22


1. Not available on CD, but will be available for download by EST at a later date. For availability, check with your Synopsys sales representative. 2. Runs only in 32-bit mode; limited to 4 GB memory space.

All UNIX platforms support the default window manager supplied by the manufacturer as well as Motif Window Manager v1.2.1 through v1.2.5, and eXceed versions 6.2 and 7.0 native window manager multiple window mode. Design Vision does not support the schematic interface (SGE) to Mentor Graphics tools. Note: OpenWindows is not a supported window manager for Design Vision. Sun Microsystems no longer supports or maintains OpenWindows and recommends that you move to the CDE Windows environment.

Chapter 1: Introduction to Design Vision 1-6

Your hardware and operating system vendor has required patches available for your system. For more information about the supported platforms and the operating system patches necessary to run Synopsys software on supported platforms, go to From this Web page you can navigate to the Supported Platforms Guide for your release.

Design Vision and Other Synopsys Products
As a visual analysis tool and GUI for Synopsys synthesis, Design Vision works with Design Compiler to synthesize and analyze your design. The Design Vision and Synopsys PrimeTime tools have similar timing visualization features; however, the tools have different timing engines and differ in their application to analysis. Design Vision has the same static timing engine as Design Compiler. Use Design Vision to perform timing analysis and modification of blocks you are synthesizing. Use PrimeTime for static timing sign-off or for analyzing the timing of a chip or of large portions of a chip.

Design Vision and Other Synopsys Products 1-7

Chapter 1: Introduction to Design Vision 1-8 .

In this chapter you can find the following sections: • • • • • • The Design Vision Documentation Set Setup Files for Design Vision Starting and Exiting the Graphical User Interface Exploring the Graphical User Interface Changing the Appearance of Schematics Using Scripts 2-1 .2 Before You Start 2 This chapter contains general and specific information you need to know before you use Design Vision for the first time.

The tutorial introduces Design Vision as the GUI for synthesis and provides some post-synthesis analysis that takes advantage of the Design Vision visual representation of analysis results. However. the SolvNet knowledge base. Chapter 2: Before You Start 2-2 . The Design Vision documentation set is divided into these parts: • • • Design Compiler Tutorial Using Design Vision Design Vision User Guide Design Vision online Help Other sources of information include man pages. Design Compiler Tutorial Using Design Vision The Design Compiler Tutorial Using Design Vision is an introduction to ASIC design using Synopsys Design Compiler and Design Vision. even if you are an experienced Design Compiler user. see “Customer Support” on page xvi.The Design Vision Documentation Set You can find most of what you need to know to run Design Vision in the Design Vision documentation set. the tutorial is a useful introduction to the features of Design Vision. For information about accessing these sources of information. The tutorial is a group of guided exercises in which you use Design Compiler to synthesize and analyze a simple design. Use the Design Compiler Tutorial Using Design Vision if you are new to Design Compiler. and the Customer Support Center.

In the tutorial. For example. it presents short procedures that use the analysis visualization features of Design Vision to locate and solve timing problems. The Design Vision User Guide does not contain specific information about individual menu items or dialog boxes. you • • • • • • • Read a design from disk into the tool’s workspace Define design constraints to direct synthesis results Compile the design to gates View analysis results Modify the design Resynthesize the design Reanalyze the design Design Vision User Guide The Design Vision User Guide assumes you are familiar with basic Design Compiler concepts. see the Design Vision online Help. The user guide provides guidance in solving particular problems. The Design Vision Documentation Set 2-3 .” Such steps refer to features of Design Vision that are explained in the Design Vision online Help. For such information. you can read about and perform exercises for basic synthesis and analysis. For example. “Create a histogram” or “Create a path schematic. Sometimes steps in a procedure refer to actions without further explanation: for example.

you can find the information you need in the online Help system. and dialog box options. the user guide explains such topics only briefly. For example. if you need help performing a step in a procedure presented in the user guide. However. Design Vision online Help explains the details of features and procedures.In Chapter 3. You access the Help system from the Help menu in the main Design Vision window. “Performing Basic Tasks. • Reference topics Provide explanations for views. • How to topics Provide procedures for accomplishing general synthesis and analysis tasks. menu commands. Chapter 2: Before You Start 2-4 . toolbar buttons.” experienced Design Compiler users can learn how to do certain familiar synthesis tasks using Design Vision. Information in online Help is grouped in the following categories: • Feature topics Provide overviews of Design Vision window components and tools. Design Vision Online Help The Design Vision online Help is integrated in the Design Vision GUI.

• Choose Help > Online Help.To access the Design Vision online Help system. For optimal viewing. These setup files have the same names in each of their three locations: the installation.78. home. and style sheets Disable Java plug-ins If you reset preferences while the Help system is open. Setup Files for Design Vision When you start Design Vision. The online Help system makes extensive use of Java.setup. Design Vision also executes the GUI setup file when you open or reopen the GUI from the Design Vision shell. and design directories. and style sheets. make sure the advanced preferences are set as follows: • • Enable Java.synopsys_dc. you should use Netscape Navigator version 4. To configure your browser for viewing online Help. and the GUI setup file. Setup Files for Design Vision 2-5 . JavaScript. it executes the standard Synopsys setup file. JavaScript.tcl. . . Design Vision online Help is a browser-based HTML Help system.dv_setup. Design Vision Help is not supported in Netscape version 6 or later. click the Reload button on the browser's navigation toolbar after you reset the preferences.

The files contain commands that initialize parameters and variables. declare design libraries. For more information about the locations of setup files and initialization settings for synthesis. Chapter 2: Before You Start 2-6 . these files can • • Change the default appearance of Design Vision schematics Define scripts that you can run by using the source command (for dctcl scripts) or the include command (for dcsh scripts) These topics are covered in detail in “Exploring the Graphical User Interface” on page 2-9 and “Using Scripts” on page 2-14 respectively. Besides defining settings for synthesis. and so forth. see the Design Compiler User Guide.

enter % design_vision -dcsh_mode You cannot switch from mode to mode in the same session. To start Design Vision in dctcl mode. the design_vision-t prompt (in dctcl mode) or the design_vision prompt (in dcsh mode) appears in the shell where you started Design Vision. enter % design_vision To start Design Vision in dcsh mode. Starting and Exiting the Graphical User Interface 2-7 . • dcsh mode You must start in this mode to use dcsh scripts. exit Design Vision and start Design Vision in dcsh mode.Starting and Exiting the Graphical User Interface You can invoke the Design Vision GUI in either of the two dc_shell modes: • dctcl mode This is the default. the Design Vision window appears by default. • At the UNIX shell prompt. to change from the default dctcl mode to dcsh mode. To operate in either mode. • At the UNIX shell prompt. Design Vision must start up and initialize in that mode. For example. When you start Design Vision. In addition.

• Choose File > Close. Chapter 2: Before You Start 2-8 .You can close and reopen the Design Vision GUI without exiting the Design Vision shell. Or you can enter gui_stop on the command line. • At the UNIX shell prompt. • Enter the following on the design_vision-t (or design_vision) command line.setup file: set gui_auto_start 0 To exit Design Vision.synopsys_dc. • Choose File > Exit. • Set the following variable in your . enter % design_vision -dcsh_mode -no_gui To set Design Vision to start without the GUI by default. To close the GUI without exiting Design Vision. In addition. • At the UNIX shell prompt. design_vision-t> gui_start To start Design Vision in dctcl mode without opening the GUI. enter % design_vision -no_gui To start Design Vision in dcsh mode without opening the GUI. To open or reopen the GUI from the Design Vision shell. you can start the Design Vision shell without opening the GUI.

Figure 2-1 The Design Vision Window Menus Toolbars Schematic view Logic hierarchy view Status bar Tabs Command line Console Exploring the Graphical User Interface 2-9 . Figure 2-1 shows the window you see when you start Design Vision. read in a design. and a design schematic for the top-level design.Exploring the Graphical User Interface Design Vision has the look and feel of the Microsoft Windows GUI.

When you start a Design Vision session. pins of child cells.Objects list The instance tree lets you quickly navigate the design hierarchy and see the relationships among its levels.Instance tree . You can also adjust the width of a column by dragging its right edge left or right. the object table displays information about hierarchical cells belonging to the selected instance in the instance tree. If you select the instance name of a hierarchical cell (an instance that contains subblocks). By default. the following view windows appear in the workspace: • Logic hierarchy View The logic hierarchy view helps you navigate your design and gather information. The view is divided into the following two panes: . select the object types in the list above the table. pins and ports. To display information about other types of objects. all cells. You use the workspace between the toolbars and the status bar to display view windows containing graphical and textual design information. a menu bar. If some of the text in a column is missing because the column is too narrow. information about that instance appears in the object table.The window consists of a title bar. and several toolbars at the top of the window and a status bar at the bottom of the window. you can hold the pointer over it to display the information in an InfoTip. You can display information about hierarchical cells. and nets. Chapter 2: Before You Start 2-10 . You can Shift-click or Control-click instance names to select combinations of instances.

see the “Using dc_shell Commands” topic in online Help. For more details about the console. In addition to the logic hierarchy view and the console. The log view provides the session transcript. and user-defined) Exploring the Graphical User Interface 2-11 . you can display design information in the following views: • • Schematic views (design schematics.• Console The console provides a command-line interface and displays information about the commands you use during the session in the following three views: . path schematics. net capacitance.Log view . The history view provides a list of the commands that you have used during the session. The errors and warnings view displays error and warning messages. click the tab at the bottom of the console. path slack. and symbol views) Histogram views (endpoint slack. Design Vision echoes the dc_shell command output (including processing messages and any warnings or error messages) in the console log view. The log view is displayed by default when you start Design Vision.Errors and warnings view You can enter dc_shell commands on the command line at the bottom of the console. To select a view.History view . Enter these commands just as you would enter them at the dc_shell prompt in a standard UNIX or Linux shell.

and you can move them to different locations within the Design Vision window. you can click the button at the right end of the status bar. a toolbar button. The status bar. button. see the “Design Vision Window” topic in online Help. see the “Opening New Design Vision Windows” topic in online Help. pins.• • Report view List views (cells. All open Design Vision windows share the same designs in memory and the same current timing information. Chapter 2: Before You Start 2-12 . If you hold the pointer over a menu command. or tab performs. However. the status bar displays a brief message about the action that the command. you can configure the views independently for each window. For more details. or a tab in the workspace. You can open additional Design Vision windows and use them to compare views. When you click anywhere within a view window. To learn more about the functions of menu commands and toolbar buttons. and designs) Design Vision displays a tab in the workspace for each undocked view you open. To quickly display the list of selected objects in the Selection List dialog box. such as the number and type of selected objects. see the “Menu Bar” and “Toolbars” topics in online Help. side by side. ports. it is the active view) and can receive keyboard and mouse input. displays current information about the session. nets. or different design information within a view. Design Vision highlights its title bar to indicate that it has the focus (that is. at the bottom of the window. You can adjust the sizes of view windows for viewing purposes. To learn more.

and click OK. it applies the same display characteristics (color. line width.synopsys_dv_prefs. or hierarchy crossing. • Changing the Appearance of Schematics 2-13 . Edit the . bus. when Design Vision generates a schematic. line style. text color. port. and font) to all the objects of a given object type: cell.tcl file and run it as a Tcl script. set the desired options. pin. select the Schematic Settings category. bus ripper.Changing the Appearance of Schematics For display purposes only. net. fill pattern. You can change schematic settings in either of the following ways: • Choose View > Preferences to open the Application Preferences dialog box. This convention allows you to define how similar objects are displayed in a schematic or whether they appear at all.

Using Scripts Designers often use scripts to accomplish routine repetitive tasks such as setting constraints or defining other design attributes. To run dcsh scripts. To run dctcl scripts. Use the dialog box to navigate to the appropriate directory and run your script. see “Starting and Exiting the Graphical User Interface” on page 2-7. Alternatively. Chapter 2: Before You Start 2-14 . The Execute File dialog box opens. see the “Using Scripts” topic in online Help. Because Design Vision can run in either dctcl mode or dcsh mode. For information about starting Design Vision in either mode. To run scripts in Design Vision. • Choose File > Execute Scripts. you can use your existing scripts in Design Vision. To learn more about adding scripts to the Tools menu. start Design Vision in dcsh mode. you can run scripts from the design_vision-t command line by using the source command in dctcl mode or from the design_vision command line by using the include command in dcsh mode. start Design Vision in dctcl mode.

Table 2-1 Command Commands for Scripting Mode Description get_selection dctcl Returns a collection that is currently selected in the GUI Changes the selection in the GUI to the collection passed to it as a parameter change_selection dctcl For detailed descriptions of commands and options. Using Scripts 2-15 . see the man page for each command.Table 2-1 is a short list of some commands that are useful when you are writing scripts for use with Design Vision.

Chapter 2: Before You Start 2-16 .

see the Design Compiler Tutorial Using Design Vision to learn about basic tasks by performing them on a simple design. This chapter is useful for experienced users of Design Compiler who need to accomplish familiar basic tasks in Design Compiler using Design Vision windows and menus. This chapter contains the following sections: • • • • Specifying Libraries Reading In Your Design Setting the Current Design Defining the Design Environment 3-1 .3 Performing Basic Tasks 3 This chapter describes how to perform basic presynthesis and synthesis tasks using Design Vision menus. If you are new to Synopsys synthesis tools.

• • • • • Setting Design Constraints Compiling the Design Saving the Design Database Working With Reports Printing Schematics Chapter 3: Performing Basic Tasks 3-2 .

and symbol library.setup file. DesignWare libraries with the synthetic_library variable (you do not need to specify the standard DesignWare library). design rules. 4. see the Design Compiler User Guide. You must specify any additional. specify the location of your libraries. Select the Defaults category if the Defaults page is not displayed. 1. delay arcs. Either method is acceptable—they both accomplish the same thing.synopsys_dc. Specifying Libraries 3-3 . The link and target libraries are technology libraries that define the semiconductor vendor’s set of cells and related information. such as cell names.synopsys_dc. The Application Setup dialog box opens. Enter the library file names for link library.setup file or indirectly by entering the locations in the Application Setup dialog box. 2. specially licensed. and operating conditions. pin loading. 3. cell pin names. Select File > Setup.Specifying Libraries Before you start work on a design. The symbol library defines the symbols for schematic viewing of the design. Make sure you enter the appropriate path in the Search Path box. To specify the library location in the Application Setup dialog box. You can define your library locations directly in the . To define libraries in the . target library.

see the “Setting Variables” topic. see the “Setting Library Locations” topic in the online Help. For information about the options on the Variables page.db format. Chapter 3: Performing Basic Tasks 3-4 . The File menu contains the commands for reading in a design: • Analyze and Elaborate Use Analyze and Elaborate to read HDL designs and convert them to Synopsys database (. and stores the intermediate files in the directory you specify. see the Design Compiler User Guide. For more information about the options on the Defaults page. • Read Use Read (read_file is the command-line equivalent) to read designs that are already in . and symbol libraries. The Analyze command checks the HDL designs for proper syntax and synthesizable logic. target libraries. read the design from disk into the tool’s active memory. Reading In Your Design To begin working on your design.5. This is where all changes in the design take place before you save the design by writing it back to disk. To understand more about the function of link libraries. translates the design files into an intermediate format.db) format. Click OK.

Setting the Current Design When you start a Design Vision session and read a design. If you use Read to read in HDL files. the Analyze and Elaborate read functions are combined. Alternatively. and it also determines correct bus size. 2. Select a design name. the current design is automatically set to the top-level design. Click the drop-down list on the Design List toolbar to display the design names.The Elaborate command first checks the intermediate format files before building a. The command-line equivalent is set current_design.db design. Read does not do certain design checks that Analyze and Elaborate do. you can open a designs list view (by choosing List > Designs View) and double-click a design name. 1. Some commands require you to set the current design to a subdesign before you issue them (the man pages provide such information). Setting the Current Design 3-5 . however. To set the current design. During this process. Elaborate determines whether it has the necessary synthetic operators to replace the HDL operators.

Defining the Design Environment Design Compiler requires that you model the environment of the design to be synthesized. To define the design environment by using Design Vision menus. temperature. explore the Operating Environment submenu on the Attributes menu. and voltage). This model comprises the external operating conditions (manufacturing process. Most designers find it convenient to use scripts to set design constraints. and wire load models. Design Compiler uses design rule and optimization constraints to control the synthesis of the design. Setting Design Constraints Setting design constraints can involve invoking a large number of commands. Defining the design environment can involve invoking a large number of commands. loads. drives. It directly influences design synthesis and optimization results. fanout. The online Help has more information about particular commands and submenus in the Attributes menu. Many designers find it convenient to define the design environment by using the default target technology library settings and by running scripts to define differences or additions. Chapter 3: Performing Basic Tasks 3-6 .

Use Specify Clock to set clock constraints. Setting Optimization Constraints Optimization constraints define the design goals for timing (clocks. Typical design rules constrain transition times. Optimization Constraints. and output delays) and area (maximum area). set options as needed. To optimize a design correctly. clock skews. it does not violate your design rules. Setting Design Constraints 3-7 . and capacitances. Explore these submenus to find the settings you need.Setting Design Rule Constraints Design rules are provided in the vendor technology library to ensure that the product meets specifications and works as intended. see the “Attributes Menu” topic in the online Help. you must set realistic optimization constraints.) To set design rule constraints by using the GUI. To set optimization constraints by using the GUI. • Click Attributes in the menu bar to open the Attributes menu. These rules specify technology requirements that you cannot violate. fanout loads. specify stricter constraints. For more information about menu items in the Attributes menu. Other optimization constraints and settings are in the submenus under the Attributes menu: Operating Environment. however. (You can. During optimization. and Optimization Directives. however. • Choose Attributes > Optimization Constraints > Design Constraints. Design Compiler attempts to meet these goals. and click OK. input delays.

Select or deselect options as you require. Use the default settings for your first-pass compile. For more information about compile methodologies.Compiling the Design Use Design Vision to invoke Design Compiler synthesis and optimization. thus compiling your high-level design description to your target technology. 1. After compiling the design. For more information about compile options. Design Vision supports standard synthesis methodology: either a top-down compile or a bottom-up compile. Choose Design > Compile Design. 2. see the Design Compiler User Guide. The Compile Design dialog box opens. To compile the current design. For most designs. see the Design Compiler User Guide and the Design Compiler Reference Manual: Optimization and Timing Analysis. Click OK to begin compiling. save the design as described in the next section. 3. Chapter 3: Performing Basic Tasks 3-8 . the default settings provide good initial results.

To save the current design and all of its subdesigns in a single file with a different file name or file format.db) format files named design_name. • Choose File > Save As. commands initiated by your menu and dialog box selections. To save the current design and each of its subdesigns in separate Synopsys database (.The command log file records your Design Vision session. select a file format. and tool commands (such as initialization commands and commands needed to execute user-entered commands). Use commands in the Timing Saving the Design Database 3-9 . You can use the command. enter or select a file name. It includes commands you enter on the command line.db. and click OK. where design_name is the name of the design. This log file is a record of all commands invoked. • Choose File > Save. Saving the Design Database Design Vision does not automatically save designs before exiting.log file to create a script file. Use commands in the Design menu to generate design information and design object reports. Copy the file and use a text editor to add or remove commands as necessary. Working With Reports Textual reports are available from the Design menu and the Timing menu.

To generate a report for a particular design object or group of design objects. If these menus do not have the report you need. 4. 3. You can generate reports and display them in the report view (the default). save them in text files. Select an object. 5. Choose a report command in the Design menu to open the associated dialog box. Click Selection in the report dialog box. or both. 1. you can select object names in the report. see the “Viewing Reports” topic in online to generate timing and constraint reports. Generating Reports for Selected Objects You can generate reports for selected objects. The names of the selected objects appear. Set other options as needed. 2. Click OK. For more information. ports. You can generate reports for cells. and nets. you can generate any Design Compiler by issuing dc_shell report commands on the command line. When you display a report in the report view. You can also save or print the report. Chapter 3: Performing Basic Tasks 3-10 .

Be sure that a default printer is set in your . design schematic. For details about the options in the Print dialog box. To print the active schematic view. Click the corresponding tab at the bottom of the workspace if you need to make the view active. Printing Schematics 3-11 .Printing Schematics You can print the path schematic. or symbol view. design schematic. The Select Printer Settings dialog box opens. Make sure the view you want to print is the active view. or symbol view displayed in the active schematic view. Choose File > Print Schematic. see the “Printing a Schematic View” topic in online Help. 1. 2. 3. Select the print options you require and click OK. Generate a path schematic. 4.cshrc file.

Chapter 3: Performing Basic Tasks 3-12 .

For detailed information about Design Vision features.4 Solving Timing Problems 4 This chapter presents procedures and suggestions for solving timing problems by using the features of Design Vision. see the Design Vision online Help system. such as how to create a histogram or how to create a path schematic. The chapter does not provide details about exercising particular features of Design Vision. This chapter contains the following sections: • • • Before You Analyze Creating a Timing Overview Choosing a Strategy for Timing Closure 4-1 .

Before You Analyze Before you analyze your design with Design Vision. Figure 4-1 is a typical endpoint slack histogram for a design with a 4-ns clock cycle. 1. a timing overview can help answer such questions as • • • Do I have many failing paths or just a few? Can I apply a local strategy for gaining timing closure? Do I need a global strategy for gaining timing closure? To create a timing overview of your design. A timing overview can help you decide what strategy to follow in gaining timing closure.” Creating a Timing Overview Creating an overview of the timing of your design is a valuable way to start any analysis of your design’s timing problems. follow your normal compile methodology to create a constrained gate-level design. For more information about using Design Vision to create a gate-level design. Chapter 4: Solving Timing Problems 4-2 . 2. A constrained gate-level design is a prerequisite to any timing analysis. “Performing Basic Tasks. Start with a constrained gate-level design. see Chapter 3. Generate an endpoint slack histogram. For example.

Conversely. strategy for problem solving. or that the design is failing your timing goals by a large margin.Figure 4-1 Endpoint Slack Histogram Endpoints of failing paths (red) Selected bin (yellow) Endpoint names for selected bin Using information such as that in Figure 4-1. you might decide on a local strategy if just a few paths are failing by a small margin (failing path endpoints are in one or more red bins to the left of 0 on the horizontal axis). Creating a Timing Overview 4-3 . you might choose a higher-level. if you find that many paths are failing. or global.

the best strategy for timing closure is one that uses the least amount of runtime or number of design iterations to achieve timing goals. however. Whether your design is failing timing goals by large or small margins. however. you can use these size guidelines to help you judge what strategy to use for timing closure. Chapter 4: Solving Timing Problems 4-4 . Assessing the Relative Size of Your Timing Violations This section suggests guidelines for describing the relative size of timing violations in your design.Choosing a Strategy for Timing Closure There is no single strategy that ensures quick and easy timing closure. • Large violations Some designers consider large violations to be about 20 percent of the clock cycle or greater. After you create an endpoint slack histogram. • Medium violations Medium-size timing failures fall between the limits you set for large and small failures in your design or design process. • Small violations Some designers consider small violations to be about 10 percent of the clock cycle or less. assessing violation size as a percentage of clock cycle can be useful. a strategy based on the size and number of timing violations can be useful. What you consider to be small or large violations depends on the requirements of your design and your design process.

Figure 4-2 Design With Small Timing Violations Clock cycle: 4 ns Endpoints of failing paths (red) Choosing a Strategy for Timing Closure 4-5 . no path is failing by more than 0. less than 10 percent of the 4-ns clock cycle (ignoring input and output delay). For example.This principle underlies the methodology suggestions in this chapter. You can click any bin to see the endpoint names for the paths in the bin.14 ns— that is. For more information about creating a timing overview. When Timing Violations Are Small Figure 4-2 is a histogram of a design that is failing timing goals by a small margin. see “Creating a Timing Overview” on page 4-2.

• Check hierarchy on failing paths Chapter 4: Solving Timing Problems 4-6 . try applying the suggestions in “When Timing Violations Are Medium Size” on page 4-8 or “When Timing Violations Are Large” on page 4-11. you can follow a global or local strategy in fixing the violations. The incremental compile with higher map effort has the advantage of simplicity—that is. The endpoint slack histogram helps you to recognize quickly which case you have. this method can change much of the logic in the design. The incremental option saves runtime by using the current netlist as the startpoint for design improvements. it requires little or no time spent in analyzing the source of timing problems. a local strategy can be effective. Working Locally to Fix Small Violations If you have a small number of paths with small violations.Designs that fail by a small margin can have many failing paths or just a few. However. If suggestions for fixing small violations (either globally or locally) don’t meet your timing goals. consider recompiling your design using the incremental option and a higher map effort. Whether you have just a few failing paths or many. Working Globally to Fix Small Violations To apply a global methodology for fixing small violations. To use a local strategy for fixing small violations. or if your violations seem to come from a limited set of problems on a few paths.

excessive fanout can worsen negative slack on failing paths. Generate an endpoint slack histogram. Design Compiler does not optimize across hierarchy boundaries. Thus. Choosing a Strategy for Timing Closure 4-7 . for example. Select the failing bin to see the endpoints. a subsequent compile has further opportunity to optimize the critical path when you ungroup such blocks. crosses multiple subblocks of a level of hierarchy. 1. snake paths limit Design Compiler’s ability to solve timing problems on such paths. consider ungrouping these subblocks. Click a bin that contains a failing path. 4. Select the endpoints for failing paths. If your critical path. To check for hierarchy problems on failing paths (dctcl mode only). A list of endpoints for failing paths is displayed. • Look for excessive fanout on failing paths Because higher fanout causes higher transition times. Thus.Design Compiler does not optimize across hierarchical boundaries. To look for excessive fanout on failing paths. 1. 2. 3. 2. Generate an endpoint slack histogram. Select the endpoint for the path you are interested in. Generate a path schematic to see which leaf cells are in which levels of hierarchy.

This step can provide useful information about the logic that drives. the problem path. A path schematic provides contextual information and details about the path and its . Examine the report for pins with high transition times and nets with high fanout.3. see “Working With Reports” on page 3-9 and the “Viewing Reports” topic in online Help. In Figure 4-3. you might choose to resize cells in those logic cones.trans Send the report output to the report view. A bin is yellow when selected. Such information is often a prerequisite to understanding problems on the path. one of the four bins containing endpoints of failing paths is selected. View fanin and fanout for path schematics. 4. Generate a timing report with the following options: . For more information on report generation. Such paths are candidates for buffering or drive-cell resizing. You can click a bin to see the endpoint names for paths the bin contains. 6. between 10 and 20 percent of the clock cycle). When Timing Violations Are Medium Size Figure 4-3 is a histogram of a design that is failing timing goals by margins that are between the large and small limits that are appropriate to your design methodology (for example. Chapter 4: Solving Timing Problems 4-8 . For example. or is driven by. Create path schematics of any paths you would like to see. after viewing fanin or fanout. 5.

html. For more information about calculating worst negative slack and total negative slack. you can use Design Vision to investigate further and focus your recompile on a critical range of negative slack values for path groups. Focusing your compile effort on a critical range can improve worst negative slack and total negative slack. Defining a critical range for path groups offers the advantage of concentrating compile effort and runtime on those areas that most need it. see the SolvNet article Synthesis-238. Choosing a Strategy for Timing Closure 4-9 .Figure 4-3 Design With Medium Timing Violations Clock cycle: 4 ns Endpoints of failing paths When negative slack values are medium.

3. Start with an arbitrary value of 1000 for the number of paths to include in each histogram.To investigate and focus a recompile by defining a critical negative slack range for path groups. Using the values you decided on in step 2. 1. The goal is to choose a value that shows you all or nearly all of the failing paths. for subsequent compiles you can adjust your critical range as necessary. Raise or lower this value depending on the number of failing paths. When deciding on a critical range.Use a range that includes the worst 50 paths in a group.Use a range equal to one generic cell delay in your technology. These are rough guidelines. Create a path slack histogram for each path group in your design. For example. some designers apply one of the following guidelines to decide on a critical range: . set the critical ranges for each path group with the group_path command.25 Chapter 4: Solving Timing Problems 4-10 . Set a critical range for each path group. choose a range that allows Design Compiler to focus on the worst endpoint violations without too large an increase in runtime. 2. For example. Decide on a critical range for each path group (note the values for use in step 3). . design_vision-t> group_path -name my_clock -critical_range 0.

select medium or high effort. With a critical range defined.4. When Timing Violations Are Large Figure 4-4 shows a design that is failing timing goals by a large margin. An incremental compile can save runtime when your design does not require fundamental changes. However. Choosing a Strategy for Timing Closure 4-11 . you can also choose to increase the compile effort over your previous compile. You can click a bin to see the endpoint names for the paths it contains. see the SolvNet article Methodology-10.html. the compile effort is now focused. For more information about defining critical ranges for synthesis. try applying the suggestions in “When Timing Violations Are Large” on page 4-11. Select the “Incremental mapping” option to direct Design Compiler to use the current netlist as a starting point for design improvements. If suggestions in this section don’t meet your timing goals. Recompile the design. In the Compile Design dialog box.

To fix large timing problems.Figure 4-4 Design With Large Timing Violations Clock cycle: 4 ns Endpoints of failing paths Fixing large violations can require a high-level strategy to improve your design’s performance. target a higher performance technology. • Change the target technology. consider any of the following changes: • Modify your constraints. For example. increase the clock cycle or adjust time budgeting for the block or chip. Chapter 4: Solving Timing Problems 4-12 . For example.

For example. you can move late-arriving signals such that you minimize their path length. Choosing a Strategy for Timing Closure 4-13 .• Modify the RTL.

Chapter 4: Solving Timing Problems 4-14 .

setting 3-5 current instance. how to 3-8 conditions. starting 2-7 dctcl mode. saving 3-9 IN-1 . operating 3-6 Console. changing for schematics 2-13 Attributes menu 3-7 dcsh mode. starting without GUI 2-8 dcsh scripts 2-14 dctcl mode.log 3-9 commands for scripting 2-15 compiling focusing on timing range 4-10 starting. setting 3-5 writing to disk 3-9 design constraints. description 2-11 constraints. setting 3-6 C cell clustering data.db file. supported formats 1-4 design schematics 2-11 Design Vision documentation set 2-2 features of 1-2 formats. timing. supported formats 1-4 change_selection command 2-15 closure. Design Vision 2-2 drive strength. starting 2-7 dcsh mode. setting 3-5 D . setting 3-6 design files. reading in a 3-4 documentation. input and output 1-4 graphical window components 2-9 introduction to 1-1 licensing for 1-5 supported platforms 1-6 Synopsys products.Index A appearance. setting 3-6 critical timing range choosing for compile 4-10 current design. strategy for 4-4 command. relationship to other 1-7 user interfaces 1-3 design. starting without the GUI 2-8 dctcl scripts 2-14 design current.

for 4-11 medium-size violations. finding excessive 4-7 histogram views 2-11 IN-2 . setting current 3-5 interfaces. for 4-8 H Help. Design Vision 1-3 L large timing violations defined 4-4 global approach 4-12 layers. online 2-4 hierarchy. setting 3-6 log files naming 3-9 scripts. finding 4-7. changing appearance 2-13 libraries specifying 3-3 supported formats 1-4 synthetic libraries 3-3 licensing 1-5 list views 2-12 loads. 4-8 histograms endpoint slack 4-2 script commands for 2-15 history view 2-11 F fanout. creating from 3-9 log view 2-11 logic hierarchy view. setting maximum 3-6 features. Design Vision 1-2 files log files 3-9 setup files 2-5 finding reported objects in schematic 3-9 focusing compile 4-10 formats cell clustering 1-4 design data 1-4 input and output 1-4 library 1-4 netlist 1-4 parasitics 1-4 script file 1-4 timing data 1-4 I initialization (see setup files) instance tree 2-10 instance. excessive. description 2-10 G generating reports 3-9 get_selection command 2-15 global approach. finding 4-7. timing closure large violations 4-12 small violations 4-6 group_path command 4-10 GUI (see window. setting operating 3-6 errors/warnings view 2-11 excessive fanout.E environment. 4-8 fanout. Design Vision) M manufacturing process. setting 3-6 medium-size timing violations defining 4-4 fixing 4-8 methodology choosing for timing closure 4-4 large violations.

4-6 O objects. operating system 1-7 path schematics 2-11 preferences. SolvNet article about 4-9 small timing violations defining 4-4 global approach to solving 4-6 local approach to solving 4-6 snake paths. setting 3-6 operating systems patches for 1-7 supported platforms 1-6 optimization constraints. initiating 3-8 synthetic libraries 3-3 R reading a design 3-4 reports for selected objects 3-10 generating 3-9 T Tcl mode.small violations. Tcl and dsch 2-14 supported formats 1-4 setup files 2-5 slack types. description of 2-4 OpenWindows. starting 2-7 timing closure. generating 2-15 menu access to 2-14 mode. supported formats 1-4 patches. finding 4-7 SolvNet articles slack types. support for 1-6 operating conditions. reports for selected 3-10 online Help. endpoint slack 4-2 judging violation size 4-4 S saving to disk 3-9 schematic views 2-11 schematics appearance. solving histogram. supported formats for 1-4 timing problems. creating for timing 4-2 P parasitics. running from 2-14 commands 2-15 creating from log file 3-9 histogram. locating reported 3-9 objects. for 4-5. calculating 4-9 specifying libraries 3-3 status bar 2-9. 2-12 supported operating systems 1-6 window managers 1-6 Synopsys Common Licensing 1-5 synthesis. methodology for large violations 4-11 for medium-size violations 4-8 for small violations high-level approach 4-6 introduction 4-5 low-level approach 4-6 timing data. schematic appearance 2-13 printing schematics 3-11 SCL (Synopys Common Licensing) 1-5 scripts command-line interface. changing 2-13 printing 3-11 IN-3 . setting 3-6 initiating 3-8 overview.

Design Vision components of 2-9 modes of initialization 2-7 schematics. overview of 2-2 U using scripts 2-14 V violations. setting 3-6 workspace 2-9 writing to disk 3-9 IN-4 . timing fixing large 4-11 fixing medium size 4-8 fixing small 4-5 judging relative size of 4-4 W window managers. choosing 4-4 timing overview.strategy for closure. supported 1-6 window. creating 4-2 toolbar 2-9 tutorial. setting appearance 2-13 starting and exiting 2-7 wire load models.

Sign up to vote on this title
UsefulNot useful