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GATE-2016 ECE

GATE 2016 Examination


Electronics and Communication Engineering

Test Date: 31/01/2016


Test Time: 9:00 AM to 12:00 PM
Subject Name: ELECTRONICS AND COMMUNICATION ENGINEERING

Section: General Aptitude

Q NO. 1.

Q NO. 2.

Q NO. 3.

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GATE-2016 ECE

Q NO. 4.

Q NO. 5.

Q NO. 6.

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GATE-2016 ECE

Q NO. 7.

Q NO. 8.

Q NO. 9.

Q NO. 10.

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GATE-2016 ECE

Section: Technical

Q NO. 1.

Q NO. 2.

Q NO. 3.

Q NO. 4.

Q NO. 5.

Q NO. 6.

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GATE-2016 ECE

Q NO. 7.

Q NO. 8.

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GATE-2016 ECE

Q NO. 9.

Q NO. 10.

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Q NO. 12.

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GATE-2016 ECE

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Q NO. 14.

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GATE-2016 ECE

Q NO. 15.

Q NO. 16.

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GATE-2016 ECE

Q NO. 17.

Q NO. 18.

Q NO. 19.

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GATE-2016 ECE

Q NO. 20.

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Q NO. 23.

Q NO. 24.

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GATE-2016 ECE

Q NO. 25.

Q NO. 26.

Q NO. 27.

Q NO. 28.

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GATE-2016 ECE

Q NO. 29.

Q NO. 30.

Q NO. 31.

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GATE-2016 ECE

Q NO. 32.

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Q NO. 35.

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GATE-2016 ECE

Q NO. 36.

Q NO. 37.

Q NO. 38.

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GATE-2016 ECE

Q NO. 39.

Q NO. 40.

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GATE-2016 ECE

Q NO. 41.

Q NO. 42.

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GATE-2016 ECE

Q NO. 43.

Q NO. 44.

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GATE-2016 ECE

Q NO. 45.

Q NO. 46.

Q NO. 47.

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GATE-2016 ECE

Q NO. 48.

Q NO. 49.

Q NO. 50.

Q NO. 51.

Q NO. 52.

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GATE-2016 ECE

Q NO. 53.

Q NO. 54.

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GATE-2016 ECE

Q NO. 55.

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GATE 2016 ECE

GATE 2016 Examination


Electronics and Communication Engineering

Test Date: 31/01/2016


Test Time: 9:00 AM 12:00 PM
Subject Name: EC ELECTRONICS AND COMMUNICATION ENGINEERING

Section: General Aptitude


1. [Ans. C]

2. [Ans. B]
The student felicitated the teacher on teachers day for twenty years of dedicated teaching

3. [Ans. C]

4. [Ans. C]

5. [Ans. B]

6. [Ans. D]

7. [Ans. A]

8. [Ans. D]

9. [Ans. C]

10. [Ans. B]

Section: Technical
1. [Ans. *] Range: 1 to 1

2. [Ans. *] Range: 0 to 0

3. [Ans. B]
f(x) decreases, then increases and then increases again

4. [Ans. *] Update soon

5. [Ans. *] Range: 90 to 90

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GATE 2016 ECE

6. [Ans. C]
Generally resistance offered by constant current source is very high
Still, maximum current which can be absorbed by IL is = VS /R

7. [Ans. B]
2 2 4 2
t=0
+ 10 V +
2 0.1 F V 2 5A
c

2
= VC (0 ) is 10 =4V
5
3
+

+ 10 V 2 VC(C)


We know,
v
I = cd
dt
I(s) = C[S V(s) V(0 )]
I(s) = CS V(s)C V(O )
I(s) + CV(0 ) = CS V(s)
I(s) V(0 ) I(s) 4
V(s) = + = +
SC S SC S
2 4 2

0.1 F 2 5A

4 10V 2
+

2 5A


So, VC(E) = VC() [VC() VC(0) ]etRec C
As, Reg = 6 , C = 0.1 F; Reg C = 0.6
= 10 [10 4]eC0.6
VC(t) = 10 6 eE0.6

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GATE 2016 ECE

8. [Ans. *] Update soon

9. [Ans. *] Range: 3 to 3
We know,
v1 = z11 I1 + z12 I2
v2 = z21 I1 + z22 I2
v1
z12 = zc = | = j
I2 I =0
1
v1
z22 = | = zb + zc = 3 + jz
I2 I =0
1
As, zc = j
zb = 3 + j
So, R b = 3

10. [Ans. *] Range: 0.25 to 0.25

11. [Ans. D]
In active, saturation and cut-off modes

12. [Ans. D]

13. [Ans. *] Range: 0.25 to 0.25

14. [Ans. *] Range: 598.60 to 599


VCC = 6V

R1 I1 = 1mA I0

Q1 Q2

R2

6 0.7
R1 = = 5.3 k; Given circuit is wildar current soruce, so
103
I1
Io R 2 = VT ln ( )
I0
R 2 = 10 26 903 (2.302)
4

R 2 = 598.672

15. [Ans. *] Update soon

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GATE 2016 ECE

16. [Ans. A]
The device parasitic capacitances behave like open circuits whereas coupling or bypass
capacitances behave like short circuit

17. [Ans. *] Range: 1.5 to 1.5

18. [Ans. A]

19. [Ans. *] Range: 1 to 1


1 s2
G(s) =
s (s + 1)(s + 3)
1 (s 2) A B C
= = + +
s (s + 1)(s + 3) s s + 1 s + 3
s 2 = A(s + 1)(S + 3) + b s(s + 3) + C(s)(s + 1)
At s = 0 At s = 1 At s = 3
z = A3 3 = B(1)(+2) 5 = C(3)(2)
2 +3 5
A= B= C=
3 2 6
2 1 3 1 5 1
y(s) = +
3 5 2s +1 6s + 3
2 3 t 5 3t
y(t) = + e e
3 2 6
dy(t) 3 t 5 et
= e + e
dt 2 2
At E 0t
dy(t) 3 5
| = + =1
dt t=0t 2 2

20. [Ans. *] Update soon

21. [Ans. *] Update soon

22. [Ans. *] Update soon

23. [Ans. B]

24. [Ans. D]

25. [Ans. *] Range: 32 to 33

26. [Ans. *] Update soon

27. [Ans. *] Range: 0 to 0

28. [Ans. *] Range: 0.8 to 0.9

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GATE 2016 ECE

29. [Ans. *] Range: 3 to 3

30. [Ans. D]
1
A
1/3 4/3
1/3
1
4/3
1/3
B 4/3

Convert inner network to star


Now convert inner star to
3 16/9 16 3
= =3 = 4
4/3 9 4
So, equivalent circuit will be
4

A
1
1 4
1
B

4
4 4 8
14 = + =
5 5 5
8 4
8 4 55
or = 12
5 5
5
32 1
= =
12 5
32 16 8
= = =
60 30 15
8
R ab = = 0.533
15

31. [Ans. *] Range: 4 to 5


Vx
Current through R 2 os Vx
5
Apply KVL to loop
60 = 5(0.24 Vx ) + 3(0.2Vx ) + Vx
60 = 1.2 Vx + 0.6Vx + Vx
60
60 = Vx (2.8), Vx = = 21.428 Volts
2.8

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GATE 2016 ECE

21.428
i= = 4.2857 Amp
5

32. [Ans. *] Update soon

33. [Ans. *] Range: 6 to 6

34. [Ans. *] Range: 100 to 100


At t = 0 VC (0 ) = 0V IL = 10A
At t = 0+

1 mH 10 A VC

Inductor equivalent is
di
VL = L = L[SI(S) I(S)]
dt
VL (s) = LS I(S) LI(S)

1 mS
1
3 +
10 10 V SC

At KVL
(S)
10 103 = + SL[I(s)]
SC
1
= I(S) = [ + SL]
SL
2
S LC +1
10 103 = I(S) [ ]
SC
SI
I(S) = 10 103 2
(S LC + 1)
C S
= 10 103
LC (S 2 + 1 )
LC
1 S
= 10 103 1
L (S 2 + )
LC
10 103 1
I(t) = cos ( t)
L LC
1 1 S
or VC (S) = 10 103 1
SL L (S 2 + )
LC
1 1
= 10 103 1
LC (S 2 + )
LC
1
= 108 10 103
(S 2 + 108 )

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GATE 2016 ECE

104
= 10 103 104
S 2 + (104 )2
VC (t) = 100 sin(104 t)
Since VC (t)U sinuoidal function are cannot find its value at t = so it undefined

35. [Ans. B]

36. [Ans. A]

37. [Ans. *] Range: 32 to 33

38. [Ans. *] Range: 1.1 to 1.3

39. [Ans. *] Update soon

40. [Ans. *] Update soon

41. [Ans. *] Update soon

42. [Ans. C]
Address can be given by
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
Here A0 to A11 is used for address so A15 to A12 is used for chip select
) = A15 + A14 + A13 A12 + A
(CS 13 A
12

43. [Ans. B]

44. [Ans. C]

45. [Ans. *] Update soon

46. [Ans. *] Update soon

47. [Ans. *] Range: 100 to 100


Change of slope is at BW = 100
So, P1 = 100

48. [Ans. *] Update soon

49. [Ans. *] Update soon

50. [Ans. *] Update soon

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GATE 2016 ECE

51. [Ans. *] Update soon

52. [Ans. D]
d

C = A/d
If New separation = 2d then
F 1
C= ; E1 = CV 2
2d 2
1C 2
E2 = V
22
E
So E2 =
2

53. [Ans. *] Update soon

54. [Ans. *] Range: 0.1 to 0.1

55. [Ans. C]

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GATE 2016 ECE

ANALYSIS OF GATE 2016


Electronic & Communication Engineering

NETWORK 10%

CONTROL
SYSTEM 8%

SIGNAL & SYSTEM 5%


MATHS 12%

EMT 12%
ANALOG CIRCUITS 11%

EDC 9% COMMUNICATION 10%

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GATE 2016 ECE

ECE ANALYSIS-2016_31-JAN_MORNING
No. OF Level of Total
SUBJECT Topics Asked in Paper
QUESTIONS Toughness Marks

1 M: 4 Star-Delta; Basic Networks;


Networks Dependent Source; EASY 10
2 M: 3 Maximum Power Transfer
Bode Plot; Time Response;
Control 1 M: 2
System
Nyquist Plot; Initial Value EASY 8
2 M: 3 (L.T)
Signals & 1 M: 1 Digital filters; Energy and
Systems Power; DFT
EASY 5
2 M: 2
DAC; Flip-flop; Finite State
Digital & uP
1 M: 2
Machines*, Memory MODERATE 8
2 M: 3 Interface
Analog 1 M: 3 Op-Amp; Elber-Moll Model;
Circuits Current Mirror;
TOUGH 11
2 M: 4
Com. 1 M: 4
Systems
Random Process TOUGH 10
2 M: 3
1 M: 1
EDC P-n Junction; NMOS MODERATE 9
2 M: 4
Optical Fibers*;
1 M: 4 Electrostatics; Lorentz
EMT
Force Uniform Plane
MODERATE 12
2 M: 4
Waves; Transmission Lines
Joint Distribution*; Analytic
Engineering 1 M: 4 Function; Greens Theorem;
Mathematics Eulers Method; Eigen
MODERATE 12
2 M: 4
Values;
Verbal Ability; Time and
1 M: 5 Work; Directions; Venn
GA
Diagrams; Mensuration and
EASY 15
2 M: 5
Area; Clock
Total 65 MODERATE 100

* Indicates Questions from New Syllabus

Faculty Feedback: Quite a few questions came from New Syllabus; General Ability was pretty
easy; Not many calculations except from Electronic Devices; Time
Management very critical.

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