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Chapter 5: Timers and Counters

Computer Aided Manufacturing TECH 4/53350 1


Ladder Logic
Learning objectives

Describe the use of timers and counters in ladder


logic

Describe such terms as retentive,


retentive cascade,
cascade delay on
and delay off

E l i the
Explain th operation
ti off TON,
TON TOF,
TOF and
d RTO timers
ti

Explain
p the use of CTU and CTD timers

Utilize timers and counters in ladder logic

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Timers
Overview

Ti
Timers are used
d to
t delay
d l actions
ti
Keep an output on for a specified time after an input turns off
Keep an output off for a specified time before it turns on

Timing functions are vital in PLC applications


Cycle times are critical in many processes

Many PLCs use block-type timers and counters


Compliance with IEC 61131-3 standards

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Block-Type Timer
E
Example
l

TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Above Timer is labeled T4:0

Ti
Timer Attributes
A ib
Time Base:
Timers are typically
yp ypprogrammed
g with several different time bases
1 second, 0.1 second, 0.01 second, 0.001 second
Suppose time base is set to 0.1 and Delay increments is set to 50
timer has 5 seconds delay (0.1 x 50)

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Block-Type Timer
Example

TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Preset Attribute:
Preset value is the number of time increments timer must count
before changing the state of the output
Time Delay = Preset value x Time Base ( refer to previous example)
Preset can be constant or a variable

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Block-Type Timer
Example
TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Accum Attribute:
[Rockwell] Timers have one input. When the input transits from low
to high, the timer will begin timing (Accum value)
Timers that do not lose their accumulated time when the enable input line
transitions to low again are known as Retentive Timers
Retentive Timers continue to maintain accumulated time and increment
the time when the input line goes to high again
Non-retentive Timers lose the accumulated time whenever the enable
input transitions to low
The accumulated time resets to zero

Computer Aided Manufacturing TECH 4/53350 6


Timer Block
Numbering System
TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Above Timer is calledT4:0

T File Type
Fil T (Timer)
(Ti )
4 File Number of the Timer
Timer T4:0 : Delimiter
0 Element (The actual timer number)

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Block-Type Timer
E
Example
l

TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Timer On (TON) Delay

Timer On Delay
y Instruction:
Turns an output on after a Timer has been on for a preset time
interval
TON starts accumulating
g time when rung g becomes true
Continue accumulating until one of the following occurs:
Accumulated (Accum) value equals preset value
The rung conditions becomes false

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Block-Type Timer
Status Bits (EN, DN, TT)

Timer Status bits can be used in ladder logic

Bit S t When
Set Wh R
Remains
i Set
S t Till
Timer done Bit Accumulated value is Rung conditions go false
(bit 13 or DN) equal to or greater than the
preset value
Timer Timing bit Rung conditions are true Rung conditions go false or
(bit 14 or TT) and the accumulated value when the done bit is set
is less than the preset
value
Timer enable bit Rung conditions are true Rung conditions go false
(bit 15 or EN)

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Using Status Bits in Ladder Logic
EN Bit

Timer Enabled bit can be used in ladder logic


Consider timer T4:0 from the example:
The Timer Enable (EN) bit is set immediately when the rung
goes true. It stays set until the rung goes false

The EN bit indicates that the timer T4:0 is enabled

The EN bit from any timer can be used for logic:

T4:0/EN could be used as a contact in a ladder

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Using Status Bits in Ladder Logic
TT Bit

Timer Timing (TT) bit can be used


sed in ladder
logic
C
Consider
id timer
ti T4
T4:0
0 from
f the
th example:
l
The Timer Timing (TT) bit is set when the rung goes true. It stays
set until the rung goes false or the Timer Done (DN) bit is set (i
(i.e.,
e
when accumulated value equals preset value)

The TT bit from any timer can be used for logic:

T4:0/TT could be used as a contact in a ladder

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Using Status Bits in Ladder Logic
DN Bit

Timer Done bit can be used


sed in ladder logic
Consider timer T4:0 from the example:
The Timer Done (DN) bit is not set until the accumulated value is
equal to the preset value. It stays set until the rung goes false

When DN bit is set, it indicates Timing operation is complete

The DN bit from any timer can be used for logic:

T4:0/DN could be used as a contact in a ladder

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Using Other Bits in Ladder Logic
Preset (PRE)
PRE can be used in ladder logic
T4:0 PRE would access the preset value of T4:0
T4:0.PRE
Note, PRE value is an integer

Accumulated Value (ACC)


T4:0.ACC would access the accumulated value of timer T4:0

Time Bases are available in 1 second intervals, 0.01 and 0.001


second intervals
Time Base Potential Time Range
Potential time ranges:
1 Second To 32,767 intervals (up to
9.1 hrs)
0 01 Second
0.01 To 32,767
32 767 intervals (up to
5.5 minutes)
0.001 Second To 32,767 intervals (up to
0.546 minutes)
What if a longer time is needed?

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Memory Storage
Timers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits
EN TT DN
Internal Use 0 T4:0
Preset Value 1 T4:0.PRE
Accumulated Value 2 T4:0
T4:0.ACC
ACC

Current status of timer bits (EN, TT and DN) stored in first 16 bits
PRE value is held in the second 16 bit of timer storage
Third 16 bit holds accumulated value of timer

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TON Timer
Ladder Diagram TON
I:2 TIMER OFF DELAY EN
Timer T4:0
Time Base 1.0
Preset 180 DN
3
Accum 0
T4:0
O:5

TT 1

T4:0
O:5

2
DN

When input I:2/3 is true timer begins to increment the accumulated value of TON Timer
T4:0 in 1 second intervals
The TT bit is used in rung 2 to turn on Output O:5/1, while the timer is timing (ACC <PRE)
The DN bit of timer 4:0 is used in rung 3 to turn an output O:5/2 when the timer is done
timing (ACC = PRE)
Note: the Preset for this timer is 180 The timer will have to accumulate 180 1-second intervals to time
out
Note: This is a non-retentive timer: If Input I:2/3 goes low before 180 is reached, the accumulated value
is reset to zero

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Timer OFF Delay
TOF
Timer OF (TOF) -Delay
Used to turn an output On or OFF after rung has
been off for a desired time
1. TOF starts to accumulate time when the rung becomes false

2. It continues to accumulate time until the accumulated value


equals the preset value or the rung becomes true

3. The timer enable bit (EN bit 15) is set when the rung becomes
true. It is reset when the rung becomes false and ACC < PRE or
the DN bit is reset (ACC = PRE)

4. The done bit (DN bit 13) is reset when the ACC value is equal to
g becomes true
the PRE value. The DN bit is set when the rung

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Timer Off Delay
TOF Bits

Bit S t When
Set Wh R
Remains
i Set
S t Till

Timer done Bit Rung conditions are true Rung conditions go false
(bit 13 or DN) and the accumulated value
is greater than or equal to
the preset value
Timer Timing bit Rung conditions are false Rung conditions go true or
(bit 14 or TT) and the accumulated value when the done bit is reset
is less than the preset
value
Timer enable bit Rung conditions are true Rung conditions go false
(bit 15 or EN)

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Ladder Logic
TOF Timer TOF
I:2 TIMER OFF DELAY EN
Timer T4:0
Time Base 1.0
Preset 180 DN
3
Acc 0
T4:0
O:5
This output is energized while the timer is timing

TT 1

T4:0
This output is energized when the timer is done timing O:5

DN 2

Input I:2/3 is used to enable the timer


When input I:2/3 transitions from true to false The ACC value is incremented
as long as the input stays false and ACC PRE
The TT bit for timer T4:0 (T4:0/TT) is used to turn output O:5/1 on while timer is
timing
The DN bit of timer 4:0 (T4:0/DN) is used to turn on output O:5/2 when the timer
has completed the timing (ACC = PRE)

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Retentive Timer On
RTO
RTO Instruction:
Used to turn an output On after a set time period

1. The RTO timer is an accumulating timer. It retains the ACC


value
l even if th
the rung goes ffalse
l

To zero the ACC value, use a reset (RES) instruction in another rung with
the same address as the RTO

2. The status bits can be used as contacts in the ladder diagram

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Retentive Timer On
Status Bits
Bit Set When Remains Set Till

Timer done Bit Accumulated value The appropriate RES


(bit 13 or DN) preset value Instruction is enabled
Timer Timing bit Rung conditions are true Rung conditions go false
(bit 14 or TT) and the accumulated value or when the done bit is set
< preset value

Timer enable bit Rung conditions are true Rung conditions go false
(bit 15 or EN)

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Ladder Logic
RTO Timer
RTO
I0:2 TIMER OFF DELAY EN
Timer T4:0
Time Base 10
1.0
Preset 180 DN
3
Accum 0

I0:2 T4:0

RES

EN bit is set when rung becomes true


When EN is 1 Indicates Timer is timing
Note: EN remains 1until rung becomes false
TT bit is set when rung becomes true and remains set until ACC value equals
the preset value or RES instruction resets the timer
DN bit is set when the timers ACC value is equal to the preset value
When DN bit is set it indicates timing is complete

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Cascading Timers

When Application requires longer time delays


than a single timer can provide
Use multiple timers
When the first timer times out, it becomes an input to
start the second timer timing
Cascading Timers
TON
O
I:2.0 TIMER ON DELAY EN
Timer T4:0
Time Base 1.0
DN
1 Preset 32,767
Accum 0

TON
T4:0 TIMER ON DELAY EN
Timer T4:1
Time Base 1.0
Preset 7233 DN
DN
Accum 0

Two timers are used to extend the time delay


The first timer output, T4:0/DN, acts as input to second timer
When Input I:2.0 becomes true, timer 1 begins to count to 32,767
seconds (the limit of the timers)
When it gets to 32,767 seconds, output T4:0/DN turns on
This energizes timer T4:1
Timer T4:1 times to 7233 seconds (its preset value)
T4:1/DN turns on

What is the delay?

23
Counters

Counting is critical in industrial applications


Suppose 24 can go into a case
Then the 24th can must be sensed by the PLC
and the case is sealed
Primaryy Counter
C Types
yp
UP Counters - PLC sense how many finished products leaving the machine
Down Counters - PLC sense how many parts are left
Up/Down Counters - PLC monitors an automated storage system to track how
many are coming and how many are leaving to determine total number in stock
Choice used depend on the task
Counters
A ib
Attributes
Counters usually use low-to-high
low to high transition from
an input to trigger the counting action
Counters count the number of low-to-high g
transitions on the input line
Similar to Timers, which count the number of time
increments
Counters also have a reset instruction to clear
th accumulated
the l t d countt
Counters (CTU) CTU

Edge-Triggered
Edge Triggered I:2 Count Up
Counter C5:0
EN

Preset 10
Accum 0 DN
3

C5:0
O:5
Energized when the Accum >= Preset

DN 1

Input I:2/3 On
Status Of

Output O:5/1 On
Of
Status
0 1 2 10 11

The rising edge triggers the counter


I:2/3 counts the pulses:
Each time there is an Of to On transition, the Counter increments its count by 1 (CTU)
When the Accumulate count equals the preset value, the counter turns on
Turns on Output O:5/1
How does CTD work?

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Counters
Numbering System
How counters are addressed:

C File Type
5 File Number of the counter
C5:0 : Delimiter
0 Element (The actual counter number)

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Counters in Ladder Logic
Accessing Counter Values

To use the Done Bit: C5 4 DN


C5:4.DN
To use the Preset Value C5:4.PRE

To use the Accumulated Value C5:4.ACC

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Memory Storage
CTU Counter Bits
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Element
CU DN OV
Internal Use 0 C5:0
Preset Value 1 C5:0.PRE
Accumulated Value 2 C5:0
C5:0.ACC
ACC

Count Up
p ((CU),
), Done ((DN)) and Overflow ((OV)) bits are stored in first 16 bits
The CPU sets the OV bit when the counter exceeds upper limit +32,767
ACC wraps around to -32,767 and continues from there towards zero
PRE value is held in the second 16 bit of counter storage
Thi d 16 bit h
Third holds
ld accumulated
l t d value
l off counter
t

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CTU Counter Bits

Bit S t When
Set Wh R
Remains
i Set
S t Till

Count-up Overflow bit Accumulated value wraps A RES instruction that has
(bit 12 or OV) around to -32,768 (from same address as the CTU
+32 767) and continues up
+32,767) instruction is executed or
from there towards zero the count is decremented
less than or equal to
+32,767 with a CTD
instruction
Done bit The accumulated value is The accumulated value
(bit 13 or DN) => the preset value becomes less than the
preset value
Count up enable bit (bit 15
Count-up Rung conditions are true Rung conditions go false or
or CU) a RES instruction that has
the same address as the
CTU instruction is enabled
Count-Up Counter CTU

Ladder Diagram I:2 COUNT UP


Counter C5:0
EN

Preset 4
Accum 0 DN
3

C5:0
O:5
Energized
g when the Accumulated Preset

DN 1

C5:0
Energized
g when the counter overflows O:5

OV 2

Input I:2/3 is used to enable the counter


Each time I:2/3 makes a low-to-high transition, the counter ACC value gets
incremented by1
The DN bit is set when the ACC value the Preset value
The DN bit of C5:0 (C5:0/DN) is used to turn on O:5/1 when ACC Preset value
The OV bit of C5:0 (C5:0/OV) is used to set O:5/2 when <What happens?>
See next slide

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Count-Up Counter CTU

Ladder Diagram I:2 COUNT UP


Counter C5:0
EN

Preset 4
Accum 0 DN
3

C5:0
O:5
Energized
g when the Accumulated >= Preset

DN 1

C5:0
Energized
g when the counter overflows O:5

OV 2

I:2 C5:0
Reset
ese cou
counter
e to
o zero
eo
RES

The OV bit of C5:0 (C5:0/OV) is used to set O:5/2


if the count reaches +32,767
Bit 1 of contact I:2/1 is set to true(1) this causes the RES instruction to reset CTU C5:0s ACC value (i.e
Accum) to zero

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Count-Down Counter CTD

Ladder Diagram I:2 COUNT DOWN


Counter C5:0
CD

Preset 4
Accum 0 DN
3

C5:0
O:3
Energized
g when the Accumulated Preset

DN 1

C5:0
Energized
g when the counter underflows O:3

UN 2

I:2 C5:0
Resets
ese s cou
counter
e to
o zero
eo
RES

1
Input I:2/3 is used to enable the counter
Each time input I:2/3 makes a 01 transition, the counter ACC value gets decremented by1
The DN bit is set when the ACC value the Preset value
The DN bit of C5:0 (C5:0/DN) is used to turn output O:3/1 on when Accum Preset value
The UN bit of C5:0 (C5:0/UN) is used to set OUTPUT O:3/2 ON when the ACC value
underflows (-32,768)
Input I:2/1 is used to reset the C5:0s ACC value to zero

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CTD Counter Bits

Bit S t When
Set Wh R
Remains
i Set
S t Till

Count-down Underflow bit Accumulated value wraps A RES instruction that has
(bit 11 or UN) around to +32,768 (from: same address as the CTD
-32,767)
32 767) and continues instruction is executed or
counting from there the count is incremented
greater than or equal to
+32,767 with a CTU
instruction
Done bit The accumulated value is The accumulated value
(bit 13 or DN) the preset value becomes less than the
preset value
Count down enable bit (bit
Count-down Rung conditions are true Rung conditions go false or
14 or CD) a RES instruction that has
the same address as the
CTDinstruction is enabled
Memory Storage
CTU and CTD Counter Bits
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Element
CU CD DN OV UN
Internal Use 0 C5:0
Preset Value 1 C5:0.PRE
Accumulated Value 2 C5:0
C5:0.ACC
ACC

Count Up (CU), Count Down (CD), Done (DN), Overflow (OV) and
Underflow (UN) bits are stored in first 16 bits
The CPU sets the OV bit when the counter exceeds upper limit +32
+32,767
767
ACC wraps around to -32,767 and continues incrementing from there towards
zero to +32,767
The CPU sets the UN bit when the counter exceeds lower limit -32,767
ACC wraps aroundd tto +32,767
32 767 and
d continues
ti d
decrementing
ti ffrom th
there ttowards
d
zero to -32,767
PRE value is held in the second 16 bit of counter storage
Third 16 bit holds accumulated value of counter

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Cascading Counters
CTU
I:2.0 COUNT UP EN
Counter C5:0
Preset 24
1 Accum 0 DN

CTU
C5:0 COUNT UP EN
Counter C5:1
Preset 5000
DN
DN Accum 257

C5:0
RES

Two counters are used to extend the count


Counter C5:0 is used to count 24 cans for each case
When C5:0 ACC value 24, DN bit is set
The CTU C5:0/DN energizes CTU C5:1
The C5:1 Acc value is incremented to count number of cases of 24 cans
The ladder diagram shows 257 cases of 24 cans

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