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VOLTAGE RESTORER

1

Research Scholar, Pondicherry University, Puducherry 605 014

+91-0413-2655281, +91-0413-2655101, E-mail: jamuna1981@gmail.com

2

Professor, Pondicherry Engineering College, Puducherry 605 014

+91-0413-2655281, +91-0413-2655101, E-mail: asir_70@pec.edu

Abstract: In this paper, a new topology for multilevel H-bridge (CHB). The main drawbacks of NPC

converter based on sub-multilevel converter units and full- topology are their unequal voltage sharing among

bridge converters is proposed. The proposed topology series connected capacitors that result in dc-link

significantly reduces the number of dc voltage sources and

capacitor unbalancing and requiring a great number of

switches as the number of output voltage levels increases.

To synthesize maximum levels at the output voltage and to clamping diodes for higher level. The FC multilevel

reduce the total harmonic distortion (THD), three different converter uses flying capacitor as clamping devices.

control strategies are proposed. The operation and These topologies have several attractive properties in

performance of the proposed multilevel converter have been comparison with the NPC converter, including the

analysed and simulated in the MATLAB software and the advantage of the transformerless operation and

results are presented for single-phase 25-level converter. redundant phase leg states that allow the switching

Dynamic Voltage Restorer is a power electronic device that

stresses to be equally distributed between

is used to inject 3-phase voltage in series and in

synchronism with the distribution feeder voltages in order to semiconductor switches. But, these converters require

compensate voltage sag. The principle component of the an excessive number of storage capacitors for higher

DVR is a voltage source inverter that generates three phase voltage steps. The CHB topologies are proper option

voltage and provides the voltage support to a sensitive load for high level applications from point of view of

during voltage sags. The improved version of proposed modularity and simplicity of control. But, in this

multilevel inverter with reduced THD is used in DVR to topology, a large number of isolated dc voltage sources

compensate the voltage sag in power system and if any fault

are required to supply each conversion cell. It increases

occurs in power system thereby reduce the voltage variation

in distribution side. Simulation of DVR has been developed the converter cost and complexity.

by using Matlab/Simulink. In multilevel converter, the power quality is

improved as the number of levels increases at the

Key words: Asymmetric Multilevel Inverter, DVR, ISPWM, output voltage. However, it causes to the increasing

MSPWM, SHPWM, THD.

number of switching devices and other components,

1. Introduction and increases the cost and control complexity and tends

The basic concept of a multilevel converter is to use to reduce the overall reliability and efficiency of the

a series of power semiconductor switches that properly converter. It is noticeable that multilevel converters can

connected to several lower dc voltage sources to sustain the operation in case of internal fault. In the

synthesize a near sinusoidal staircase voltage case of internal fault of one cell of FC converter, the

waveform. The small output voltage step results in high maximum output voltage remains constant, but the

quality output voltage, reduction of voltage stresses on number of levels decreases. On the other hand, when

power switching devices, lower switching losses and an internal fault is detected in the CHB converter, and

higher efficiency. Numerous multilevel converter the faulty cell is identified, it can be easily isolated

topologies and wide variety of control methods have through an external switch and replaced by a new

been developed in [1]-[4]. Three different basic operative cell [7].

multilevel converter topologies are the neutral point Asymmetric and/or hybrid multilevel converters have

clamped (NPC) or diode clamped [5-6], the flying been presented in [8]. In the asymmetric topologies, the

capacitor (FC) or capacitor clamped and the cascaded values of dc voltage sources magnitudes are unequal or

changed dynamically [9]. These converters reduce the

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size and cost of the converter and improve the structure of the proposed topology is optimized for

reliability since fewer semiconductors and capacitors various aims. Finally, a design example of the proposed

are employed [10]. The hybrid multilevel converters multilevel converter is included.

are composed of different multilevel topologies with

unequal values of dc voltage sources and different 2. Proposed Multilevel Converter

modulation techniques and/or semiconductor The basic unit of the sub multilevel converter, is

technologies [8]. With appropriate selection of presented in [19-20], is illustrated in Fig. 1(a). It

switching devices, the converter cost is significantly consists of several dc voltages and bidirectional

reduced. But, the application of different multilevel switches. If n voltage sources are used, n+ 1 different

topologies result in loss of modularity and produces value can be obtained for vo, by n + 1 bidirectional

problems with switching frequency and restrictions on switches. The output voltage of this sub multilevel

the modulation and control method [11]. converter has zero or positive values. The presented

The researchers are strived in [12] to introduce a new unit requires bidirectional switches with the capability

topology for multilevel converters with a reduced of blocking voltage and conducting current in both

number of components compared to conventional directions. Several arrangements can be used to create

multilevel converters. This topology is composed of bidirectional switches.

modular sub multilevel converters that makes it easily

extensible to higher number of output voltage levels

without undue increase in the power circuit complexity

and reduces controller design cost. By the presented

algorithm in [12], it is not possible to create all levels

(odd and even) at the output voltage, and it reduces the

flexibility of the converter. Also, to create the output

voltage with a constant number of levels, the converter

needs many large numbers of bidirectional switches.

To overcome these disadvantages, [13] has presented a

new topology, which has decreased the number of

bidirectional switches and dc voltage source compared

to [12] and with the ability of the production of all

levels at the output voltage. The main drawback of this

topology is the utilization of unidirectional switches

that operate in the high output voltage.

The structures, based on similar concepts, have been

presented in [14-15]. In these topologies, the dc source

is formed by connecting a number of half-bridge cells,

diode-clamped phase leg or capacitor-clamped phase Fig. 1(a): Proposed Multilevel Inverter

leg. Also, in [16-18], the topology has been obtained

from the mixture of the FC and CHB inverter. These The proper configuration of bidirectional switches is

structures provide a high number of output levels using arranged by a common emitter connection of two

low number of components. But, the main drawback of IGBTs, with each one of IGBTs has an anti parallel

these topologies is the utilization a full-bridge diode. Because the emitters of two IGBTs are common,

converter, which operates in the high output voltage. the base voltage of each IGBT can be measured versus

Also, these designs are not flexible. its common emitter. Therefore, a bidirectional switch

This paper proposes a new modular and simple requires a gate driver circuit in this configuration. This

topology for cascaded multilevel converter that configuration of bidirectional switch is used in this

produces a high number of levels with the application paper, to make it comparable with one presented in

of a low number of power electronic components. [19-20]. The typical output waveform is shown in Fig.

Then, a procedure for calculating the values of required 1 (b).

dc voltage sources is also proposed. In addition, the

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seen, 2n + 1 different value can be obtained for Vo.

TABLE I: VALUES OF THE OUTPUT VOLTAGE OF MLM

3. Improved Version of Proposed Technology

The cascaded connection of these sub multilevel The proposed multilevel converter topology, which

converters increases the possible value of Vo, is based on the combination of MLMs and full-bridges

effectively. But, it can only generate the positive output converters, is shown in Fig. 2. The structure of the

voltages. To generate both positive and negative first till kth MLM has n1, n2, . . . , nk bidirectional

voltages, a full-bridge converter is connected to the switches, respectively. Each MLM can generate a

output terminal of the cascaded connection of sub stepped voltage waveform with positive polarity. The

multilevel converters. But, the unidirectional switches full-bridge converters provide positive and negative

in the full-bridge converter and some bidirectional stepped voltage waveforms in their output.

switches, such as S1, must operate at the high output

voltage and need higher voltage blocking. As a result,

the cost and losses will be increased and its industrial

applications will be limited.

Fig. 2 shows the proposed topology for a sub

multilevel converter, hereafter called multilevel module

(MLM), which is used for the implementation of the

proposed multilevel converter topology. It consists of n

dc voltage sources and n bidirectional switches. A

MLM produces a staircase voltage waveform with

positive polarity. It is connected to a single phase full-

bridge converter, which particularly alternates the input

voltage polarity and provides positive or negative

staircase waveform at the output. The full-bridge

converter has four unidirectional switches, which

consists of an IGBT and an anti parallel fast recovery Fig. 2: Improved Version of Proposed Multilevel

diode. It is noticeable that only one switch turns on in Inverter

different operation modes of the MLM and also, both

switches T1 and T4 (or T2 and T3) cannot be The different output voltage levels can be

simultaneously turned on (expect state 1 in Table I) determined by the combination of switching states of

because of a short circuit occurrence across dc voltage MLMs. It is obvious that only one switch of each

sources and then the voltage Vo would be produced. MLM turns on in different operation modes of the

Table I summarizes the values of the output voltage of converter without considering the zero voltage state of

a MLM and corresponding full-bridge converter for MLMs.

different state of switches S1, S2, . . . , Sn, T1, . . . , T4. It should be noted that the capacitors can be replaced

State conditions 1 and 0 means that the switch is on with the dc voltage sources in the proposed topology.

and off respectively. For simplicity, the on state voltage Although this topology requires multiple dc voltage

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sources, but they may be available in some systems width of each pulse is varied in proportion to the

through renewable energy sources, such as photovoltaic amplitude of a sine wave evaluated at the centre of the

panels or fuel cells, or with energy storage devices, same pulse. The distortion factor and lower order

such as capacitors or batteries. When ac voltage is harmonics are reduced significantly. The gating signals

already available, then, multiple dc sources can be are generated by comparing a sinusoidal reference

generated using isolated transformers and rectifiers, too signal with a triangular carrier wave of frequency Fc.

[12]. The frequency of reference signal Fr, determines the

If the dc voltage sources are considered to be equal inverter output frequency and its peak amplitude Ar,

in MLMs, the structure of the proposed topology will controls the modulation index M, and rms output

be symmetrical. In the asymmetrical structure of the voltage V0. The number of pulses per half cycle

proposed topology, similar to the asymmetrical depends on carrier frequency.

cascaded multilevel converter, there is only one

4.2 ISPWM Strategy

switching state for each output voltage level (except the

zero level) to produce unequal values for vo. In this This method provides an enhanced fundamental

paper, to reduce the number of components, the voltage, lower total harmonic distortion (THD) and

asymmetrical structure has been studied. It is minimizes the switch utilization among the various

noticeable that the asymmetrical structure has levels in inverters. In this method the control signals

circulating energy problems. Therefore, if diode-based have been generated by comparing sinusoidal reference

rectifiers are used for dc voltage sources, their dc-link signal with a high frequency inverted sine carrier. The

voltages can increase their values dangerously. carrier frequencies are so selected that the number of

Considering the first dc voltage source (V11) as the switching in each band are equal. The proposed

base value of the per-unit system, i.e., modulation technique maximizes the output voltage

and gives a low THD.

Vbase V11 Vdc (1)

4.3 MSPWM Strategy

Then, the normalized values of the dc voltage

sources for producing all levels (odd and even) in the This technique involves comparing several absolute

output must be chosen using the following algorithm. sinusoidal modulation signals with single triangular

For module 1 carrier. This carrier signal is a train of triangular waves

with frequency fc and amplitude Ac. The single phase

V11 Vdc (2) multilevel inverter is modeled in SIMULINK in the

software package MATLAB 10. Switching signals for

inverter are developed using the above mentioned

V1i V11 Vdc , i 2,..., n1 PWM techniques. Fig.3 and Fig.4 shows the

(3) Output voltage waveform and FFT analysis using

n1 SHPWM technique with fixed frequency for the

V21 V11 2V (2n1 1)Vdc proposed inverter (5 levels).

i 1 1i (4) Fig. 5 and Fig. 6 shows the Output voltage

waveform and FFT analysis using SHPWM technique

V2i V21 (2n1 1)Vdc , i 2,..., n2 (5)

with variable frequency.

k

N level (2ni 1)

i 1 (6)

(2n1 1) x(2n2 1) x...x(2nk 1)

4. Control Strategies

Fig. 3: Output Voltage Waveform Using SHPWM

Instead of, maintaining the width of all pulses of Technique with Fixed Frequency (SHPWM)

same as in case of multiple pulse width modulation, the

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Fig. 4: FFT Analysis Using SHPWM Technique with Fig. 8: FFT Analysis Using ISPWM Technique with

Fixed Frequency Fixed Frequency

and FFT analysis using ISPWM technique with

variable frequency.

Technique with Variable Frequency (SHPWM)

Technique with Variable Frequency

Variable Frequency

waveform and FFT analysis using ISPWM technique Fig. 10: FFT Analysis Using ISPWM Technique

with fixed frequency for the proposed inverter (5 with Variable Frequency

levels).

Fig. 7: Output Voltage Waveform Using ISPWM Technique with Fixed Frequency

Technique with Fixed Frequency

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MSPWM Technique. Fig.12 shows the FFT Analysis

Using MSPWM Technique.

with Fixed Frequency

Fig. 12: FFT Analysis Using MSPWM Technique analysis using SHPWM technique with variable

with Fixed Frequency frequency for the improved inverter (25 levels). Fig.

16 shows the FFT analysis using SHPWM technique

TABLE II: COMPARISON OF BASIC UNIT with variable frequency.

From the Table II, the SHPWM with fixed frequency Fig. 15: Output Voltage Waveform Using SHPWM

has less total harmonic distortion. Fig.13 shows the Technique with variable frequency

Output Voltage Waveform Using SHPWM Technique

with Fixed Frequency for improved version (25 levels).

Fig.14 shows the FFT Analysis Using SHPWM

Technique with Fixed Frequency.

with variable Frequency

Fig. 13: Output Voltage Waveform Using SHPWM

waveform and FFT analysis using ISPWM technique

Technique with Fixed Frequency

with fixed frequency for the improved inverter (25

levels).

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Fig. 17: Output Voltage Waveform Using ISPWM Fig. 21: Output Voltage Waveform Using MSPWM

Technique with Fixed Frequency Technique

waveform and FFT analysis using MSPWM technique

for the improved inverter (25 levels).

with Fixed Frequency

frequency has less total harmonic distortion.

Technique with variable Frequency

waveform and FFT analysis using ISPWM technique

with variable frequency for the improved inverter (25

levels).

SHPWM, ISPWM and MSPWM are tabulated for 5-

levels and 25-levels. It can be seen that SHPWM

technique yields a better performance than other

techniques.

Fig. 20: FFT Analysis Using ISPWM Technique

with variable Frequency DVR is a power electronic based device that injects

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voltage into the system to regulate the load side voltage 0.5s. Fig. 24 and Fig. 25 shows the voltage and

[17],[18]. It is normally installed between supply and current waveforms.

critical load feeder. The basic function of DVR is to

boost up the load side voltage in the event of

disturbance in order to avoid any power disruption to

the load. There are many control technique available to

implement the DVR. The primary function of DVR is

to compensate voltage sags and swells but it can also

perform the tasks such as: harmonic compensation,

reduction of transient in voltage and fault current

limitation.

Fig. 24: Output Voltage Waveform For Voltage Sag

The main parts of DVR are:

injection transformer,

harmonic filter,

a voltage source converter,

energy storage device

control & protection system

components: supply, dynamic voltage restorer and

load. The detailed model description of Dynamic

Voltage Restorer is presented in following paragraphs

of software development Fig. 25: Output current Waveform For Voltage Sag

and maintained sensitive to its nominal value. Then the

voltage sag can be compensated by DVR. Fig. 26

and Fig. 27 shows the voltage and current waveforms

after compensation.

compensation is shown in Fig. 23. Dynamic voltage

Fig. 26: Output Voltage Waveform With DVR

restorer [19] is a series connected device is used for

mitigating voltage disturbances in the distribution

system. Voltage sags caused by unsymmetrical line-to

line, line to ground, double-line-to-ground and

symmetrical three phase faults is affected to sensitive

loads.

Consider a three phase power system with base

voltage - 100V, Frequency - 50 Hz, MVA rating-

100MVA. Due to voltage sag in power system the

output voltage and current are disturbed between 0.4-

Fig. 27: Output Current Waveform With DVR

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multilevel converters with non integer or dynamically changing dc

A new basic multilevel module has been proposed. voltage ratios: Concepts and modulation techniques, IEEE Trans. Ind.

Electron., Vol. 57, No. 7, pp. 24112418, Jul. 2010.

The proposed topology and improved version of [10] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M.

proposed topology is analysed and simulated for 5 A. M. Prats, and M. A. Perez, Multilevel converters: An enabling

levels and 25 levels with three different control technology for high-power applications, Proc. IEEE, Vol. 97, No. 11,

pp. 17861817, Nov. 2009.

techniques. The main achievement of this control [11] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. Perez, A

techniques are the reduction in their total harmonic survey on cascaded multilevel inverters, IEEE Trans. Ind. Electron.,

distortion (THD), closer to sinusoidal waveform Vol. 57, No. 7, pp. 21972206, Jul. 2010.

[12] M. T. Haque, Series sub-multilevel voltage source inverters

without the usage of an output filter. Proposed (MLVSIs) as a high quality MLVSI, in Proc. SPEEDAM, 2004, pp.

multilevel inverter reduces the switching losses by F1B-1F1B-4.

[13] E. Babaei, A cascade multilevel converter topology with reduced

reducing number of switches and provides improved number of switches, IEEE Trans. Power Electron., Vol. 23, No. 6, pp.

output voltage capability. It can be observed that 26572664, Nov. 2008.

SHPWM produces a better fundamental output voltage [14] Karuppanan P AyasKanta Swain Kamalakanta Mahapatra, FPGAA

Based Single Phase Cascaded Multilevel Voltage Source Inverter FED

and minimized total harmonic distortion (THD). The ASD Applications, Journal of Electrical Engineering, Vol. 11 ,

proposed topologies can be a good solution for Edition 3, pp. 102-107, 2011.

applications that require high power quality. The [15] G. Su, Multilevel dc-link inverter, IEEE Trans. Ind. Appl., Vol. 41,

No. 3, pp. 848854, May/Jun. 2005.

improved version of proposed multilevel inverter has [16] P. Lezana and J. Rodriguez, Mixed multicell cascaded multilevel

reduced THD and higher output voltage with reduced inverter, in Proc. ISIE, 2007, pp. 509514.

number of switches. So this configuration is used as a [17] J. G. Nielsen, F. Blaabjerg, Control Strategies for Dynamic Voltage

Restorer Compensating Voltage Sags with Phase Jump, Applied

DVR in power system for voltage sag compensations. Power Electronics Conference and Exposition, 2001. APEC 2001.

In case of voltage sag in power system, DVR injects 16th Annual IEEE Vol. 2, 4-8 March 2001, pp 1267-1273

[18] Agileswari, K. Ramasamy, Rengan Krishnan Iyer, Dr. R.N. Mukerjee,

the voltage which is in phase with the supply voltage. Dr. Vigna K. Ramachandramurthy, 2005. Dynamic Voltage Restorer

The load side connected converter topology has for voltage sag compensation, IEEE PEDS, pp: 1289-1293.

capability of mitigating the long duration voltage sags [19] N. Hamzah, M. R. Muhamad, and P. M. Arsad, Investigation On the

Effectiveness of Dynamic Voltage Restorer For Voltage Sag

on the line. Simulation of DVR has been developed by Mitigation, The 5th SCOReD, Dec 2007, Malaysia, pp 1-6.

using Matlab/Simulink. The simulation results show [20] N. Chellammal S.S. DASH P.Palanivel, Performance Analysis of

that the DVR compensates the sag quickly and Multi Carrier Based Pulse Width Modulated Three Phase Cascaded H-

Bridge Multilevel Inverter, Vol. 11, Edition 2, pp. 28-35, 2011.

provides excellent voltage regulation.

7. References

[1] J. Rodriguez, B.Wu, S. Bernet, J. Pontt, and S. Kouro, Multilevel

voltage source converter topologies for industrial medium voltage

drives, IEEE Trans. Ind. Electron., Vol. 54, No. 6, pp. 29302945,

Dec. 2007.

[2] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, Medium

voltage multilevel convertersState of the art, challenges and

requirements in industrial applications, IEEE Trans. Ind. Electron,

Vol. 57, No. 8, pp. 25812596, Aug. 2010.

[3] E. Babaei and S. H. Hosseini, New cascaded multilevel inverter

topology with minimum number of switches, J. Energy Convers.

Manag., Vol. 50, No. 11, pp. 27612767, Nov. 2009.

[4] E. Babaei and M. S. Moeinian, Asymmetric cascaded multilevel

inverter with charge balance control of a low resolution symmetric

subsystem, J. Energy Convers. Manag., Vol. 51, No. 11, pp. 2272

2278, Nov. 2010.

[5] M.Murugesan, Cascaded and Hybrid Multilevel Inverters with

Reduced Number of Switches for Induction Motor, Journal of

Electrical Engineering, Vol. 12 , Edition 1, pp. 175-181, 2012.

[6] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped

PWM inverter, IEEE Trans. Ind. Appl., Vol. IA-17, No. 5, pp. 518

523, Sep. 1981.

[7] A. K. Sadigh, S. H. Hosseini, M. Sabahi, and G. B. Gharehpetian,

Double flying capacitor multi cell converter based on modified phase-

shifted pulse width modulation, IEEE Trans. Power Electron., Vol.

25, No. 6, pp. 15171526, Jun. 2010.

[8] C. Rech and J. R. Pinheiro, Hybrid multilevel converters: Unified

analysis and design considerations, IEEE Trans. Ind. Electron., Vol.

54, No. 2, pp. 10921104, Apr. 2007.

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