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Allegro PSpice Simulator

A unified environment for PCB design, simulation, and analysis

On larger designs especially, PCB design teams need fast andreliable simulation to achieve
convergence. The Cadence Allegro PSpice Simulator provides simulation technology for PCB
design that offers a single, unified design environment for both simulation and PCB design. With
integrated analog and event-driven digital simulation, teams benefit from improved speed without
sacrificing accuracy. Using advanced analysis capabilities, designers can automatically maximize
the performance ofcircuits.

Cadence Simulation and SystemC, Verilog A-ADMS, and Allows for automatic identification
Technology for PCB Design a set of behavioral analog devices and of analog and digital signals
controlled sources. and applies A-to-D and D-to-A
The Allegro PSpice Simulator provides interfaces
a full-featured analog simulator with The products are tightly integrated
support for digital e lements to help with Cadence Allegro Design Entry Explores design relationships
solve virtually any design challenge HDL and Cadence OrCAD Capture / with what if scenarios before
from high-frequency systems to CIS. The simulation technology can committing to hardware
low-power IC designs. The powerful also interface with MathWorks
Maximizes circuit performance
simulation engine integrates easily with MATLAB Simulink package in a
automatically using Optimizer
Cadence PCB schematic entry solutions, powerful co-simulation environment
improving time to market and (SLPS). Identifies and simulates functional
keeping operating costs in check. An (See Figure 1.) blocks of complex circuitry
interactive, easy-to-use graphical user using mathematical expressions,
interface p rovides complete control Benefits functions, and behavioral devices
over the design process. Availability
Improves simulation times, reliability, Determines which components are
of resources such asmodels from
and convergence on larger designs overstressed using Smoke analysis
many vendors, built-in mathematical
and by observing component yields
functions, and behavioral modeling Improves speed without loss of
using Monte Carlo analysis
techniques make for an efficient design accuracy via integrated analog and
process. Advanced analysis f eatures event-driven digital simulations Virtual prototyping leverages
(Sensitivity, Monte Carlo, Smoke, GUI-based code generation of
Explores circuit behavior using
parametric plotter, and an optimizer mixed-signal system models
basic DC, AC, noise, and transient
with multiple engines) are built on top written in C/C++ and SystemC,
analyses
of the simulator to improve design and compact models from Verilog
performance, cost-effetiveness, and Allows system-level interfaces to be A using Automatic Device Model
reliability. The Allegro PSpice Simulator tested with actual electrical designs Synthesizer can be easily used in the
now offers the new Device Model using SLPS PSpice environment
Interface feature for automating
Offers library selection of more than
the code generation for multilevel
33,000 analog and mixed-signal
abstraction models written in C/C++,
models
Allegro PSpice Simulator

Features
Device
Allegro PSpice
Cadence simulation technology for PCB BSIM1, BSIM3, Simulator
equations
Custom
Model Library semiconductor
design integrates seamlessly with the EKV models
models
Analog or
Cadence front-to-back PCB design flow, mixed-signal
Datasheet simulator with
making it possible to have a single, u
nified specifications probe graphical Measurements
Allegro PSpice Simulator
advanced analysis
post-processor
design environment for both s imulation - Smoke analysis
Allegro PSpice Parameters - Sensitivity analysis
and PCB design. Vendor models
Simulator - Optimizer
Model Editor - Monte Carlo analysis

Design entry and editing Symbols Netlist, stimuli,


Allegro Design Entry HDL from models, simulation settings,
bias info cross-probing
Select from a library of more than 33,000
symbols and models for simulation to PCB layout
Part Manager
design with Cadence PCB schematic Gerber/NC Drill,
Verified
GenCAM/GenCAD,
design entry technology. It provides Interface
DE-HDL netlists
pick and place reports
to part data
manyfeatures that allow you to easily
Part Browser Variant Editor Purchasing/ Fabrication,
capture and simulate mixed-signal Part table file
Verified inventory Parts assembly and test
BOMs
designs. Seamless integrations include Place part

one-button simulation and cross-probing, Variant reports for board assembly and BOMs

Released BOMs
and many other simulation utilities. MRP/ERP/PDM
system
Additionally, Allegro PSpice Simulator
includes a syntax-aware Spice circuit file
Figure 1: Allegro PSpice Simulator
text editor.

Stimulus creation and 64 strengths, load-dependent delays, for gain and phase margin and derivatives
and hazard/race checking. Allegro PSpice for small-signal characteristics.
Access built-in functions that can Simulator also features propagation (See Figure 2.) Annotate simulation
be described parametrically or draw modeling for digital gates and constraint result using floating labels on the circuit
piecewise linear (PWL) signals freehand checking (such as setup and hold timing). voltage, current, and power dissipation
with the mouse to create any shape at time 0 for a circuit at each node in the
stimulus. Create digital stimuli for signals, Analog analysis
schematic.
clocks, and buses; click-and-drag to Explore circuit behavior using DC,
introduce and move transitions. Models
AC,noise, transient, parameter
Circuit simulation sweeps,Monte Carlo, and DC sensitivity Included are a large variety of accurate
analyses. Allegro PSpice Simulator internal modelswhich typically include
Users can easily set up and run simula- includes interactive simulation controllers temperature effectsthat add flexibility
tions, and then cross-probe simulation and two simulation solvers. to simulations. Models are available with
results from Probe, an industry-standard R, L, C, and bipolar transistors plus:
waveform viewer. Support for multiple Graphical results and data display
simulation profiles enables users to recall Modeling apps create a model with
Probe Windows allows users to choose
and run different simulations on the same user-input parameters (such as from
from an expanded set of mathematical
schematic. Simulation bias results can be a datasheet) and place a schematic
functions to apply to simulation output
viewed directly on the schematic including component automatically associated
variables. Designers can create plot
node voltages, device power calculations, with the newly created model without
window t emplates and use them to easily
and pin and subcircuit current. Support having to leave the OrCAD Capture
make complex measurements by simply
for Checkpoint Restart allows designers canvas.
placing markers directly on the desired
to reduce simulation times when the pins, nets, and parts in the schematic, Built-in IGBTs
same circuit is simulated multiple times as well as be able to view a continuous
with minor changes. Assertions enable Seven MOSFET models, including
marching waveform as simulation
designers to detect failure or warning industry-standard BSIM3v3.2 and
progresses.
conditions as the simulation progresses. thenew EKV 2.6 model
The tools also enable users to measure
Mixed analog/digital simulation Five GaAsFET models, including
performance characteristics of a circuit
Parker-Skellern and TriQuint TOM-2,
Integrated analog and event-driven digital using built-in measurement functions
TOM-3 models
simulations improve speed without loss andcreation of custom measurements.
of accuracy. A single graphical waveform For data display, additional capabilities Nonlinear magnetic models complete
analyzer displays mixed analog and digital allow plotting of both real and complex with saturation and hysteresis
simulation results on the same time axis. functions of circuit voltage, current, and
Digital functions support five logic levels power consumption, including Bod plots

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Allegro PSpice Simulator

New behavioral capabilities include


mathematical functions like in(x), exp(x),
and sqrt(x).

Magnetic parts editing


The Magnetic Parts Editor helps designers
overcome issues involved in manually
designing transformers. Users can design
magnetic transformers and DC inductors,
and generate simulation models for trans-
formers and inductors that can then be
used in Allegro PSpice Simulator circuits.
The Magnetic Parts Editor also allows
designers to generate data required
for manufacturing the transformers or
inductors. The manufacturers report
Figure 2: Allegro PSpice Simulator provides a complete simulation environment including
thatis generated by the PSpice Magnetic
simulation waveform analysiswith cross-probing and bias results displayedon the schematic
Designer after the completion of the
Transmission line models that Model editing design process contains the complete data
incorporate delay, reflection, loss, required by avendor to develop the trans-
Its easy to extract a model of a supported
dispersion, and crosstalk former for commercial use. The modeling
device typesimply enter the required
design capabilities help you generate
Digital primitives, including bi-directional data from the devices datasheet. Once
accurate PSpice models, including winding
transfer gates with analog I/O models you have extracted, the PSpice Model
resistances and various parasitics.
Editor automatically creates a part of the
Battery models allow accurate
model, making it available for immediate Encryption
simulation of the discharge cycle and
use in the design.
operating conditions The encryption feature allows models to
Behavioral modeling be encrypted using 56-bit DES algorithm.
Comprehensive model set for various
electromechanical and mechanical Functional blocks are described using SLPS
devices like BLDC, flywheel, resolver, mathematical expressions and functions,
tacho, etc. which allow designers to leverage a full Cadence simulation technology and the
set of mathematical operators, nonlinear MathWorks MATLAB Simulink package
Built-in library component for integrate two industry-leading simulation
functions, and filters. Circuit behavior
commonly used mathematical functions tools into a powerful co-simulation
canbe defined in the time or frequency
Models for Tiny Switch-III family devices domain, by formula (including Laplace environment (SLPS). However, in order
and new Optocoupler devices transforms), or by look-up tables. Error to run PSpice SLPS one must have a
and warning messages can be specified PSpice SLPS license along with a PSpice
The Device Model Interface capability or Allegro PSpice Simulator license.
indifferent conditions. Users can easily
in PSpice offers enables simulation of Simulink is a platform for multi-domain
select parameters, which have been
system designs using different kinds of simulation and model-based design of
passed to subcircuits in a hierarchy, and
abstractions. With the GUI, users can dynamic systems. The SLPS integration
insert them into transfer functions.
define C/ C++, System C, and Verilog A allows designers to perform system-level
components and simulate them in the
simulator.

Model library
P(u) 1 Scope1
SLPS -K- -K-
Users can select from more than 33,000 0(P) = 2 s
Polynomial Relay heater blower Gain1 Integrator
analog and mixed-signal models of
devices made in North America, Japan, -K-

and Europe. Also included are more than 50


1/Req

4,500 parameterized models for BJTs, average 5/9


JFETs, MOSFETs, IGBTs, SCRs, magnetic outdoor temperature
Add1 Gain2
cores and toroids, power diodes and 32
daily temperature
bridges, operational amplifiers, optocou- variation constant
plers, regulators, PWM controllers,
multipliers, timers, and sample-and-holds. Figure 3: SLPS integration allows designers to interface the Allegro PSpice Simulator with Simulink
and then observe the waveforms after Simulink-Allegro PSpice Simulator co-simulation

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Allegro PSpice Simulator

Optimizer
The optimizer analyzes analog circuits
and systems, fine-tuning designs faster
than trial-and-error bench testing. It
helps find the best component values to
meet performance goals and constraints.
Designers can use the optimizer to
improve design performance, update
designs to meet new specifications,
optimize behavioral models for top-down
design and model generation, and tune a
circuit to match known results in the form
of measurements or curves. The optimizer
includes three engines: modified least
squares quadratic (LSQ), random, and
discrete.

Smoke
The Smoke option warns of stressed
components due to power dissipation,
increases in junction temperature,
Figure 4: Smoke compares simulated values with manufacturers limits to highlight devices secondary breakdowns, or violations
operating outside safe operating rages. of voltage/current limits. Over time,
these components can cause circuit
simulations that include realistic electrical fine-tune simulations by further modifying
failure. Designers can use Smoke to
models of actual components. Design and simulator options. This option is recom-
compare circuit simulation results to a
integration problems can be discovered mended for power electronic designs.
components safe operating limits. If
much earlier in the design process,
Advanced analysis capabilities limits are exceeded, Smoke identifies the
reducing the n umber of prototypes
problem parameters. It can also be used
needed to execute the design. SLPS Using advanced analysis capabilities,
for creating, modifying, and configuring
integration also lets designers of electro- designers can automatically maximize
derate files for use with Smoke analysis.
mechanical systemssuch as control theperformance of circuits. Four important
(See Figure 4.)
blocks, sensors, and power converters capabilitiessensitivity analysis, optimi-
perform integrated system and circuit zation, Smoke (stress analysis), andMonte Monte Carlo
simulation. Carlo (yield analysis)enable engineers
(See Figure 3.) Monte Carlo predicts the behavior
tocreate virtual prototypes of designs and
of a circuit statistically when part
maximize circuit performance automatically.
Checkpoint restart values are varied within their tolerance
Measurements across m ultiple simulation
range. MonteCarlo also calculates
The checkpoint restart feature allows profiles can be processed together.
yield, which can be used for mass
the designer to store simulation states
Sensitivity manufacturing predictions. Use Monte
at various time-points and then restart
Carlo for c alculating yield based on your
simulations from any of the simulation The sensitivity option identifies which
specifications calculating statistical data,
states, which saves time. The designer component parameters are critical to
displaying results in a probability density
can modify simulation settings and design thegoals of a circuits performance
histogram, and displaying results in a
parameters before starting a simulation by examining how each component
cumulative distribution graph.
from a pre-recorded time-state. affects circuit behavior by itself and in
comparison to the other components.
Auto-convergence option
It allows designers to identify sensitive
This option makes the simulator components and export them to the
automatically change tolerances limits optimizer to fine-tune circuit behavior.
of c onvergence to make the design
converge. Designers can use this option
toachieve convergence and then

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Allegro PSpice Simulator

Parametric plotter Cadence Services and Support


Once a circuit is created and simulated, Cadence application engineers can
the parametric plotter is used for answer your technical questions by
s weeping multiple parameters. Any telephone, email, or Internetthey can
number of design and model param- also provide technical assistance and
eters (in any combination) can be swept custom training
and results viewed in tabular or plot
Cadence certified instructors teach
form. Designers can use the parametric
more than 70 courses and bring
plotter for allowing device/model param-
their real-world experience into the
eters to be swept, displaying sweep
classroom
results in spreadsheet format, allotting
measurement results in probe UI, and More than 25 Internet Learning
evaluating post-analysis measurement. Series (iLS) online courses allow you
the flexibility of training at your own
System Requirements computer via the Internet
Intel Core 2 Duo 2.66GHz or AMD Cadence Online Support gives you 24x7
Athlon 64 X2 5200+ (Note: Faster online access to a knowledgebase of
processors are preferred) the latest solutions, technical documen-
tation, software downloads, and more
8GB RAM
For more information, please visit
500GB free disk space
www.cadence.com/support-and-
1280 x 1024 display resolution with training
true color (at least 32-bit color)

Dedicated graphics card

Single or dual monitors (for physical


design)

Broadband internet connection for


some services

Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of todays electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify todays mobile, cloud, and connectivity applications. www.cadence.com

2016 All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks
are trademarks or registered trademarks of Cadence Design Systems, Inc. SystemC is a trademark of Accellera Systems Initiative Inc. All other
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