Department of Electrical and Computer Engineering

ELEC 499B

LCC Resonant Inverter
For A High Frequency Distributed Power System

July 28, 2006 Project Supervisor: Dr A.K.S. Bhat Matt Weber Tyler Nitsch Sean Clutterbuck Geoff Lindsay (02-32601) (01-31768) (00-29577) (02-35351)

Abstract
An LCC Resonant Inverter is proposed for applications in high frequency distributed AC power systems. The advantages of the LCC topology are low total harmonic distortion (THD) high efficiency and the ability to handle varying loads. Design of the LCC resonant tank was based around previously developed theory. This report documents one LCC configuration with a variety of load configurations. A microprocessor approach is taken over previous fixed frequency phase shift circuitry and FPGA chips to provide a lower cost solution to pulse width modulation control. This also enables later development of a more robust closed loop design. Efficiencies greater than 90% were obtained down to resistive loads of 50%. Efficiencies greater than 75% were obtained at significantly reduced loads (11%). Operation above resonance was utilized to increase the efficiency and maintain zero voltage switching (ZVS) for varied loads. Total harmonic distortion (THD) of less than 10% was achieved for all resistive loads.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay

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Table of Contents
Introduction ................................................................................................1 Problem .............................................................................................................1 Project Specifications ........................................................................................2 2. Applications................................................................................................3 3. Construction ...............................................................................................4 Components ......................................................................................................4 H-Bridge..........................................................................................................4 Driver Board....................................................................................................4 Microcontroller Gate Generator.......................................................................4 Fixed Frequency Phase Shift Board ...............................................................4 LCC Resonant Tank .......................................................................................4 LCC Configuration.............................................................................................5 Driver Board ......................................................................................................6 Bridge Board .....................................................................................................7 Fixed Frequency Phase Shift Board..................................................................9 ATmega8 Microcontroller ................................................................................10 4. Analysis....................................................................................................11 Design Calculations, Theoretical Output Values and Harmonic Analysis........11 Snubber Calculations ......................................................................................14 5. Simulation Results ...................................................................................15 Full Load Resistive Load Simulation Results ..................................................16 11% Load Resistive Load Simulation Results .................................................17 Full Load Inductive Load Simulation Results...................................................18 Full Load Capacitive Load Simulation Results ................................................19 Summary of Simulation Results ......................................................................20 6. Experimental Results ...............................................................................21 Summary of Experimental Results and Efficiency ...........................................27 Summary of Load Values ................................................................................27 7. Harmonic Analysis ...................................................................................28 Current Total Harmonic Distortion for Varied Resistive Loading .....................32 8. Discussion................................................................................................33 Microcontroller Selection and Programming Challenges.................................33 Choosing of the LCC .......................................................................................34 Concluding Comments ....................................................................................35 9. Recommendations ...................................................................................36 Closed Loop Design ........................................................................................36 LCC Resonant Tank Optimization ...................................................................36 Packaging .......................................................................................................37 10. References...............................................................................................38 11. Appendices ..............................................................................................39 ATmega8 Microcontroller Code.......................................................................39 Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page ii 1.

Table of Figures
Figure 1 - Simulation Circuit................................................................................15 Figure 2 - VAB and ILs at Full Load Resistive Load ..............................................16 Figure 3 Vout and Iout at Full Load Resistive Load................................................16 Figure 4 - VAB and ILs at 11% Load Resistive Load .............................................17 Figure 5 - Vout and Iout at 11% Load Resistive Load ............................................17 Figure 6 - VAB and ILs at Full Load Lagging Power Factor ...................................18 Figure 7 - Vout and Iout at Full Load Lagging Power Factor ..................................18 Figure 8 - VAB and ILs at Full Load Leading Power Factor ...................................19 Figure 9 - Vout and Iout at Full Load Leading Power Factor ..................................19 Figure 10 – VAB and ILs at Full Load Resistive Load............................................22 Figure 11 - Vout and Iout at Full Load Resistive Load ...........................................22 Figure 12 - VAB and ILs at 50% Load Resistive Load ...........................................23 Figure 13 - Vout and Iout at 50% Load Resistive Load ..........................................23 Figure 14 - VAB and ILs at 11% Load Resistive Load ...........................................24 Figure 15 - Vout and Iout at 11% Load Resistive Load ..........................................24 Figure 16 – VAB and ILs at Full Load Lagging Power Factor ................................25 Figure 17 – Vout and Iout at Full Load Lagging Power Factor ...............................25 Figure 18 – VAB and ILs at Full Load Leading Power Factor ................................26 Figure 19 – Vout and Iout at Full Load Leading Power Factor ...............................26 Figure 20- Full Load Current Spectrum...............................................................29 Figure 21 - Full Load Voltage Spectrum .............................................................29 Figure 22 - 50% Load Current Spectrum ............................................................30 Figure 23 - 50% Load Voltage Spectrum ............................................................30 Figure 24 - 11% Load Current Spectrum ............................................................31 Figure 25 - 11% Load Voltage Spectrum ............................................................31 Table 1 - Final LCC Resonant Tank Components ................................................5 Table 2 - Summary of RMS Current and Voltage from Simulation Results.........20 Table 3 - Summary of Experimental Results and Efficiency Calculations ...........27 Table 4 - Summary of Load Values.....................................................................27 Table 5 – Current Total Harmonic Distortion for Varied Resistive Loading .........32

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay

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Introduction Problem The increased use of distributed power systems (DPS) in recent years has driven the need for high efficiency power conversion techniques. Matt Weber. Efforts to improve the efficiency under varying loads have shown good promise. Tyler Nitsch. We intend to focus primarily on designing a LCC topology to handle varied loads while maintaining constant output voltage with low total harmonic distortion (THD). we intend to replace the FPGA phase shifter circuitry with a microcontroller. 3] has shown that LCC topology resonant inverters have a number of desirable features as compared to series or parallel topologies. high efficiency conversion systems. The microcontroller approach is ideal considering the rising cost of high frequency FPGAs. Recent research by several authors [1. making resonant inverters ideal. Sean Clutterbuck. Power systems for avionic applications require high frequency. Designing an LCC-type resonant inverter that can operate under resistive and reactive loads is still a challenging process.1. While LCC topologies have been designed and tested for various applications. Geoff Lindsay Page 1 . Resonant inverters have come to be recognized as the next generation of power conversion circuits due to low component costs. small component sizes and high efficiency. 2.

0. Sean Clutterbuck. Zero voltage switching (ZVS) at full load ensures very low losses in the bridge circuit while at reduced loads the mode of operation in the MOSFET switches in one arm of the bridge is zero current switching (ZCS). By adjusting the resonant frequency of the LCC tank we intend to maximize the range of ZVS and therefore increase the total efficiency of the bridge. Having decided on an LCC resonant inverter topology our primary efforts will be towards optimizing the LCC parameters for the highest efficiency given varying loads. Tyler Nitsch.Project Specifications A High-Frequency DC/AC Power Inverter is proposed which is capable of supplying power to an AC bus with varying loads. Preliminary Specifications for our circuit are: Input Voltage Output Power Output Voltage Output Current Output Frequency Minimum Load Power Factor Minimum Load Efficiency Full Load Efficiency 40-60V DC ~250 VA ~ 28 VRMS ~ 10 A 20 kHz unity.9 leading. 0. Considerable efforts will also be devoted to designing a microcontroller circuit to mimic existing fixed frequency phase shift circuits. Geoff Lindsay Page 2 . Design parameters have been taken from previous work [1. 2.9 lagging In excess of 80% In excess of 90% Matt Weber. 3] and LCC configuration is based on these parameters.

the LCC resonant inverter components are very small. A high frequency distributed bus implies a raillike system where multiple loads can be connected in parallel to the same inverter output. Geoff Lindsay Page 3 . For example. Tyler Nitsch. Matt Weber. The LCC resonant inverter topology has a number of advantages over other simpler topologies such as the parallel and series resonant topologies. Aircraft also utilize an LCC topology to provide efficient and highly reliable power throughout the aircraft. Smaller components yield a lighter inverter which is desirable for aerospace applications.2. the international space station combines multiple LCC resonant inverters to convert the DC power produced by solar panels to a high frequency AC bus which supplies power throughout the space station. At high frequencies. Obviously aircraft require highly reliable power sources to supply power to electronics and control circuitry. Applications The target application for LCC resonant inverter topology detailed in this report is a high frequency distributed bus. Sean Clutterbuck. Some of the advantages of the LCC topology are: • • • • • • • Low total harmonic distortion (THD) Low electromagnetic interference (EMI) High efficiency Load independence Power factor stability Small component size Low component cost LCC resonant inverter topologies are currently being used in the aerospace and aeronautics industries.

1µF High Frequency High Voltage Capacitors Matt Weber.Hex Inverting Buffer Microcontroller Gate Generator • ATmega8 Microcontroller • 16MHz Crystal Oscillator Fixed Frequency Phase Shift Board • Fixed Frequency Phase Shift Board (Prebuilt) • 1 x UC3875N Phase Shift Resonant Controller LCC Resonant Tank • 3 x Syntax Generic Protoboards • 2 x High Frequency Magnetic Cores • 9 x 0.9nF. Geoff Lindsay Page 4 . 100Ω (1/4 Watt) Snubber Circuits • 4 x MOSFET Bolt Mounted Heat Sinks Driver Board • Driver Board PCB • 2 x IR2110 High Power.3. Construction Components H-Bridge • 4 x IRPF3710 HEXFET Power MOSFETs • Power H-Bridge PCB • 1 x 2µF High Frequency High Voltage Bias Capacitor • 1 x 10µF High Voltage Bias Capacitor • 4 x 1. High Frequency High and Low Side Drivers • 2 x A 2630 Dual Channel Optocouplers • 1 x CD4081BE CMOS Quad 2-Input AND Gate • 1 x HCF4049UBE CMOS-Input Level Translator . Tyler Nitsch. Sean Clutterbuck.

Geoff Lindsay Page 5 . The LCC components were calculated as is shown in the analysis section of this report.357 but in practice a slightly higher ratio was achieved. By reviewing reference papers values of Cn and Qs were chosen as 2 and 4 respectively. Sean Clutterbuck. Bhat. A resonant frequency was chosen as 19kHz initially and simulations confirmed that this would ensure zero voltage switching at full load. Simulations verified this design and a number of other scenarios were simulated to assure that this design performed better.LCC Configuration An LCC topology was designed based on recommendations and references from Dr.Final LCC Resonant Tank Components Ls 174. a step-down transformer was hand-wound to bring the RMS output voltage down to 28V. Final LCC component values are shown in Table 1 below.K. Matt Weber. Tyler Nitsch. Design parameters Qs and Cn were very important to the design of the LCC resonant tank.5µH Cs 400nF Cp (on secondary) 350nF Transformer Winding Ratio 1. Once Qs. Table 1 . Other important parameters included the ratio of the switching frequency (fsw) to the resonant frequency of the tank (fr) and the LCC tank gain. Cn and y were chosen. the LCC resonant tank gain was computed and the value of Ls and the load resistance were finalized.S. The benefits of the LCC topology are mentioned previously. Another benefit of the step-down transformer is that it serves to electrically isolate the load from the bridge circuit. As such. The frequency ratio (y) was chosen such that the circuit would operate above resonance and thus all 4 switches would operate in zero voltage switching. A. The transformer ratio was to be 1.357 The LCC resonant tank gain was not sufficient to bring the 48VDC rail voltage down to the specified 28VRMS output.

This serves to protect the MOSFET’s. a driver board was necessary as an intermediate circuit between the gating circuitry and the bridge board. using the high end soldering equipment. Deepak Gautam helped our team test its function using a proven MOSFET H-bridge.S. The integrated circuits as well as large high frequency capacitors were obtained from Dr. along with an empty PCB to construct the driver board on. Construction of the driver board was performed in ELWB320. A. Bhat. providing a valuable experience in electronics assembly. Testing was immediately successful. A. allowing us to proceed to the next phase of the project. Bhat. All team members participated in this phase. As such. The basic driver board components were obtained from the engineering lab technicians in ELWB320. Along with these attributes the driver board was designed to provide gating signals to MOSFET’s within an H-bridge and as such handles other possibly inherent behaviors of such a circuit.S. Additionally the driver board provides current to charge the MOSFET internal capacitance before gating. Geoff Lindsay Page 6 . The main purpose of the driver board is to amplify the gating signals to the appropriate voltage levels with sufficient current to turn on the MOSFET switches.K. The driver board also acts to isolate the gating circuitry from the bridge board. Tyler Nitsch. Once the driver board was constructed. Matt Weber. Fortunately the board design was provided by Dr. Sean Clutterbuck.Driver Board The output power of both the fixed frequency phase shift board and the ATmega8 microcontroller was too low to properly gate the MOSFET switches.K.

The final snubber circuit calculations are detailed in the analysis section of this report. Dr. Bias Capacitor A 2uF high frequency capacitor was connected across the input DC terminals to further clean up the DC input voltage. During the first testing phase a large high frequency ripple was observed on the output of H-bridge (VAB).K. Snubber values were recalculated for worst case scenarios and implemented. When a MOSFET switch is operating with zero current switching (ZCS) lossy snubbers are necessary to dissipate the high current through the snubber circuit. The circuit schematic for the generic board was also provided and gave us a starting point.S. the snubber circuitry Matt Weber. a special PCB was required to ensure safe operation. The H-bridge schematic was analyzed to determine which components would have to be soldered onto the PCB and where. but this was not the case. however the observed variation was clearly too great. Some variation in VAB is expected due to the varying loss in the MOSFETs as the current varies sinusoidally. A. This did not solve the problem with the DC voltage ripple. Lossless snubbers consist of only a capacitor. Bhat was consulted for all changes deemed necessary. Lossy snubbers consist of a capacitor and a resistor in series. Sean Clutterbuck. This theory was put to rest when a proven bridge board was connected and a similar ripple was observed. It was thought that this would be sufficient to smooth any ripple seen on the DC voltage. Snubber Circuits Snubber circuits are required across each MOSFET switch to protect them during turn-on and turn-off from voltage and current transients.Bridge Board Due to the large currents in the H-bridge circuit. Initially the variation was thought to be a result of an oscillation occurring between the bridge capacitances and the series inductor within the LCC. The main considerations in calculating the snubber components were the MOSFET fall time and the dead gap time between consecutive gating pulses. Due to the complexity of the circuit given. Tyler Nitsch. When a MOSFET switch is operating with zero voltage switching (ZVS) lossless snubbers are adequate. Bhat.K. As mentioned above. During testing of the bridge circuit the snubber circuits were targeted as a possible cause of the input DC voltage ripple. The reason that the snubber circuit was required to complete its discharge period before gating the next MOSFET is to prevent a momentary short circuit across the H-bridge.S. Geoff Lindsay Page 7 . A. Fortunately a generic H-Bridge PCB was provided by Dr.

Finally a 10uF capacitor was added in parallel across the DC voltage and the ripple was significantly reduced. Tyler Nitsch. the operation of the MOSFETs within the right arm of the Hbridge changes to ZCS and significant heating of the MOSFETs is noticable. however when the load is reduced. Matt Weber. Geoff Lindsay Page 8 .was analyzed to ensure it was not the cause of the ripple observed. we were forced to mount two of the MOSFET switches on the top side of the PCB in order to avoid contact between the heat sinks themselves. Due to the geometry of the H-bridge and the heat sinks available to us. Under normal ZVS operation. Heat Sinks Heat sinks were mounted on the MOSFET switches to assist in heat dissipation. Sean Clutterbuck. the switches do not heat up.

Parallel resistors added to the reference voltage resistor to bring the reference voltage into the proper range Ramp potentiometer added in order to properly vary the dV/dt rise of the ramp function. Two approaches were available: (1) Fixed Frequency Phase Shifting Board. Sean Clutterbuck. Modifications to the board were required in order to use it at 20kHz.Fixed Frequency Phase Shift Board Once the driver board and the H-bridge were constructed. Tyler Nitsch. The ATmega8 controller was tested to ensure that operation exactly duplicated the fixed frequency phase shift board however it required reprogramming for different pulse widths. Geoff Lindsay Page 9 . A fixed frequency phase shift board was available but it was designed to operate at a switching frequency of 100kHz. The fixed frequency phase shift board was used for all experimental results and the demonstration because it was easy to adjust the pulse width modulation for varying loads. a means of generating gating pulses to the MOSFETs with appropriate dead gap time and phase shifting ability for pulse width modulation was required. This allowed proper phase shifting at 20kHz. (2) ATmega8 microcontroller. Matt Weber. The following changes were made to the fixed frequency phase shift board: • • • Series resistor added to the frequency control potentiometer to change the range of operating frequencies.

It was decided that the internal clock was both too slow and too unreliable to adequately generate the 20kHz gating pulses to the MOSFETs. Matt Weber. A 40kHz control signal was generated. The actual assembly language code is attached in the first appendix of this report.ATmega8 Microcontroller The ATmega8 microcontroller was used to perform the same function as the fixed frequency phase shift board. The code was generated by using the microcontroller timer interrupts to toggle output pins between high state (+5V) and low state (0V). The current implementation of the microcontroller requires reprogramming of the controller whenever the duty cycle requires tuning. This introduces a limitation in the gating frequency that can be achieved with this implementation. Tyler Nitsch. an external clock with frequency 16MHz was connected to the microcontroller. The ATmega8 microcontroller was chosen because it is a smaller and cheaper solution to PWM gating pulse generation. Sean Clutterbuck. Assembly language was chosen as the platform for coding the microcontroller and a custom programming jig was available from the engineering lab technicians. As a solution to this. Geoff Lindsay Page 10 . The interrupt flags were triggered when timer counter compare register (TCCR1B) matches either of two high values. This external clock provided highly reliable timing to the microcontroller. A sufficient dead gap is ensured by a delay routine that has been programmed to generate an 800ns dead gap. This can be adjusted down to 3-5 clock cycles. The maximum time delay between the rising edge and the falling edge corresponds to the full load 50% duty cycle pulse train to the MOSFETs. The falling edge of the control signal was used as a trigger for the phase shifted gating pulses while the stable rising edge was used to generate the non-shifted gating pulses. A difficulty realized in this approach was the clock frequency of the microcontroller. This is not ideal for testing but can be overcome by connecting an adjustable input voltage signal and scaling the value over the range of duty cycle tuning.

754 × 10 R_load := ωr⋅ Ls k ⋅ Qs 2 −4 H R_load = 2. Sean Clutterbuck.842Ω rating := Vout 2 2 k R_load rating = 271. Analysis Design Calculations.729V Vout := Vin⋅ V_gain Cs := 400⋅ 10 2 −9 farad Cs = 4 × 10 Cp := k ⋅ 200⋅ 10 1 ωr ⋅ Cs 2 −9 −7 F −7 farad Cp = 3.053 D := 1 38 k := 28 V ≡ 48volt ωr := 2πfr k is the transformer winding ratio Design Calculations Vin := 2 2V π sin ⎜ ⎛ D⋅ π ⎞ ⎟ ⎝ 2 ⎠ Vin = 43.902W ωsw := 2⋅ π⋅ fsw 1 Tsw := fsw Matt Weber.873 Vout = 37. Tyler Nitsch.4.215V Cn := 2 Qs := 4 V_gain := 2⋅ 2 π ⋅ y y⋅ ⎛ 1 + ⎜ 1 Cn ⎝ −y ⋅ 2 1 ⎞ + i⋅ Qs ⋅ y 2 − 1 ⎟ Cn ⎠ ( ) ⋅ sin ⎜ ⎛ D⋅ π ⎞ ⎟ ⎝ 2 ⎠ V_gain = 0.684 × 10 F Ls := Ls = 1. Geoff Lindsay Page 11 . Theoretical Output Values and Harmonic Analysis Circuit Parameters fsw := 20kHz fsw y := fr fr := 19kHz y = 1.

643V Vabrms( 7) = 6. Tyler Nitsch. t) := ⎜ ⎜ ⎟ ⎜ ⎟ ⎟ 2⎠ ⎝ n⋅ π ⎝ 2 ⎠ ⎝ ⎠ 1 Tsw ⎛ ⎞ ⎜ ⎟ ⌠ 2 ⎜ 2 ⎮ 2 ⎟ Vabrms( n ) := Vab( n .215V Vabrms( 3) = 14.729Ω RL_load( 1) = 2. t) dt ⎜ Tsw ⋅ ⎮ ⎟ ⌡ 0 ⎝ ⎠ 2 Vabrms( 1) = 43.87Ω Xl( n ) := ωsw ⋅ n ⋅ Ls Zparallel( n ) := −i⋅ Xcp( n ) ⋅ RL_load( n ) ( −i⋅ Xcp( n ) ) + ( RL_load( n ) ) Zs ( n ) := i⋅ Xl( n ) − i Xcs ( n ) Zeq ( n ) := Zs ( n ) + Zparallel( n ) φ( n ) := atan ⎛ ⎜ Im( Zeq ( n ) ) ⎝ Re( Zeq ( n ) ) ⎠ ⎞ ⎟ VAB Calculations ⎛ 4⋅ V ⋅ sin ⎛ n⋅ π ⎞ ⋅ sin ⎛ D⋅ n ⋅ π ⎞ ⋅ sin ( n⋅ ωsw ⋅ t) ⎞ Vab( n .802V Vabrms( 11) = 3. Sean Clutterbuck. Geoff Lindsay Page 12 .324V Matt Weber.Equivalent Impedance Computations X_load ( n ) := n ⋅ ωsw ⋅ L_load i⋅ X_load ( n ) RL_load( n ) := R_load + 2 k Xcp( n ) := 1 ωsw ⋅ n ⋅ Xcs ( n ) := 1 ωsw ⋅ n ⋅ Cs Cp k 2 Inherent Inductance Primary Side Load X_load ( 1) = 0.929V Vabrms( 13) = 3.405V Vabrms( 5) = 8.174V Vabrms( 9) = 4.

Geoff Lindsay Page 13 .781V = 0. Tyler Nitsch. t) := Vab( n .012A −3 Iorms( 13) = 9.248V = 0.166V = 0. t) dt ⎜ Tsw ⋅ ⎮ ⎟ ⌡ 0 ⎝ ⎠ 2 Vcp( n .177A = 0.079V = 0.581V = 0. Sean Clutterbuck. t) ⋅ Zparallel( n ) k 1 Tsw ⎛ ⎞ ⎜ ⎟ ⌠ 2 ⎜ 2 ⎮ 2 ⎟ Vcprms( n ) := Vcp( n .051V Output Current Through the Load Iorms( n ) := Vcprms( n ) Zparallel( n ) Iorms( 1) Iorms( 3) Iorms( 5) Iorms( 7) Iorms( 9) Iorms( 11) 13 = 8.219% Matt Weber.03A = 0. t) Zeq ( n ) Io( n .571A Vlrms := n =1 ∑ 13 Vcprms( n ) Vlrms = 24.06A = 0.571A = 0.Output Voltage Across the Parallel Capacitor Io( n .781V Output Current Total Harmonic Distortion Iorms( 3) 2 THD := + Iorms( 5) 2 + Iorms( 7) 2 + Iorms( 9) 2 + Iorms( 11) 2 + Iorms( 13) 2 Iorms( 1) THD = 2.917 × 10 Ilrms := A n =1 ∑ Iorms( n ) Ilrms = 8. t) := Vcprms( 1) Vcprms( 3) Vcprms( 5) Vcprms( 7) Vcprms( 9) Vcprms( 11) Vcprms( 13) = 24.124V = 0.018A = 0.

Geoff Lindsay Page 14 .Snubber Calculations Iturnoff ≡ 10amp tfall ≡ 48ns Vdc ≡ 48volt tdeadgap ≡ 800ns Csnubber_max := Iturnoff ⋅ tfall Vdc Csnubber_max = 1 × 10 Csnubber ≡ 1. Tyler Nitsch. Sean Clutterbuck.263Ω Matt Weber.9nF −8 F Rsnubber := tdeadgap 4⋅ Csnubber Rsnubber = 105.

Figure 1 . Tyler Nitsch.Simulation Circuit Matt Weber. Simulation Results The evaluation version of PSIM was used to model the LCC topology for varied loads and LCC configurations. Geoff Lindsay Page 15 . The circuit in Figure 1 is used to model for the resistive load in the lab. The resistors had an intrinsic inductance which has been added in as Lload. The test circuit is shown in Figure 1 below.5. All components are assumed to be ideal for the simulation and the measured leakage inductance of the transformer is incorporated in the series inductor (Ls). Sean Clutterbuck.

Simulations were conducted for a number of different load configurations.VAB and ILs at Full Load Resistive Load Figure 3 Vout and Iout at Full Load Resistive Load Matt Weber. Sean Clutterbuck. Below are some of the simulation results that were compared to experimental results. Tyler Nitsch. Geoff Lindsay Page 16 . Full Load Resistive Load Simulation Results Figure 2 .

Vout and Iout at 11% Load Resistive Load Matt Weber. Tyler Nitsch. Sean Clutterbuck.11% Load Resistive Load Simulation Results Figure 4 . Geoff Lindsay Page 17 .VAB and ILs at 11% Load Resistive Load Figure 5 .

Vout and Iout at Full Load Lagging Power Factor Matt Weber. Tyler Nitsch. Geoff Lindsay Page 18 .Full Load Inductive Load Simulation Results Figure 6 . Sean Clutterbuck.VAB and ILs at Full Load Lagging Power Factor Figure 7 .

VAB and ILs at Full Load Leading Power Factor Figure 9 . Sean Clutterbuck.Vout and Iout at Full Load Leading Power Factor Matt Weber.Full Load Capacitive Load Simulation Results Figure 8 . Tyler Nitsch. Geoff Lindsay Page 19 .

44276 20.Summary of RMS Current and Voltage from Simulation Results ILS (ARMS) Full Load Resistive 11% Load Resistive Full Load Inductive Full Load Capacitive 12.5684 Vout (VRMS) 31.0804 2. Tyler Nitsch.0695 7. Geoff Lindsay Page 20 .Summary of Simulation Results Table 2 .22031 9.002 32.65811 13.14905 1.1222 Iout (ARMS) 9.7639 52.2439 Matt Weber.6106 30. Sean Clutterbuck.

the average DC input current and the DC rail voltage. Digital multi-meters were also used to measure the RMS output voltage. Geoff Lindsay Page 21 . Experimental Results In the following pages oscilloscope plots for a variety of actual loads are presented. digital multi-meters were used to measure the RMS current through both the load and the series inductor.6. The scaling factor on the high frequency current probe that was used did not give consistent results and as such. Matt Weber. Tyler Nitsch. Inductance and capacitance was measured and verified using the 1kHz RLC probe in ELWB303. Sean Clutterbuck.

Figure 10 – VAB and ILs at Full Load Resistive Load Figure 11 . Sean Clutterbuck. Tyler Nitsch. Geoff Lindsay Page 22 .Vout and Iout at Full Load Resistive Load Matt Weber.

Vout and Iout at 50% Load Resistive Load Matt Weber.VAB and ILs at 50% Load Resistive Load Figure 13 . Geoff Lindsay Page 23 . Sean Clutterbuck.Figure 12 . Tyler Nitsch.

Vout and Iout at 11% Load Resistive Load Matt Weber. Sean Clutterbuck.VAB and ILs at 11% Load Resistive Load Figure 15 .Figure 14 . Tyler Nitsch. Geoff Lindsay Page 24 .

Sean Clutterbuck.Figure 16 – VAB and ILs at Full Load Lagging Power Factor Figure 17 – Vout and Iout at Full Load Lagging Power Factor Matt Weber. Geoff Lindsay Page 25 . Tyler Nitsch.

Tyler Nitsch.Figure 18 – VAB and ILs at Full Load Leading Power Factor Figure 19 – Vout and Iout at Full Load Leading Power Factor Matt Weber. Sean Clutterbuck. Geoff Lindsay Page 26 .

Summary of Load Values Resistance (Ω) Full Load 50% Load 11% Load Inductive Load Capacitive Load 3.30 3.20 9.10 0.80 8.50 76.30 31.78 24.40 5.30 VDC (V) 48.90 41.30 Inductance (µH) 5.10 48.Summary of Experimental Results and Efficiency Table 3 .30 6.81 24. Geoff Lindsay Page 27 .59 86.09% 7.40 18.20 Iout (ARMS) Vout (VRMS) Efficiency 7.Summary of Experimental Results and Efficiency Calculations IDC (Amps) Full Load Resistive 50% Load Resistive 11% Load Resistive Full Load Inductive Full Load Capacitive 4. Sean Clutterbuck.50 30.10 48.60 24.05 19.51 3.56 93.21 88. Table 4 .68% Summary of Load Values The resistance was measured using an RMS Fluke digital multi-meter (DMM).00 48.17% 12.00 3.80 Capacitance (µF) 3.36 2.57 93.64% 3.61% 0.00 Matt Weber. Tyler Nitsch.00 48.

Sean Clutterbuck. Nor was true resistive loading possible due to the inherent inductance of the LabVolt resistance boxes.7. oscilloscope plots of the Fourier transforms of the output current and voltage. Geoff Lindsay Page 28 . Matt Weber. The input current harmonics were analyzed to try and obtain an expression for the total harmonic distortion. Harmonic analysis was only performed on the resistive load as true capacitive loading was not possible. Tyler Nitsch. Harmonic Analysis In the following pages. The power levels were measured relative to the fundamental at 20kHz.

Geoff Lindsay Page 29 .Full Load Voltage Spectrum Matt Weber. Sean Clutterbuck.Figure 20. Tyler Nitsch.Full Load Current Spectrum Figure 21 .

Tyler Nitsch.50% Load Current Spectrum Figure 23 . Sean Clutterbuck. Geoff Lindsay Page 30 .Figure 22 .50% Load Voltage Spectrum Matt Weber.

Geoff Lindsay Page 31 .11% Load Current Spectrum Figure 25 . Sean Clutterbuck.Figure 24 .11% Load Voltage Spectrum Matt Weber. Tyler Nitsch.

Current Total Harmonic Distortion for Varied Resistive Loading Table 5 – Current Total Harmonic Distortion for Varied Resistive Loading Fundamental Full Load Resistive 50% Load Resistive 11% Load Resistive 0 0 0 3rd Harmonic -31.36 -60 -60 9th Harmonic -39.34% 8. Sean Clutterbuck. Tyler Nitsch.56 -21. Matt Weber.25 7th Harmonic -34.2 -60 5th Harmonic -23. **All dB levels were measured relative to the fundamental output current.68 -60 THD 7.88 -35. Geoff Lindsay Page 32 .12 -26.36 -34.66% *All values are relative dB.75% 5.

test algorithms were created to determine if the microcontroller outputs would be fast enough. This project design was chosen by Dr. The manual for the microcontroller was exhaustively explored for an answer to this problem to no avail. A variety of approaches were explored and finally a solution was reached using a control signal at double the output gating frequency.S. The second challenge. Sean Clutterbuck. it was thought that only the PWM output pins would be fast enough but this proved to be untrue and standard output pins were used to output the gating signals. This method is similar to a previously explored method [4]. A. power electronic equipment and test procedures as well as the many obstacles and uncertainties involved in construction of such a circuit.S. Our challenge was two-fold: (1) design a microcontroller solution to generate gating signals to the MOSFET switches and (2) choose and optimize an LCC configuration from the design parameters. stability of the design and previously explored design curves. There were a number of obstacles to overcome during the design of both challenges. Due to time constraints a method to vary the pulse width modulation externally (ie. was choosing an algorithm for the gating pulse generation. Eventually. Bhat to help us to gain understanding and familiarity with inverter topologies. an adjustable reference voltage via a potentiometer) was not completed. The LCC topology was given as a starting point for reasons involving simplicity. Due to the high frequency of the output signals it was not immediately clear than standard output pins on the microcontroller IC would be fast enough. Microcontroller Selection and Programming Challenges Choosing the correct microcontroller for the job was the first obstacle to overcome. By varying the elapsed time between the rising and falling edge (essentially. and the more pertinent. manipulating an output compare register value) pulse width modulation was achieved. constructed and tested in the power lab (ELWB303) under the supervision of Dr. Initially. Discussion The project was prepared.K. A. The rising edge of the control waveform is used to trigger the gating pulses to one arm of the H-Bridge while the falling edge is used to trigger the gating pulses to the other arm of the bridge. Tyler Nitsch. Matt Weber. Soldering was completed in ELWB303 with a basic soldering iron or in ELWB320 with the lab technicians’ high end soldering iron.K.8. Programming of the ATmega8 microcontroller was complete in the designated ELEC499 lab on a PC. Bhat. Geoff Lindsay Page 33 .

Matt Weber. A. Geoff Lindsay Page 34 . MathCAD was utilized to calculate the LCC resonant tank gain and the output voltage at various stages of the circuit. is an important design parameter. The step down transformer was also hand wound around a similar high frequency magnetic core. The first approach that was taken was to calculate arbitrary values of series inductance and series capacitance based on the resonant frequency that was required for this application. The ratio of Ls (series inductance) to the load resistance for example.K.Further work on this design would begin by first incorporating an external control leading naturally into a closed loop design. The LCC topology is advantageous for this design for a number of reasons mentioned above. With this in mind. Tyler Nitsch. Choice of the LCC resonant tank components was a difficult task involving numerous calculations and recalculations. Cn := Cs Cp Qs := ωr⋅ Ls R_load Once this approach was verified. By selecting the capacitors beforehand and using these values to calculate the gain of the LCC resonant tank we were able to construct a new set of boundary conditions for the calculation of the series inductor. Bhat based on previously published results. construction of the LCC resonant tank began. Final LCC tank configuration is available in Table 1. After closer inspection of the reference papers it was realized that a more rigorous method of choosing LCC tank values was needed. Choosing of the LCC The LCC topology was recommended by Dr. Below are the two most important equations for LCC resonant tank design.S. The target application for the LCC resonant inverter constructed here is a high frequency distributed bus. It soon became clear that the initial capacitances that were calculated would not be available and some recalculation was necessary. Sean Clutterbuck. Capacitance and inductance was verified using a 1kHz RLC multi-meter. The series inductor was hand wound around a high frequency magnetic core. the remaining LCC tank values were calculated using proven design parameters.1µF high frequency. At this point. high voltage capacitors. Exact values of the series and parallel capacitors were not available and they were constructed from series and parallel combinations of 0.

As the load was decreased. The targeted design constraints. efficiencies remained high. Matt Weber.Concluding Comments Above all else a high level of confidence with high power equipment and measurement techniques was gained. The experience in design. Tyler Nitsch. Another important consideration to mention is the disproportionate variation of the inherent inductance with decreased load. At full resistive (partially inductive) load an efficiency of 93. Sean Clutterbuck.75% total harmonic distortion (THD). This prohibited measurement of a purely resistive load and hindered efforts to accurately vary the power factor.09% with THD of 8. circuit troubleshooting and simulation was invaluable. At 11% load the efficiency of the circuit was measured as 76.66%. The fact that the large inherent inductance did not significantly affect the result obtained at reduced loads helps to validate the operation of the LCC resonant tank. high efficiencies were achieved. including efficiency.64% was obtained with less than 7. output voltage and output power. Despite the aforementioned difficulties. were met successfully. An important factor in the test procedure was the self inductance of the Lab-Volt resistance boxes. As the load was decreased the inductance increased dramatically making 11% load results nearly meaningless as the power factor of the load was so low. Geoff Lindsay Page 35 . redesign.

By varying the output of the bridge the power delivered to the load is varied thus maintaining the 28VRMS output across the load terminals (also the parallel capacitor terminals). Second. A limitation of winding the inductor and the transformer was realized in the 1kHz test frequency output by the multi-meter. Recommendations The LCC resonant inverter topology constructed for this project serves as a strong foundation for a marketable high frequency distributed bus inverter. the LCC topology described in this report needs optimization. a more precise method of measuring the inductance and the transformer inductance would have aided in the implementation of the LCC tank and could be utilized to optimize the design at a later date. This method also varies the values of the resonant tank and recalculation is again required. Tyler Nitsch. the LCC resonant inverter would have to have a closed loop control circuit built in to adjust the pulse width as the load varied.9. Before marketing this device there are a number of foreseeable developments that would need to be first added. Sean Clutterbuck. Ideally. Finally. Closed Loop Design Closed loop design implies that as the load current changes the pulse width modulation used to control the bridge output voltage would be automatically adjusted. By programming the gate pulse generation into a microprocessor this closed loop design would be a simple addition to the inverter package. the LCC resonant inverter could be designed and packaged in a space efficient manner. Another method of optimizing the circuit is to adjust the switching frequency slightly to vary the ratio of the resonant frequency to the switching frequency. A reference voltage take from the output could be monitored and scaled to control the duty cycle of the control waveform thus varying the duty cycle of the bridge output voltage. If it were possible to construct the exact components needed then it would be possible to achieve a more ideal tank gain. LCC Resonant Tank Optimization Due to limitations of available components and measurement equipment the capacitors and inductors in the LCC tank were subject to some drift from the ideal. First. Matt Weber. Geoff Lindsay Page 36 .

This last would require more sophisticated test gear and much more lab time. Geoff Lindsay Page 37 .Packaging Before finalizing a marketable product some consideration of packaging and documentation would need to be decided upon. Matt Weber. Packaging should be tailored to suit applications in aerospace and aeronautics where size and weight are paramount. Tyler Nitsch. Sean Clutterbuck. Documentation should also be compiled listing key operating parameters of the entire LCC resonant inverter.

Dalal. Lee. Tyler Nitsch. pp 326-338.C. “Analysis and DesignOptimization of LCC Resonant Inverter for High-Frequency AC Distributed Power System”. “A Generalized Approach for the Steady-State Analysis of Resonant Inverters”. Shashi B. Vol. pp 1002-1009. Geoff Lindsay Page 38 . Jovanic. A. R. in IEEE Transactions on Industrial Electronics. March/April 1989.K. 1.M. No. 5.T. Dewan. No. [2]J. 42. [4] Dhaval B. Matt Weber. pp 265-274. in IEEE Transactions on Industrial Electronics. 1990. Vol. Sean Clutterbuck. October 1992.10. Bhat.S. in IEEE Transactions on Industrial Electronics. pp 63-71. M. in Digital Equiptment Corporation. No.K. F. Sabate. [3] A. IEEE. Bhat. “A 500kHz Multi-Output Converter with Zero Voltage Switching”. February 1995. Gean. 25. 28. 2. References [1] A.S. Vol. “Fixed Frequency PWM Series-Parallel Resonant Converter”.

General Description of Approach: .hi time for main control signal . .def . Geoff Lindsay Page 39 .At 100% load.We are using PORTB1.def .There must also be a delay between the turn off of G1 and G4 . . .org 0x000 rjmp Reset .------------------------------------------------------------------------------------------------. Geoff Lindsay.Authors: Tyler Nitsch.Delay time for rise and fall .SO! Our Gating pulses come from the following PORTB outputs: . . . G4. .4 as our output gating signals . Tyler Nitsch. . Sean Clutterbuck.timer counter 1 compare match A . . As labeled on the H-Bridge PCB.11.finally G3 as the top right-most switch.Register definitions for variables .def pwmhi=r16 pwmlo=r17 pwmT=r18 tf=r19 temp=r20 temp2=r21 . Switch G4 = PORTB1 = PIN 15 .include "m8def. . Switch G1 = PORTB3 = PIN 17 .timer counter 1 compare match B Matt Weber. .lo time for main control signal .It must be noted that on an H-bridge we have defined the following. This delay is also seen in the .inc" .def .3. and . Matt Weber.Interrupt Service Vectors .org OC1Aaddr rjmp T1comA . .into the turn on of G2 and G3. G1 and G4 are in phase as well as G2 and G2 .Moving counter-clockwise through the switches we have G2. Switch G3 = PORTB2 = PIN 16 .org OC1Baddr rjmp T1comB . Switch G2 = PORTB4 = PIN 18 .Date: July 2006. . Appendices ATmega8 Microcontroller Code .Period of control signal .------------------------------------------------------------------------------------------------.MOSFET Gating Pulse Generation for the ATMEL ATmega8.2.Starting at the top left switch in the H-bridge we have switch G1 . Sean Clutterbuck.def .reverse where G2 and G3 turn off and G1 and G4 turn on.def .

0x01 .sets data direction for pins out DDRB.temp .temp ldi temp.0x01 out OCR1AH.This Changes duty cycle change me change me .(1<<DDB4)|(1<<DDB3)|(1<<DDB2)|(1<<DDB1) .Set stack ptr to ram end .(PORTB2) rjmp bit2clear nop . Geoff Lindsay Page 40 .Clear G3 tf.100% 0x01 15% 0x00 out OCR1BH.(1<<WGM12)+(1<<CS10) out TCCR1B.(1<<OCIE1A)+(1<<OCIE1B) out TIMSK.initialize interrupts and service routines Reset: ldi out ldi out temp. Tyler Nitsch.0x90 .0x90 out OCR1AL..temp .Initialize timercounter1 and interrupts ldi temp.Rising of Control signal T1comA: sbis PORTB.temp .temp .--------------------------------------------------.loads compare value for duty cycle note must load H before low ldi temp.these nop’s make both pulses have equivalent duty cycle nop nop cbi PORTB.Reset vector .temp .100% 0x90 15% 0x30 out OCR1BL.tc1 compare matchA and matchB interrupts .Initialize outputs ldi temp.high(RAMEND) SPH.Control signal values are here for Peroid value correspond to # of CPU cycles .temp temp.0x01 Matt Weber.------------------------------------------.loads max count value for TimerCounter1 .CS10 no prescale run at clock speed .low(RAMEND) SPL.this is our period of control waveform ldi temp. Sean Clutterbuck.WGM12 Clear timer on compare to OCIE1A .temp ldi temp.set data direction to out ldi sei loop: rjmp loop . temp ldi temp.(PORTB2) .

Clear G2 rcall DELAY sbi PORTB.Clear G1 rcall DELAY sbi PORTB.Set G2 reti .Clear G4 .(PORTB4) rjmp bit4clear nop . Tyler Nitsch. Sean Clutterbuck.Set G3 T1comB: sbis PORTB.Delay subroutine DELAY: ldi temp.Set G1 reti bit4clear: cbi PORTB.tf rjmp loopy ret Matt Weber.(PORTB1) reti bit2clear: cbi PORTB.(PORTB2) reti .rcall DELAY sbi PORTB.(PORTB4) .(PORTB3) . Geoff Lindsay Page 41 .(PORTB4) .0x00 loopy: inc temp cpse temp.(PORTB1) rcall DELAY sbi PORTB.(PORTB3) .Set G4 .Falling of Control signal .these nops make both pulses have equivalent duty cycle nop nop cbi PORTB.

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