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R12 INTEL UMA/DISCRETE SYSTEM DIAGRAM


+3V/+5V
A A

PG.31
+1.05VTT/+1.8V SODIMM1 DDR3 INTEL 14.318MHz
Max. 4GB
PG.32
PG.12
Channel A
Arrandale AMD CLOCK GEN
PG.2
CPU Core PCI-E x8 Seymour-XT
37.5mm X 37.5mm
PG.33 SODIMM2 DDR3 989pin PGA PP;PP
VGACore/+1.1V Max. 4GB
Channel B TDP 35W 7'3:
PG.13
PG.34
PG.3~6 PG.14~18
+1.5VSUS DDR3 900MHz
FDI DMI
B
PG.35 VRAM B

64Mx16x4,64bit PG.19
Charger SATA0
PG.36 HDD PG.23 HDMI
Discharger Level
SATA1 Shifter HDMI PG.21
PG.37
ODD PG.23
INTEL PCH DP Port B PG.21
UMA VGACORE CRT
PG.38
Ibex Peak-m CRT PG.22

LVDS LVDS PG.20


3&,([
27mm X 25mm
LAN3 LAN2 LAN1
C
1071pin FCBGA USB2.0 Ports Webcam BT C

Card reader LAN WLAN USB 2.0 TDP 5W X2 PG.26 PG.20 Softbreeze
PG.26
RTS5219-GR RTS8165EH BT COMBO PORT10 PORT0,1 PORT4 PORT13
10/100 PG.24 10/100 PG.27 PG.30 USB 2.0

Stackup
KBC LPC PG.7~11 TOP
EnE KB3930QF D2 PG.29
GND
Azalia
IN1
KB TP ROM FAN IN2
Speaker
AUDIO PG.25 VCC
D

CODEC BOT D

HP/MIC
PG.26
IDT92HD80B1 352-(&75
Analog MIC 4XDQWD&RPSXWHU,QF
PG.25 PG.25
Size Document Number Rev
Custom 1A
BLOCK DIAGRAM
Date: Tuesday, September 14, 2010 Sheet 1 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

25mA 150mA 150mA


02
+3V +VDDCORE_CLK Y6
+1.05V +VDDIO_CLK +3V +VDDSE_CLK L53 XTAL_IN 1 2XTAL_OUT +3V
L56 L57 1 2 C733 4.7U/6.3V_6
1 2 C742 0.1U/10V_4 1 2 C704 4.7U/6.3V_6 *HCB1608KF-181T15/1.5A_6
14.318MHZ

1
HCB1608KF-181T15/1.5A_6 C723 0.1U/10V_4 HCB1608KF-181T15/1.5A_6 C731 0.1U/10V_4 +1.5V C729 0.1U/10V_4
C747 10U/6.3VS_6 C705 0.1U/10V_4 L54 C711 0.1U/10V_4 C702 C703 R474
A A
C746 *10U/6.3V_8 1 2 C716 0.1U/10V_4 33P/50V_4 33P/50V_4 *10K_4

2
HCB1608KF-181T15/1.5A_6

Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin CPU_SEL

R476
0510 add for WiMAX 10K_4
close to U13

C714 *3.3P/50V_4
CLK_BUF_BCLK_P CLK_BUF_BCLK_N 0 1

CPU_SEL CPU0/1=133MHz CPU0/1=100MHz


(default)
U29

+VDDSE_CLK 5 23 CLK_BUF_BCLK_P CLK_BUF_BCLK_P <8>


VDD_LCD CPU-0 CLK_BUF_BCLK_N
29 VDD_REF CPU-0# 22 CLK_BUF_BCLK_N <8>

+VDDCORE_CLK 1 VDD_USB CPU-1 20


2 1 17 VDD_SRC CPU-1# 19
C722 *0.047U/10V_4 24

+VDDIO_CLK 18
VDD_CPU
9LRS3197 3 CLK_BUF_DREFCLK CLK_BUF_DREFCLK <8>
+3V
VDD_CPU_IO DOT96T_LPR CLK_BUF_DREFCLK#
B 2 1 15 VDD_SRC_IO DOT96C_LPR 4 CLK_BUF_DREFCLK# <8> B
C737 *0.047U/10V_4
<8,12,13> CGDAT_SMB 31 13 CLK_BUF_PCIE_3GPLL CLK_BUF_PCIE_3GPLL <8>
SDATA SRC-1 CLK_BUF_PCIE_3GPLL# R493
<8,12,13> CGCLK_SMB 32 SCLK SRC-1# 14 CLK_BUF_PCIE_3GPLL# <8>
1K_4
+3V R494 10K_4 16 10 CLK_BUF_DREFSSCLK CLK_BUF_DREFSSCLK <8>
CLK_ICH_14M R478 33_4 CPU_SEL CPU_STOP# SATA CLK_BUF_DREFSSCLK#
<8> CLK_ICH_14M 30 REF_0/CPU_SEL SATA# 11 CLK_BUF_DREFSSCLK# <8>
C708 *10P/50V_4 CK_PWRGD_R
CK_PWRGD_R 25 6 CLK_VGA_27M_NOSS R491 *22_4 PCH_CLK_27M_1
CK_PW RGD/PD#_3.3 27MHz_nonSS
Place R8044 within 0.5" of C/G 27MHz_SS 7 0918 SI Modify

3
XTAL_OUT 27 UMA remove Q39
XTAL_IN XOUT CLK_VGA_27M_SS 2N7002E
28 33
9
XIN
VSS_SATA
QFN32 GND
VSS_REF 26 8/25 SI for H/W
T46
R495
2 VSS_USB VSS_CPU 21 Discrete only <33> VR_PWRGD_CLKEN# 2 100K_4
8 VSS_LCD VSS_SRC 12

ICS9LVS3197

1
AL003197001
IC OTHER(32P) ICS9LVS3197AKLFT(MLF)

Vender Part Part Number Part Description


ICS ICS9LVS3197 AL003197000 IC OTHER(32P) ICS9LVS3197AKLFT(MLF)
Realtek RTM890N-632 AL000890000 IC OTHER(32P) RTM890N-632-GRT(QFN)
Silego SLG8LV595VTR AL000595000 IC OTHER(32P)SLG8LV595VTR(QFN) +3V
C
8/25 SI for H/W UMA remove C
C741 *0.1U/10V_4
DGPU_PWROK <10,17,29,34,35>

1
U30

PCH_CLK_27M_1 2 4 PCH_CLK_27M <15>


*74LVC1G126

+1.05V <7,8,9,11,39>
+1.5V <5,30>
+3V <3,7,8,9,10,11,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36>

D D

352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 1A
Clock Gen(9LRS3197)
Date: Sunday, September 19, 2010 Sheet 2 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

DIS UMA

<9> DMI_TXN0 A24


U15A

DMI_RX#[0]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
B26 PEG_COMP R288
A26
B27
49.9/F_4
Ra
Rb
Rc
NA 0 ohm
0 ohm NA
0 ohm NA
03
<9> DMI_TXN1 C23 DMI_RX#[1] PEG_RBIAS A25 PEG_RBIAS R289 750/F_4
<9> DMI_TXN2 B22 DMI_RX#[2] PEG_RX#[0..7] <14>
<9> DMI_TXN3 A21 K35 PEG_RX#0 U15B
DMI_RX#[3] PEG_RX#[0] PEG_RX#1 R139 20/F_4 H_COMP3 AT23
PEG_RX#[1] J34 COMP3 BCLK A16 CLK_CPU_BCLK <10>
<9> DMI_TXP0 B24 J33 PEG_RX#2 R142 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# <10>
DMI_RX[0] PEG_RX#[2] PEG_RX#3 R81 49.9/F_4 H_COMP1 G16 COMP2 BCLK#
A <9> DMI_TXP1 D23 DMI_RX[1] PEG_RX#[3] G35 COMP1 MISC A
<9> DMI_TXP2 B23 G32 PEG_RX#4 R143 49.9/F_4 H_COMP0 AT26 AR30 For ITP CLk
DMI_RX[2] PEG_RX#[4] PEG_RX#5 COMP0 BCLK_ITP
<9> DMI_TXP3 A22 DMI_RX[3] PEG_RX#[5] F34 AH24 SKTOCC# BCLK_ITP# AT30 CLK_PCIE_3GPLL <8>
F31 PEG_RX#6 CLK_PCIE_3GPLL# <8>
PEG_RX#[6] PEG_RX#7
D24 D35
CLOCKSPEG_CLK# E16 Rc
<9>
<9>
DMI_RXN0
DMI_RXN1 G24
F23
DMI_TX#[0]
DMI_TX#[1] DMI PEG_RX#[7]
PEG_RX#[8] E33
C33
H_CATERR# AK14
AT15
CATERR#
PEG_CLK
D16
Ra
<9> DMI_RXN2 DMI_TX#[2] PEG_RX#[9] <10> H_PECI PECI
<9> DMI_RXN3 H23 D32 <29,33> H_PROCHOT# AN26 THERMAL A18 DREFSSCLK_R DREFSSCLK <8>
DMI_TX#[3] PEG_RX#[10] PROCHOT# DPLL_REF_SSCLK DREFSSCLK#_R
PEG_RX#[11] B32 <10,29> PM_THRMTRIP# AK15 THERMTRIP# DPLL_REF_SSCLK# A17 DREFSSCLK# <8>
<9> DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31 Rb
<9> DMI_RXP1 F24 DMI_TX[1] PEG_RX#[13] B28
<9> DMI_RXP2 E23 B30 H_CPURST# AP26 F6 DDR3_DRAMRST#_C
DMI_TX[2] PEG_RX#[14] T31 RESET_OBS# SM_DRAMRST#
<9> DMI_RXP3 G23 DMI_TX[3] PEG_RX#[15] A31 <9> PM_SYNC AL15 PM_SYNC
J35 PEG_RX0
PEG_RX[0..7] <14> AN14
AN27
VCCPWRGOOD_1 DDR3 SM_RCOMP[0] AL1 SM_RCOMP_0R363
AM1 SM_RCOMP_1R364
100/F_4
24.9/F_4
PEG_RX[0] <10> H_PW RGOOD VCCPWRGOOD_0
2.7GT/s data rate PEG_RX[1] H34
H33
PEG_RX1
PEG_RX2
<9> PM_DRAM_PW RGD AK13 SM_DRAMPWROK MISC SM_RCOMP[1]
SM_RCOMP[2] AN1 SM_RCOMP_2R365
R176
130/F_4
10K_4
<9> FDI_TXN[7:0] PEG_RX[2] +1.05V_VTT
FDI_TXN0 E22 F35 PEG_RX3 H_PW RGD_XDP AM26 AN15 PM_EXT_TS#0
R177 *0_4/S PM_EXTTS#0 <12,13>
FDI_TX#[0] PEG_RX[3] T45 TAPPWRGOOD PM_EXT_TS#[0]
FDI_TXN1 D21 G33 PEG_RX4 AP15 PM_EXT_TS#1
R166 *0_4/S PM_EXTTS#1 <13>
FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_RX5 H_VTTPW RGD AM15 PM_EXT_TS#[1] R168 10K_4
D19 FDI_TX#[2] PEG_RX[5] E34 VTTPWRGOOD +1.05V_VTT
FDI_TXN3 D18 F32 PEG_RX6 <8,14,24,27,29,30> PLTRST# CPU_PLTRST# AL14
FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_RX7 R124 1.5K/F_4 RSTIN# XDP_PRDY#
G21 FDI_TX#[4] PEG_RX[7] D34 PRDY# AT28 T44
FDI_TXN5 E19 F33 AP27 XDP_PREQ#
FDI_TXN6 F21
FDI_TX#[5]
Intel(R) FDI PEG_RX[8]
B33 R126 750/F_4 PWR MANAGEMENT
PREQ#
AN28 XDP_TCLK
T28
T25

PCI EXPRESS -- GRAPHICS


FDI_TXN7 FDI_TX#[6] PEG_RX[9] TCK
G18 FDI_TX#[7] PEG_RX[10] D31
A32 AP28 XDP_TMS T27
PEG_RX[11] TMS
<9> FDI_TXP[7:0] PEG_RX[12] C30
FDI_TXP0 D22 A28 AT27 XDP_TRST#

B
FDI_TXP1
FDI_TXP2
C21
D20
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
B29
A30
AJ22
AK22
BPM#[0]
BPM#[1]
JTAG & BPM TRST#

TDI AT29 XDP_TDI_R


T32

T33 B
FDI_TXP3 C18 PEG_TX#[0..7] <14> AK24 AR27 XDP_TDO_R T30
FDI_TXP4 FDI_TX[3] C_PEG_TX#0 C543 PEG_TX#0 BPM#[2] TDO
G22 FDI_TX[4] PEG_TX#[0] L33 0.1U/10V_4 AJ24 BPM#[3] TDI_M AR29 XDP_TDI_M T29
FDI_TXP5 E20 M35 C_PEG_TX#1 C549 0.1U/10V_4 PEG_TX#1 AJ25 AP29 XDP_TDO_M T26
FDI_TXP6 FDI_TX[5] PEG_TX#[1] C_PEG_TX#2 C554 0.1U/10V_4 PEG_TX#2 BPM#[4] TDO_M
F20 FDI_TX[6] PEG_TX#[2] M33 AH22 BPM#[5]
FDI_TXP7 G19 M30 C_PEG_TX#3 C561 0.1U/10V_4 PEG_TX#3 AK23
FDI_TX[7] PEG_TX#[3] C_PEG_TX#4 C565 0.1U/10V_4 PEG_TX#4 BPM#[6]
PEG_TX#[4] L31 AH23 BPM#[7] DBR# AN25 XDP_DBRESET# <9>
F17 K32 C_PEG_TX#5 C570 0.1U/10V_4 PEG_TX#5
<9> FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5]
E17 M29 C_PEG_TX#6 C577 0.1U/10V_4 PEG_TX#6 IC,AUB_CFD_rPGA,R1P0
<9> FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 C_PEG_TX#7 C582 0.1U/10V_4 PEG_TX#7
PEG_TX#[7]
<9> FDI_INT C17 FDI_INT PEG_TX#[8] K29
PEG_TX#[9] H30
<9> FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29
<9> FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29
PEG_TX#[12] E28 UMA remove
PEG_TX#[13] D29
PEG_TX#[14] D27
PEG_TX#[15] C26

L34 C_PEG_TX0 C537 0.1U/10V_4 PEG_TX0


PEG_TX[0..7] <14> +1.05V_VTT JTAG MAPPING
PEG_TX[0] C_PEG_TX1 C546 0.1U/10V_4 PEG_TX1
PEG_TX[1] M34
M32 C_PEG_TX2 C550 0.1U/10V_4 PEG_TX2 XDP_TDO_R R144 51_4
PEG_TX[2] C_PEG_TX3 C557 0.1U/10V_4 PEG_TX3 H_CATERR# R119 49.9/F_4
PEG_TX[3] L30
M31 C_PEG_TX4 C562 0.1U/10V_4 PEG_TX4 H_PROCHOT# R130 56.2/F_4
PEG_TX[4] C_PEG_TX5 C566 0.1U/10V_4 PEG_TX5 CPU_PLTRST# R123 *68_4 XDP_TDI_R
PEG_TX[5] K31 Ra
M28 C_PEG_TX6 C572 0.1U/10V_4 PEG_TX6 XDP_TMS R138 *51_4 XDP_TDO_M Rb
PEG_TX[6] C_PEG_TX7 C578 0.1U/10V_4 PEG_TX7 XDP_TDI_R R145 *51_4
PEG_TX[7] H31
K28 XDP_PREQ# R141 *51_4 Rc
PEG_TX[8] R140
PEG_TX[9] G30
C G29 XDP_TCLK R137 *51_4 0_4 C
PEG_TX[10]
PEG_TX[11] F28
PEG_TX[12] E27
D28 XDP_TDI_M Rd
PEG_TX[13] XDP_TDO_R
PEG_TX[14] C27 Re
PEG_TX[15] C25
+3V
IC,AUB_CFD_rPGA,R1P0 XDP_TRST#
U10

5
MC74VHC1G08DFT2G 2 R170 R147
4HW PG_1 H_VTTPW RGD 51_4
<29,31,32,35,38,39> HW PG 1 2K/F_4
for S3 power reduction
R164

3
1K/F_4
R62 *0_4

Q6 BSS138_NL

DDR3_DRAMRST#_C 1 3 +3VS5 +1.5VSUS


DDR3_DRAMRST# <12,13>
Scan Chain STUFF -> Ra, Rc, Re
SI modify (Default) NO STUFF -> Rb, Rd
2

R66 SI modify R178


*0_4 CPU Only STUFF -> Ra, Rb
PCIE_CLK_REQ7# <10> R187 R186 NO STUFF -> Rc, Rd, Re
100K_4 *10K_4 *8.2K_4
R184 *0_4 R172 *0_4/S HW PG_1
5

D
R58 10K_4 GMCH Only STUFF -> Rd, Re D
C98 2 1 +3VS5 2 R179 NO STUFF -> Ra, Rb, Rc
0.047U/10V_4 4 1.5K/F_4
<32> STAT_1.1 1

PM_DRAM_PW RGD
352-(&75
3

U9
*MC74VHC1G08DFT2G

Use a voltage divider with VDDQ (1.5 V) rail


R163
750/F_4
4XDQWD&RPSXWHU,QF
<5,10,11,29,32,33,38> +1.05V_VTT
<5,12,13,34,35,36> +1.5VSUS ON in S3) and resistor combination of 1.5K 1%
<2,7,8,9,10,11,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V (to VDDQ)/7501% (to GND) to convert to Size Document Number Rev
Custom 1A
processor VTT level. PROCESSER 1/4(HOST&PEX)
Date: Sunday, September 19, 2010 Sheet 3 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

04
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

A A
<13> M_B_DQ[63:0]
<12> M_A_DQ[63:0] U15C U15D
M_A_DQ0 A10 AA6 M_A_CLK0 <12> M_B_DQ0 B5 W8 M_B_CLK0 <13>
M_A_DQ1 C10 SA_DQ[0] SA_CK[0] M_B_DQ1 SB_DQ[0] SB_CK[0]
SA_DQ[1] SA_CK#[0] AA7 M_A_CLK0# <12> A5 SB_DQ[1] SB_CK#[0] W9 M_B_CLK0# <13>
M_A_DQ2 C7 P7 M_A_CKE0 <12> M_B_DQ2 C3 M3 M_B_CKE0 <13>
M_A_DQ3 SA_DQ[2] SA_CKE[0] M_B_DQ3 SB_DQ[2] SB_CKE[0]
A7 SA_DQ[3] B3 SB_DQ[3]
M_A_DQ4 B10 Y6 M_A_CLK1 <12> M_B_DQ4 E4 V7 M_B_CLK1 <13>
M_A_DQ5 D10 SA_DQ[4] SA_CK[1] M_B_DQ5 SB_DQ[4] SB_CK[1]
SA_DQ[5] SA_CK#[1] Y5 M_A_CLK1# <12> A6 SB_DQ[5] SB_CK#[1] V6 M_B_CLK1# <13>
M_A_DQ6 E10 P6 M_A_CKE1 <12> M_B_DQ6 A4 M2 M_B_CKE1 <13>
M_A_DQ7 SA_DQ[6] SA_CKE[1] M_B_DQ7 SB_DQ[6] SB_CKE[1]
A8 SA_DQ[7] C4 SB_DQ[7]
M_A_DQ8 D8 AE2 M_A_CS#0 <12> M_B_DQ8 D1 AB8 M_B_CS#0 <13>
M_A_DQ9 F10 SA_DQ[8] SA_CS#[0] M_B_DQ9 SB_DQ[8] SB_CS#[0]
SA_DQ[9] SA_CS#[1] AE8 M_A_CS#1 <12> D2 SB_DQ[9] SB_CS#[1] AD6 M_B_CS#1 <13>
M_A_DQ10 E6 M_B_DQ10 F2
M_A_DQ11 F7 SA_DQ[10] M_B_DQ11 SB_DQ[10]
SA_DQ[11] SA_ODT[0] AD8 M_A_ODT0 <12> F1 SB_DQ[11] SB_ODT[0] AC7 M_B_ODT0 <13>
M_A_DQ12 E9 AF9 M_A_ODT1 <12> M_B_DQ12 C2 AD1 M_B_ODT1 <13>
M_A_DQ13 B7 SA_DQ[12] SA_ODT[1] M_B_DQ13 SB_DQ[12] SB_ODT[1]
SA_DQ[13] M_A_DM[7:0] <12> F5 SB_DQ[13] M_B_DM[7:0] <13>
M_A_DQ14 E7 B9 M_A_DM0 M_B_DQ14 F3 D4 M_B_DM0
M_A_DQ15 C6 SA_DQ[14] SA_DM[0] SB_DQ[14] SB_DM[0]
SA_DQ[15] SA_DM[1] D7 M_A_DM1 DM signals are not present on Clarkfield M_B_DQ15 G4 SB_DQ[15] SB_DM[1] E1 M_B_DM1 DM signals are not present on Clarkfield
M_A_DQ16 H10 H7 M_A_DM2 processor. All DM signal can be left as M_B_DQ16 H6 H3 M_B_DM2 processor. All DM signal can be left as
M_A_DQ17 G8 SA_DQ[16] SA_DM[2] SB_DQ[16] SB_DM[2]
SA_DQ[17] SA_DM[3] M7 M_A_DM3 NC on Clarkfield and connect directly to M_B_DQ17 G2 SB_DQ[17] SB_DM[3] K1 M_B_DM3 NC on Clarkfield and connect directly to
M_A_DQ18 K7 AG6 M_A_DM4 M_B_DQ18 J6 AH1 M_B_DM4
SA_DQ[18] SA_DM[4] GND on So-DIMM side for Clarkfield SB_DQ[18] SB_DM[4] GND on So-DIMM side for Clarkfield
M_A_DQ19 J8 AM7 M_A_DM5 M_B_DQ19 J3 AL2 M_B_DM5
M_A_DQ20 G7 SA_DQ[19] SA_DM[5] design only SB_DQ[19] SB_DM[5] design only
SA_DQ[20] SA_DM[6] AN10 M_A_DM6 M_B_DQ20 G1 SB_DQ[20] SB_DM[6] AR4 M_B_DM6

DDR SYSTEM MEMORY A


M_A_DQ21 G10 AN13 M_A_DM7 M_B_DQ21 G5 AT8 M_B_DM7

DDR SYSTEM MEMORY B


M_A_DQ22 SA_DQ[21] SA_DM[7] M_B_DQ22 SB_DQ[21] SB_DM[7]
J7 SA_DQ[22] M_A_DQS#[7:0] <12> J2 SB_DQ[22] M_B_DQS#[7:0] <13>
M_A_DQ23 J10 C9 M_A_DQS#0 M_B_DQ23 J1 D5 M_B_DQS#0
M_A_DQ24 SA_DQ[23] SA_DQS#[0] M_A_DQS#1 M_B_DQ24 SB_DQ[23] SB_DQS#[0] M_B_DQS#1
L7 SA_DQ[24] SA_DQS#[1] F8 J5 SB_DQ[24] SB_DQS#[1] F4
M_A_DQ25 M6 J9 M_A_DQS#2 M_B_DQ25 K2 J4 M_B_DQS#2
M_A_DQ26 M8 SA_DQ[25] SA_DQS#[2] SB_DQ[25] SB_DQS#[2]
B SA_DQ[26] SA_DQS#[3] N9 M_A_DQS#3 M_B_DQ26 L3 SB_DQ[26] SB_DQS#[3] L4 M_B_DQS#3 B
M_A_DQ27 L9 AH7 M_A_DQS#4 M_B_DQ27 M1 AH2 M_B_DQS#4
M_A_DQ28 SA_DQ[27] SA_DQS#[4] SB_DQ[27] SB_DQS#[4]
L6 SA_DQ[28] SA_DQS#[5] AK9 M_A_DQS#5 M_B_DQ28 K5 SB_DQ[28] SB_DQS#[5] AL4 M_B_DQS#5
M_A_DQ29 K8 AP11 M_A_DQS#6 M_B_DQ29 K4 AR5 M_B_DQS#6
M_A_DQ30 N8 SA_DQ[29] SA_DQS#[6] SB_DQ[29] SB_DQS#[6]
SA_DQ[30] SA_DQS#[7] AT13 M_A_DQS#7 M_B_DQ30 M4 SB_DQ[30] SB_DQS#[7] AR8 M_B_DQS#7
M_A_DQ31 P9 M_A_DQS[7:0] <12> M_B_DQ31 N5 M_B_DQS[7:0] <13>
M_A_DQ32 AH5 SA_DQ[31] SB_DQ[31]
SA_DQ[32] SA_DQS[0] C8 M_A_DQS0 M_B_DQ32 AF3 SB_DQ[32] SB_DQS[0] C5 M_B_DQS0
M_A_DQ33 AF5 F9 M_A_DQS1 M_B_DQ33 AG1 E3 M_B_DQS1
M_A_DQ34 AK6 SA_DQ[33] SA_DQS[1] SB_DQ[33] SB_DQS[1]
SA_DQ[34] SA_DQS[2] H9 M_A_DQS2 M_B_DQ34 AJ3 SB_DQ[34] SB_DQS[2] H4 M_B_DQS2
M_A_DQ35 AK7 M9 M_A_DQS3 M_B_DQ35 AK1 M5 M_B_DQS3
M_A_DQ36 AF6 SA_DQ[35] SA_DQS[3] SB_DQ[35] SB_DQS[3]
SA_DQ[36] SA_DQS[4] AH8 M_A_DQS4 M_B_DQ36 AG4 SB_DQ[36] SB_DQS[4] AG2 M_B_DQS4
M_A_DQ37 AG5 AK10 M_A_DQS5 M_B_DQ37 AG3 AL5 M_B_DQS5
M_A_DQ38 AJ7 SA_DQ[37] SA_DQS[5] SB_DQ[37] SB_DQS[5]
SA_DQ[38] SA_DQS[6] AN11 M_A_DQS6 M_B_DQ38 AJ4 SB_DQ[38] SB_DQS[6] AP5 M_B_DQS6
M_A_DQ39 AJ6 AR13 M_A_DQS7 M_B_DQ39 AH4 AR7 M_B_DQS7
M_A_DQ40 AJ10 SA_DQ[39] SA_DQS[7] M_B_DQ40 SB_DQ[39] SB_DQS[7]
SA_DQ[40] M_A_A[15:0] <12> AK3 SB_DQ[40] M_B_A[15:0] <13>
M_A_DQ41 AJ9 Y3 M_A_A0 M_B_DQ41 AK4 U5 M_B_A0
M_A_DQ42 AL10 SA_DQ[41] SA_MA[0] M_A_A1 M_B_DQ42 SB_DQ[41] SB_MA[0] M_B_A1
SA_DQ[42] SA_MA[1] W1 AM6 SB_DQ[42] SB_MA[1] V2
M_A_DQ43 AK12 AA8 M_A_A2 M_B_DQ43 AN2 T5 M_B_A2
M_A_DQ44 AK8 SA_DQ[43] SA_MA[2] M_A_A3 M_B_DQ44 SB_DQ[43] SB_MA[2] M_B_A3
SA_DQ[44] SA_MA[3] AA3 AK5 SB_DQ[44] SB_MA[3] V3
M_A_DQ45 AL7 V1 M_A_A4 M_B_DQ45 AK2 R1 M_B_A4
M_A_DQ46 AK11 SA_DQ[45] SA_MA[4] M_A_A5 M_B_DQ46 SB_DQ[45] SB_MA[4] M_B_A5
SA_DQ[46] SA_MA[5] AA9 AM4 SB_DQ[46] SB_MA[5] T8
M_A_DQ47 AL8 V8 M_A_A6 M_B_DQ47 AM3 R2 M_B_A6
M_A_DQ48 AN8 SA_DQ[47] SA_MA[6] M_A_A7 M_B_DQ48 SB_DQ[47] SB_MA[6] M_B_A7
SA_DQ[48] SA_MA[7] T1 AP3 SB_DQ[48] SB_MA[7] R6
M_A_DQ49AM10 Y9 M_A_A8 M_B_DQ49 AN5 R4 M_B_A8
M_A_DQ50 AR11 SA_DQ[49] SA_MA[8] M_A_A9 M_B_DQ50 SB_DQ[49] SB_MA[8] M_B_A9
SA_DQ[50] SA_MA[9] U6 AT4 SB_DQ[50] SB_MA[9] R5
M_A_DQ51 AL11 AD4 M_A_A10 M_B_DQ51 AN6 AB5 M_B_A10
M_A_DQ52 AM9 SA_DQ[51] SA_MA[10] M_A_A11 M_B_DQ52 SB_DQ[51] SB_MA[10] M_B_A11
SA_DQ[52] SA_MA[11] T2 AN4 SB_DQ[52] SB_MA[11] P3
M_A_DQ53 AN9 U3 M_A_A12 M_B_DQ53 AN3 R3 M_B_A12
M_A_DQ54 AT11 SA_DQ[53] SA_MA[12] M_A_A13 M_B_DQ54 SB_DQ[53] SB_MA[12] M_B_A13
SA_DQ[54] SA_MA[13] AG8 AT5 SB_DQ[54] SB_MA[13] AF7
C
M_A_DQ55 AP12 T3 M_A_A14 M_B_DQ55 AT6 P5 M_B_A14 C
M_A_DQ56AM12 SA_DQ[55] SA_MA[14] M_A_A15 M_B_DQ56 SB_DQ[55] SB_MA[14] M_B_A15
SA_DQ[56] SA_MA[15] V9 AN7 SB_DQ[56] SB_MA[15] N1
M_A_DQ57 AN12 M_B_DQ57 AP6
M_A_DQ58AM13 SA_DQ[57] M_B_DQ58 SB_DQ[57]
SA_DQ[58] AP8 SB_DQ[58]
M_A_DQ59 AT14 M_B_DQ59 AT9
M_A_DQ60 AT12 SA_DQ[59] M_B_DQ60 SB_DQ[59]
SA_DQ[60] AT7 SB_DQ[60]
M_A_DQ61 AL13 M_B_DQ61 AP9
M_A_DQ62 AR14 SA_DQ[61] M_B_DQ62 SB_DQ[61]
SA_DQ[62] AR10 SB_DQ[62]
M_A_DQ63 AP14 M_B_DQ63 AT10
SA_DQ[63] SB_DQ[63]

<12> M_A_BS#0 AC3 SA_BS[0] <13> M_B_BS#0 AB1 SB_BS[0]


<12> M_A_BS#1 AB2 SA_BS[1] <13> M_B_BS#1 W5 SB_BS[1]
<12> M_A_BS#2 U7 SA_BS[2] <13> M_B_BS#2 R7 SB_BS[2]

<12> M_A_CAS# AE1 SA_CAS# <13> M_B_CAS# AC5 SB_CAS#


<12> M_A_RAS# AB3 SA_RAS# <13> M_B_RAS# Y7 SB_RAS#
<12> M_A_W E# AE9 SA_WE# <13> M_B_W E# AC6 SB_WE#
IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0

D D

352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 1A
PROCESSER 2/4(DDR)
Date: Tuesday, September 14, 2010 Sheet 4 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

+VCORE
C206
C513
C599
22U/6.3VS_8
22U/6.3VS_8
22U/6.3VS_8
AG35
AG34
AG33
U15F
VCC1
VCC2
VCC3
VTT0_1
VTT0_2
VTT0_3
AH14
AH12
AH11 C589
C573
18A
+1.05V_VTT
10U/6.3V_8
10U/6.3V_8
Rc
DIS
NA
UMA
4.7K
05
C515 22U/6.3VS_8
AG32
AG31
VCC4 VTT0_4 AH10
J14 C539 10U/6.3V_8 Rd NA 0 ohm
C233 22U/6.3VS_8 VCC5 VTT0_5 C49 10U/6.3V_8
C202 22U/6.3VS_8
AG30
AG29
VCC6 VTT0_6 J13
H14 C56 10U/6.3V_8 Re NA 0 ohm
C205 22U/6.3VS_8 VCC7 VTT0_7
C322 22U/6.3VS_8
AG28
AG27
VCC8 VTT0_8 H12
G14 C62 10U/6.3V_8 U15G Rf NA NA
A
C587 22U/6.3VS_8 VCC9 VTT0_9 A
AG26 VCC10 VTT0_10 G13 8/25 SI for H/W.
C285 22U/6.3VS_8 AF35 G12 C179 22U/6.3VS_8 AT21
C281 22U/6.3VS_8 VCC11 VTT0_11 C583 22U/6.3VS_8 VAXG1

SENSE
LINES
AF34 VCC12 VTT0_12 G11 AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE <38>
C604 22U/6.3VS_8 AF33 F14 AT18 AT22 VSS_AXG_SENSE <38>
C593 10U/6.3V_8 VCC13 VTT0_13 VAXG3 VSSAXG_SENSE
AF32 VCC14 VTT0_14 F13 AT16 VAXG4
C282 10U/6.3V_8 AF31 F12 AR21
C283 10U/6.3V_8 VCC15 VTT0_15 VAXG5
AF30 VCC16 VTT0_16 F11 AR19 VAXG6
C516 10U/6.3V_8 AF29 E14 AR18
VCC17 VTT0_17 VAXG7

GRAPHICS VIDs
C251 10U/6.3V_8 AF28 E12 AR16 AM22 GFXVR_VID_0 <38>
C203 10U/6.3V_8 VCC18 VTT0_18 VAXG8 GFX_VID[0]
AF27 VCC19 VTT0_19 D14 AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1 <38>
C312 10U/6.3V_8 AF26 D13 AP19 AN22 GFXVR_VID_2 <38>
C274 10U/6.3V_8 VCC20 VTT0_20 VAXG10 GFX_VID[2]
AD35 VCC21 VTT0_21 D12 AP18 VAXG11 GFX_VID[3] AP23 GFXVR_VID_3 <38>
C216 10U/6.3V_8 AD34 D11 UMA only AP16 AM23

1.1V RAIL POWER


VCC22 VTT0_22 VAXG12 GFX_VID[4] GFXVR_VID_4 <38>
C320 10U/6.3V_8 AD33 C14 AN21 AP24 GFXVR_VID_5 <38>
C321 10U/6.3V_8 VCC23 VTT0_23 VAXG13 GFX_VID[5]
AD32 VCC24 VTT0_24 C13 AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 <38>

GRAPHICS
C603 10U/6.3V_8 AD31 C12 AN18
C204 10U/6.3V_8 VCC25 VTT0_25 VAXG15 GFX_VR_EN
C284 10U/6.3V_8
AD30 VCC26 VTT0_26 C11 Please note that +VCC_GFX_CORE AN16 VAXG16 Rc R372 4.7K_4
AD29 VCC27 VTT0_27 B14 should be 1.05V in Auburndale AM21 VAXG17 GFX_VR_EN AR25 GFXVR_EN <38>
C601 10U/6.3V_8 AD28 B12 AM19 AT25 Rd GFXVR_DPRSLPVR <38>
C298 10U/6.3V_8 VCC28 VTT0_28 VAXG18 GFX_DPRSLPVR
C311 0.1U/10V_4
AD27 VCC29 VTT0_29 A14 AM18 VAXG19 GFX_IMON AM24 Re R195 *1K_4
GFXVR_IMON <38>
C314 0.1U/10V_4
AD26 VCC30 VTT0_30 A13 +VGACORE_IGPU
C590 22U/6.3VS_8
AM16 VAXG20 Rf
AC35 A12 AL21 for S3 power reduction
VCC31 VTT0_31 C584 22U/6.3VS_8 VAXG21 +1.5VSUS
AC34 VCC32 VTT0_32 A11 AL19 VAXG22
C200 2 1*0.047U/10V_4 C564 10U/6.3V_8
C198 2 1*0.047U/10V_4
AC33
AC32
VCC33
VCC34
C574 10U/6.3V_8
AL18
AL16
VAXG23
VAXG24
2A

5
C199 2 1*0.047U/10V_4 AC31 AK21 AJ1 +1.5V_CPU
VCC35 VAXG25 VDDQ1 C383 1U/6.3V_4
AC30 AF10 AK19 AF1 SI modify

- 1.5V RAILS
VCC36 VTT0_33 +1.05V_VTT VAXG26 VDDQ2
AC29 AE10 AK18 AE7 C391 1U/6.3V_4
VCC37 VTT0_34 C176 22U/6.3VS_8 VAXG27 VDDQ3 C390 1U/6.3V_4
AC28 VCC38 VTT0_35 AC10 AK16 VAXG28 VDDQ4 AE4
CPU CORE SUPPLY

C178 22U/6.3VS_8 C389 1U/6.3V_4

POWER
B AC27 VCC39 VTT0_36 AB10 AJ21 VAXG29 VDDQ5 AC1 <36> MAIND 4 B
AC26 Y10 AJ19 AB7 C388 1U/6.3V_4
VCC40 VTT0_37 VAXG30 VDDQ6 C392 22U/6.3VS_8
AA35 VCC41 VTT0_38 W10 AJ18 VAXG31 VDDQ7 AB4
AA34 U10 VTT Rail Values are AJ16 Y1 C371 22U/6.3VS_8 AON7410
DIS UMA

3
2
1
VCC42 VTT0_39 VAXG32 VDDQ8 C6381
AA33 VCC43 VTT0_40 T10 AH21 VAXG33 VDDQ9 W7 2 <12,36> MAINON_G Q33
Auburndal VTT=1.05V
AA32 J12
Ra 0 ohm NA AH19 W4

+
VCC44 VTT0_41 VAXG34 VDDQ10

2
*330U_2.5V_5.0x5.9_ESR10m
POWER

AA31 VCC45 VTT0_42 J11 Clarksfield VTT=1.1V AH18 VAXG35 VDDQ11 U1


AA30 VCC46 VTT0_43 J16 AH16 VAXG36 VDDQ12 T7
AA29 J15 T4 0.1U/10V_4 C616 1 3
VCC47 VTT0_44 VDDQ13 R402 220/F_4
AA28 VCC48 VDDQ14 P1
AA27 N7 0.1U/10V_4 C619

DDR3
VCC49 VDDQ15 Q34 2N7002E
AA26 VCC50 PSI# AN33 H_PSI# <33> VDDQ16 N4 +1.5VSUS
Y35 L1 0.1U/10V_4 C394
VCC51 VDDQ17

FDI
Y34 VCC52 +1.05V_VTT J24 VTT1_45 VDDQ18 H1
Y33 AK35 CPU_VID0 <33> C180 22U/6.3VS_8 J23 0.1U/10V_4 C613
VCC53 VID[0] VTT1_46
Y32 VCC54 VID[1] AK33 CPU_VID1 <33> H25 VTT1_47
Y31 VCC55 VID[2] AK34 CPU_VID2 <33>
Y30 VCC56 VID[3] AL35 CPU_VID3 <33> 8/25 SI for H/W.
Y29 AL33 P10
CPU VIDS

VCC57 VID[4] CPU_VID4 <33> VTT0_59 +1.05V_VTT


Y28 AM33 CPU_VID5 <33> +1.05V_VTT K26 N10 C555 10U/6.3V_8
VCC58 VID[5] VTT1_48 VTT0_60

PEG & DMI


Y27 AM35 CPU_VID6 <33> C72 22U/6.3VS_8 J27 L10 C563 10U/6.3V_8
VCC59 VID[6] C31 22U/6.3VS_8 VTT1_49 VTT0_61 C541 22U/6.3VS_8
Y26 VCC60 PROC_DPRSLPVR AM34 DPRSLPVR <33> J26 VTT1_50 VTT0_62 K10
V35 C30 22U/6.3VS_8 J25 J22 C540 22U/6.3VS_8

1.1V
VCC61 C181 22U/6.3VS_8 VTT1_51 VTT1_63 R394 *0_8/S
V34 VCC62 H27 VTT1_52 VTT1_64 J20 +1.5V_CPU +1.5V
V33 VCC63 G28 VTT1_53 VTT1_65 J18
V32 VCC64 VTT_SELECT G15 H_VTTVID1 <32> G27 VTT1_54 VTT1_66 H21 40mile routing
V31 VCC65 G26 VTT1_55 VTT1_67 H20
V30 VCC66 H_VTTVID1=Low, 1.1V F26 VTT1_56 VTT1_68 H19
V29 VCC67 E26 VTT1_57
V28 H_VTTVID1=High, 1.05V E25
C VCC68 VTT1_58 C
V27 L26 +1.8V

1.8V
VCC69 VCCPLL1 C177 22U/6.3VS_8
V26 VCC70 VCCPLL2 L27
U35 M26 C338 4.7U/6.3V_6
VCC71 VCCPLL3 C183 2.2U/6.3V_6
U34 VCC72
U33 AN35 C341 1U/6.3V_4
SENSE LINES

VCC73 ISENSE I_MON <33>


U32 IC,AUB_CFD_rPGA,R1P0 C536 1U/6.3V_4
VCC74
U31 VCC75 VTT_SENSE B15 VTT_SENSE <32>
U30 VCC76 VSS_SENSE_VTT A15 VSS_SENSE_VTT <32>
U29 VCC77
U28 CPU_VID0 R354 1K_4 +1.05V_VTT
VCC78 R346 100_4 R352 *1K_4
U27 VCC79 +VCORE
U26 AJ34 VCCSENSE <33> CPU_VID1 R351 1K_4
VCC80 VCC_SENSE +VCORE +1.5VSUS R348 *1K_4
R35 VCC81 VSS_SENSE AJ35 VSSSENSE <33> 0510 add for WiMAX
R34 R349 100_4 CPU_VID2 R353 1K_4
VCC82 R355 *1K_4
R33 VCC83
R32 CPU_VID3 R356 *1K_4
VCC84 R361 1K_4
R31 VCC85
R30 CPU_VID4 R362 *1K_4
VCC86 R366 1K_4
R29 VCC87
R28 CPU_VID5 R381 1K_4
VCC88
C23

C39

C24

C25

C22

C38

C74

C70

C80

C54

C94

C64

C52

C59
R376 *1K_4
C511

C292

C514

C512

*2.2U/6.3V_6 C223

*2.2U/6.3V_6 C142

*2.2U/6.3V_6 C149

*2.2U/6.3V_6 C109

*2.2U/6.3V_6 C175

*2.2U/6.3V_6 C128

C235

C103

C138

C118

C252

C278

C224

C245

C193

C129

C186

C261
R27 VCC89
R26 CPU_VID6 R367 *1K_4
VCC90 R373 1K_4
P35 VCC91

*2.2U/6.3V_6

*2.2U/6.3V_6

*2.2U/6.3V_6

*2.2U/6.3V_6
P34 DPRSLPVR R374 1K_4

*15P/50V_4

*15P/50V_4

*15P/50V_4

*15P/50V_4

*15P/50V_4

*15P/50V_4
*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4

*3.3P/50V_4
VCC92 R371 *1K_4
P33
*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

VCC93 H_PSI# R382 *1K_4


P32 VCC94
P31 R377 1K_4
VCC95
P30 VCC96
P29 VCC97
D P28 VCC98 HFM_VID : Max 1.4V D
P27 VCC99
P26 LFM_VID : Min 0.65V
VCC100
IC,AUB_CFD_rPGA,R1P0

352-(&75
4XDQWD&RPSXWHU,QF
<33> +VCORE
<3,10,11,29,32,33,38> +1.05V_VTT
<3,12,13,34,35,36> +1.5VSUS Size Document Number Rev
Custom 1A
<11,32> +1.8V PROCESSER 3/4(POWER)
Date: Sunday, September 19, 2010 Sheet 5 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

AUBURNDALE/CLARKSFIELD PROCESSOR (GND)


U15H U15I
AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)
U15E
06
K27 VSS161
AT20 AE34 K9 DDR_VREF_DQ0 J17 AT2
VSS1 VSS81 VSS162 T1 SA_DIMM_VREF RSVD_NCTF_41
AT17 AE33 K6 DDR_VREF_DQ1 H17 AT3
VSS2 VSS82 VSS163 T2 SB_DIMM_VREF RSVD_NCTF_42
AR31 VSS3 VSS83 AE32 K3 VSS164 RSVD_NCTF_43 AR1
A AR28 AE31 J32 CFG0 AM30 AL28 A
VSS4 VSS84 VSS165 CFG[0] RSVD45
AR26 VSS5 VSS85 AE30 J30 VSS166 AM28 CFG[1] RSVD46 AL29
AR24 VSS6 VSS86 AE29 J21 VSS167 AP31 CFG[2] RSVD47 AP30
AR23 AE28 J19 CFG3 AL32 AP32
VSS7 VSS87 VSS168 CFG4 CFG[3] RSVD48
AR20 VSS8 VSS88 AE27 H35 VSS169 AL30 CFG[4] RSVD49 AL27
AR17 VSS9 VSS89 AE26 H32 VSS170 AM31 CFG[5] RSVD50 AT31
AR15 VSS10 VSS90 AE6 H28 VSS171 AN29 CFG[6]
AR12 AD10 H26 CFG7 AM32 AT32
VSS11 VSS91 VSS172 CFG[7] RSVD51
AR9 VSS12 VSS92 AC8 H24 VSS173 AK32 CFG[8] RSVD52 AP33
AR6 VSS13 VSS93 AC4 H22 VSS174 AK31 CFG[9] RSVD53 AR33
AR3 VSS14 VSS94 AC2 H18 VSS175 AK28 CFG[10] RSVD_NCTF_54 AT33
AP20 VSS15 VSS95 AB35 H15 VSS176 AJ28 CFG[11] RSVD_NCTF_55 AT34
AP17 VSS16 VSS96 AB34 H13 VSS177 AN30 CFG[12] RSVD_NCTF_56 AP35
AP13 VSS17 VSS97 AB33 H11 VSS178 AN32 CFG[13] RSVD_NCTF_57 AR35
AP10 VSS18 VSS98 AB32 H8 VSS179 AJ32 CFG[14] RSVD58 AR32
AP7 VSS19 VSS99 AB31 H5 VSS180 AJ29 CFG[15] RSVD_TP_59 E15
AP4 VSS20 VSS100 AB30 H2 VSS181 AJ30 CFG[16] RSVD_TP_60 F15
AP2 VSS21 VSS101 AB29 G34 VSS182 AK30 CFG[17]
AN34 VSS22 VSS102 AB28 G31 VSS183 H16 RSVD_TP_86 KEY A2
AN31 VSS23 VSS103 AB27 G20 VSS184 RSVD62 D15
AN23 VSS24 VSS104 AB26 G9 VSS185 AP25 RSVD1 RSVD63 C15
AN20 VSS25 VSS105 AB6 G6 VSS186 AL25 RSVD2 RSVD64 AJ15 RSVD64_R R121 *0_4
AN17 AA10 G3 AL24 AH15 RSVD65_R R125 *0_4

RESERVED
VSS26 VSS106 VSS187 RSVD3 RSVD65
AM29 VSS27 VSS107 Y8 F30 VSS188 AL22 RSVD4 RSVD_TP_66 AA5
AM27 VSS28 VSS108 Y4 F27 VSS189 AJ33 RSVD5 RSVD_TP_67 AA4
AM25 VSS29 VSS109 Y2 F25 VSS190 AG9 RSVD6 RSVD_TP_68 R8
AM20 VSS30 VSS110 W35 F22 VSS191 M27 RSVD7 RSVD_TP_69 AD3
AM17 VSS31 VSS111 W34 F19 VSS192 L28 RSVD8 RSVD_TP_70 AD2
AM14 VSS32 VSS112 W33 F16 VSS193
B AM11 VSS33 VSS113 W32 E35 VSS194 G25 RSVD11 RSVD_TP_71 AA2 B
AM8 VSS34 VSS114 W31 E32 VSS195 G17 RSVD12 RSVD_TP_72 AA1
AM5 VSS35 VSS115 W30 E29 VSS196 E31 RSVD13 RSVD_TP_73 R9
AM2 VSS36 VSS116 W29 E24 VSS197 E30 RSVD14 RSVD_TP_74 AG7
AL34 W28 E21 B19 AE3
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E18
E13
VSS198
VSS199
VSS200
VSS R59 *0_4 TP_RSVD17_R
A19
A20
RSVD15
RSVD16
RSVD17
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
V4
V5
AL20 W6 E11 R63 *0_4 TP_RSVD18_R B20 N2
VSS40 VSS120 VSS201 RSVD18 RSVD_TP_78
AL17 VSS41 VSS121 V10 E8 VSS202 U9 RSVD19 RSVD_TP_79 AD5
AL12 VSS42 VSS122 U8 E5 VSS203 T9 RSVD20 RSVD_TP_80 AD7
AL9 VSS43 VSS123 U4 E2 VSS204
AL6 VSS44 VSS124 U2 D33 VSS205 AC9 RSVD21 RSVD_TP_81 W3
AL3 VSS45 VSS125 T35 D30 VSS206 AB9 RSVD22 RSVD_TP_82 W2
AK29 VSS46 VSS126 T34 D26 VSS207 C1 RSVD_NCTF_23 RSVD_TP_83 N3
AK27 VSS47 VSS127 T33 D9 VSS208 A3 RSVD_NCTF_24 RSVD_TP_84 AE5
AK25 VSS48 VSS128 T32 D6 VSS209 J29 RSVD26 RSVD_TP_85 AD9
AK20 VSS49 VSS129 T31 D3 VSS210 J28 RSVD27
AK17 VSS50 VSS130 T30 C34 VSS211 A34 RSVD_NCTF_28
AJ31 VSS51 VSS131 T29 C32 VSS212 A33 RSVD_NCTF_29
AJ23 VSS52 VSS132 T28 C29 VSS213 C35 RSVD_NCTF_30 VSS AP34
AJ20 VSS53 VSS133 T27 C28 VSS214
AJ17 VSS54 VSS134 T26 C24 VSS215 B35 RSVD_NCTF_31
AJ14 VSS55 VSS135 T6 C22 VSS216 AJ13 RSVD32
AJ11 VSS56 VSS136 R10 C20 VSS217 AJ12 RSVD33
AJ8 VSS57 VSS137 P8 C19 VSS218 AH25 RSVD34
AJ5 VSS58 VSS138 P4 C16 VSS219 AK26 RSVD35
AJ2 VSS59 VSS139 P2 B31 VSS220 AL26 RSVD36
AH35 VSS60 VSS140 N35 B25 VSS221 AR2 RSVD_NCTF_37
AH34 VSS61 VSS141 N34 B21 VSS222 AJ26 RSVD38
C AH33 VSS62 VSS142 N33 B18 VSS223 AJ27 RSVD39 C
AH32 VSS63 VSS143 N32 B17 VSS224 AP1 RSVD_NCTF_40
AH31 VSS64 VSS144 N31 B13 VSS225
AH30 N30 B11 IC,AUB_CFD_rPGA,R1P0
VSS65 VSS145 VSS226
AH29 VSS66 VSS146 N29 B8 VSS227
AH28 VSS67 VSS147 N28 B6 VSS228
AH27 VSS68 VSS148 N27 B4 VSS229
AH26 VSS69 VSS149 N26 A29 VSS230
AH20 VSS70 VSS150 N6 A27 VSS231
AH17 VSS71 VSS151 M10 A23 VSS232
AH13 VSS72 VSS152 L35 A9 VSS233
AH9 VSS73 VSS153 L32
AH6 VSS74 VSS154 L29 AT35 VSS_NCTF1
AH3 VSS75 VSS155 L8 AT1 VSS_NCTF2
AG10 L5 AR34 For Discrete only
NCTF

VSS76 VSS156 VSS_NCTF3


AF8 VSS77 VSS157 L2 B34 VSS_NCTF4
AF4 VSS78 VSS158 K34 B2 VSS_NCTF5
AF2 VSS79 VSS159 K33 B1 VSS_NCTF6
AE35 VSS80 VSS160 K30 A35 VSS_NCTF7 CFG0 R136 3.01K/F_4
IC,AUB_CFD_rPGA,R1P0 CFG3 R134 *3.01K/F_4
IC,AUB_CFD_rPGA,R1P0 CFG4 R133 *3.01K/F_4
CFG7 R135 *3.01K/F_4

1 0
CFG[ 1:0 ] - PCI_Epress Configuration Select
D CFG4 Enabled; An external Display port * 11= 1 x 16 PEG D
(Display Port Disabled; No Physical Display Port device is connected to the Embedded * 10= 2 x 8 PEG
Presence) attached to Embedded Diplay Port Display port
The Clarkfield processor's PCI Express interface may
not meet PCI Express 2.0 jitter specifications. Intel CFG0
recommends placing a 3.01K +/- 5% pull down resistor to (PCI-Epress Single PEG Bifurcation enabled
352-(&75
VSS on CFG[7] pin for both rPGA and BGA components.
This pull down resistor should be removed when this
Configuration Select) 4XDQWD&RPSXWHU,QF
issue is fixed. CFG3
Normal Operation Lane Numbers Reversed Size Document Number Rev
(PCI-Epress Static Custom
PROCESSER 4/4 (GND) 1A
Lane Reversal) 15 -> 0 , 14 -> 1
Date: Sunday, September 19, 2010 Sheet 6 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

INTVRMEN - Integrated SUS 1.1V VRM Enable


High - Enable Internal VRs
07
C663 18P/50V_4 UMA CRT,LVDS&HDMI signals
IBEX PEAK-M (HDA,JTAG,SATA) IBEX PEAK-M (LVDS,DDI)
2
1
Y4 R444 U24D
A A
32.768KHZ 10M_4 U24A
<20> LVDS_BLON T48
L_BKLTEN Ibex-M SDVO_TVCLKINN
BJ46
<20> DISP_ON T47 4 OF 10 BG46
3
4 L_VDD_EN SDVO_TVCLKINP
RTC_X1 B13 Ibex-M D33
RTCX1 FWH0 / LAD0 LAD0 <29,30>
C665 18P/50V_4 RTC_X2 D13 1 OF 10 B33 <20> DPST_PWM Y48 BJ48
RTCX2 FWH1 / LAD1 LAD1 <29,30> L_BKLTCTL SDVO_STALLN
C32 BG48
LPC FWH2 / LAD2
FWH3 / LAD3
A32
LAD2
LAD3
<29,30>
<29,30> <20> EDIDCLK AB48
L_DDC_CLK
SDVO_STALLP
RTC_RST# C14 C34 <20> EDIDDATA Y45 BF45
RTCRST# FWH4 / LFRAME# LFRAME# <29,30> L_DDC_DATA SDVO_INTN
A34 SDVO BH45
SRTC_RST# LDRQ0# R230 10K_4 R266 10K_4 L_CTRL_CLK SDVO_INTP
D17 F34 AB46
SRTCRST# RTC (+3V) LDRQ1# / GPIO23
SERIRQ
AB9
+3V
SERIRQ <29> +3V R269 10K_4 L_CTRL_DATA V48
L_CTRL_CLK
L_CTRL_DATA SDVO_CTRLCLK
T51 DPB_CTRL_CLK
SM_INTRUDER# A16 T53 DPB_CTRL_DATA
INTRUDER# R259 2.37K/F_4 LVDS_IBG SDVO_CTRLDATA
SATA0RXN AK7 SATA_RXN0 <23> HDD AP39 LVD_IBG
+RTC_CELL R445 330K_6 PCH_INVRMEN A14 AK6 SATA_RXP0 <23> LVDS_VBG AP41 BG44 TP16
INTVRMEN SATA0RXP TP7 LVD_VBG DDPB_AUXN TP15
AK11 BJ44

DISPLAY PORT B
SATA0TXN SATA_TXN0 <23> DDPB_AUXP
AK9 SATA_TXP0 <23> AT43 AU38 DPB_HPD_Q
SATA0TXP LVD_VREFH DDPB_HPD
ACZ_BCLK A30 AH6
HDD0 (SATA3 6.0Gb/s) AT42 LVD_VREFL DPB_LANE0_N
ACZ_SYNC D29
HDA_BCLK SATA1RXN
AH5
SATA_RXN4 <23> ODD DDPB_0N BD42
DPB_LANE0_P
HDA_SYNC SATA1RXP SATA_RXP4 <23> LVDS--A DDPB_0P BC42

Digital Display Interface


<10,25> ACZ_SPKR P1 AH9 SATA_TXN4 <23> <20> TXLCLKOUT- AV53 BJ42 DPB_LANE1_N
ACZ_RST# SPKR SATA1TXN LVDSA_CLK# DDPB_1N DPB_LANE1_P
C30 HDA_RST# SATA1TXP AH8 SATA_TXP4 <23> <20> TXLCLKOUT+ AV51 LVDSA_CLK DDPB_1P BG42
<25> ACZ_SDIN0 G30 BB40 DPB_LANE2_N
HDA_SDIN0 DDPB_2N DPB_LANE2_P
F30 AF11 BB47 BA40
E32
HDA_SDIN1
HDA_SDIN2
IHDA SATA2RXN
SATA2RXP AF9
<20>
<20>
TXLOUT0-
TXLOUT1- BA52
LVDSA_DATA#0
LVDSA_DATA#1
DDPB_2P
DDPB_3N AW38 DPB_LANE3_N
F32 AF7 <20> TXLOUT2- AY48 BA38 DPB_LANE3_P
ACZ_SDOUT HDA_SDIN3 SATA2TXN LVDSA_DATA#2 DDPB_3P
B29 HDA_SDO SATA2TXP AF6 AV47 LVDSA_DATA#3
<10,29> GPIO33_E R249 *0_4 PCH_GPIO33_R H32 Y49
J30
HDA_DOCK_EN# / GPIO33 (+3V) AH3 BB48
DDPC_CTRLCLK
AB49
HDA_DOCK_RST# / GPIO13 (+3V_S5) SATA3RXN <20> TXLOUT0+ LVDSA_DATA0 DDPC_CTRLDATA
AH1 BA50
SATA SATA3RXP

DISPLAY PORT C
<20> TXLOUT1+ LVDSA_DATA1
SATA3TXN AF3 <20> TXLOUT2+ AY49 LVDSA_DATA2 DDPC_AUXN BE44
SATA3TXP AF1 AV48 LVDSA_DATA3 DDPC_AUXP BD44
PCH_JTAG_TCK M3 AV40
TP12 JTAG_TCK DDPC_HPD
SATA4RXN AD9 LVDS--B
PCH_JTAG_TMS K3 AD8 <20> TXUCLKOUT- AP48 BE40
TP10 JTAG_TMS SATA4RXP LVDSB_CLK# DDPC_0N
B SATA4TXN AD6 <20> TXUCLKOUT+ AP47 LVDSB_CLK DDPC_0P BD40 B
PCH_JTAG_TDI K1 AD5 BF41
TP9 JTAG_TDI JTAG SATA4TXP
<20> TXUOUT0- AY53 LVDSB_DATA#0
DDPC_1N
DDPC_1P BH41
PCH_JTAG_TDO J2 AD3 <20> TXUOUT1- AT49 BD38
TP8 JTAG_TDO SATA5RXN LVDSB_DATA#1 DDPC_2N
SATA5RXP AD1 <20> TXUOUT2- AU52 LVDSB_DATA#2 DDPC_2P BC38
PCH_JTAG_RST# J4 AB3 <20> TXUOUT0+ AT53 BB36
TP1 TRST# SATA5TXN LVDSB_DATA#3 DDPC_3N
SATA5TXP AB1 <20> TXUOUT1+ DDPC_3P BA36
must add test point. <20> TXUOUT2+ AY51 LVDSB_DATA0
AT48 U50
SPI_CLK_R LVDSB_DATA1 DDPD_CTRLCLK
BA2 AF16 AU50 U52
SPI_CLK SATAICOMPO LVDSB_DATA2 DDPD_CTRLDATA
AT51

DISPLAY PORT D
<22> CRT_B LVDSB_DATA3
SPI_CS0#_R AV3 AF15 SATA_COMP R237 37.4/F_4 +1.05V R455 150/F_4 BC46
SPI_CS0# SATAICOMPI DDPD_AUXN
<22> CRT_G AA52 BD46
SPI_CS1# SATA_LED# R457 150/F_4 CRT_BLUE DDPD_AUXP
AY3 T3 AB53 AT38
TP13 SPI_CS1# SPI SATALED# SATA_LED# <28>
<22> CRT_R AD53
CRT_GREEN
CRT_RED
DDPD_HPD
R456 150/F_4
SPI_SI_R AY1 V51
CRT DDPD_0N
BJ40
BG40
SPI_MOSI <22> DDCCLK CRT_DDC_CLK DDPD_0P
Y9 SATA_DET0# <22> DDCDATA V53 BJ38
SPI_SO AV1
(+3V) SATA0GP / GPIO21
V1 SATA_DET1# R409 *0_4 CRT_DDC_DATA DDPD_1N
BG38
SPI_MISO (+3V_S5) SATA1GP / GPIO19 ODD_PRSNT# <23> DDPD_1P
<22> HSYNC_COM Y53 BF37
IbexPeak-M_Rev1_0 CRT_HSYNC DDPD_2N
<22> VSYNC_COM Y51 BH37
CRT_VSYNC DDPD_2P
BE36
R272 1K/F_4 DAC_IREF AD48 DDPD_3N
BD36
DAC_IREF DDPD_3P
AB51
CRT_IRTN
IbexPeak-M_Rev1_0
1205 The SATALED# signal is
open-collector and requires a
weak external pull-up (8.2 k
to 10 k ) to +V3.3.
+3VS5
R411 10K_4 SATA_LED#
R223 10K_4 SATA_DET0# R433 51_4 PCH_JTAG_TCK
+3V R410 10K_4 SATA_DET1#
C R415 R413 R416 R192 C
R251 *10K_4 GPIO33_E For ES1 ONLY.NI for ES2.
200_4 20K/F_4
200_4 200_4
+3V PCH_JTAG_RST#
UMA HDMI signals Q18
PCH_JTAG_TDO
PCH_JTAG_TDI
2

*2N7002K PCH_JTAG_TMS
DPB_CTRL_CLK R459 0_4 SDVO_CLK <21>
DPB_CTRL_DATA R458 0_4 SDVO_DATA <21> DPB_HPD_Q 1 3 HDMI_HPD_CON <21> R414 R412 R436 R197
DPB_LANE0_N C474 0.1U/10V_4 IN_D2# <21>
DPB_LANE0_P C478 0.1U/10V_4 IN_D2 <21> For ES1 ONLY.NI for ES2.
DPB_LANE1_N C471 0.1U/10V_4 IN_D1# <21> 100_4 10K_4
DPB_LANE1_P C472 0.1U/10V_4 IN_D1 <21> R287 100_4 100_4
DPB_LANE2_N C480 0.1U/10V_4 IN_D0# <21> 100K_4 R286 0_4
DPB_LANE2_P C482 0.1U/10V_4 IN_D0 <21>
DPB_LANE3_N C465 0.1U/10V_4 IN_CLK# <21> Part
DPB_LANE3_P C467 0.1U/10V_4 IN_CLK <21>
Part Number
Part Description

For AUDIO
<25>
<25>
ACZ_RST#_AUDIO
ACZ_SDOUT_AUDIO
R452
R450
C666
33_4 ACZ_RST#
33_4 ACZ_SDOUT
*10P/50V_4
RTC +RTC_CELL
1mA
4M byte SPI ROM Vender
<25> ACZ_SYNC_AUDIO R451 33_4 ACZ_SYNC Socket DG008000031
C667 *10P/50V_4
+3VPCU RB500V-40 CR1 C438 1U/6.3V_4 EON - EN25F32-100HIP
<25> BIT_CLK_AUDIO R453 33_4 ACZ_BCLK U22
C464 *10P/50V_4 +3VRTC_2 R242 20K/F_4 RTC_RST# +3V 8 1 SPI_CS0#_R AKE39FN0Q00 IC FLASH(8P) EN25F32-100HIP (SOIC)
RB500V-40 CR2 C428 1U/6.3V_4 VDD CE# SPI_CLK_R
D SCK 6 D
5 SPI_SI_R WINBOND - W25Q32BVSSIG
SPI_HOLD# 7 SI SPI_SO
HOLD# SO 2
R241 20K/F_4 SRTC_RST# R422 10K_4 AKE391P0N00 IC FLASH(8P) W25Q32BVSSIG(SOIC)
C429 1U/6.3V_4 C659 0.1U/10V_4 4 3 SPI_WP# R440 10K_4 +3V
VSS WP#
For MDC W25Q32BVSSIG
R243 1M_4 SM_INTRUDER# AKE391P0N00
IC FLASH(8P) W25Q32BVSSIG(SOIC)
352-(&75
CN24
R254 1K_4 +3VRTC_1
4XDQWD&RPSXWHU,QF
1 2

BAT_CONN <2,8,9,11,39> +1.05V


8/25 SI for M/E. <2,3,8,9,10,11,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V
DFWF02MS032 <20,28,29,31,37> +3VPCU Size Document Number Rev
50273-0027N-001-2P-L Custom 1A
PCH 1/5 (SATA,HDA,LPC)
Date: Sunday, September 19, 2010 Sheet 7 of 39
1 2 3 4 5 6 7 8
5 4 3 2 1

IBEX PEAK-M (GND)


AY7
B11
U24I
VSS[159]
VSS[160]
VSS[259]
VSS[260]
H49
H5 IBEX PEAK-M (PCI-E,SMBUS,CLK)
08
B15 VSS[161] VSS[261] J24
B19 K11 U24B
VSS[162] VSS[262] +3VS5
B23 VSS[163] VSS[263] K43
B31 K47 Ibex-M
B35
VSS[164]
VSS[165]
VSS[264]
VSS[265] K7 <30> PCIE_RXN1 PCIE_RXN1 BG30
PERN1 2 OF 10 SMBus
B39 L14 <30> PCIE_RXP1 PCIE_RXP1 BJ30 B9 SMBALERT# 10K_4 R442
D VSS[166] VSS[266] C450 0.1U/10V_4 PCIE_TXN1_C BF29 PERP1 (+3V_S5) SMBALERT# / GPIO11 PCLK_SMB 2.2K_4 R189
D
B43 VSS[167] VSS[267] L18 [WLAN] <30> PCIE_TXN1
C449 0.1U/10V_4 PCIE_TXP1_C BH29 PETN1 SMBCLK H14
PDAT_SMB 2.2K_4 R208
B47 VSS[168] VSS[268] L2 <30> PCIE_TXP1 PETP1 SMBDATA C8
B7 L22 J14 SMBL0ALERT# 10K_4 R238
VSS[169] VSS[269] PCIE_RXN2_LAN
(+3V_S5) SML0ALERT# / GPIO60 SMB_CLK_ME0 2.2K_4 R229
BG12 VSS[170] VSS[270] L32 <27> PCIE_RXN2_LAN AW30 PERN2 SML0CLK C6
BB12 L36 <27> PCIE_RXP2_LAN PCIE_RXP2_LAN BA30 G8 SMB_DATA_ME0 2.2K_4 R212
VSS[171] VSS[271] C458 0.1U/10V_4 PCIE_TXN2_C PERP2 SML0DATA SML1ALERT# 10K_4 R239
BB16 VSS[172] VSS[272] L40 [LAN] <27> PCIE_TXN2_LAN
C459 0.1U/10V_4 PCIE_TXP2_C
BC30 PETN2 (+3V_S5) SML1ALERT# / GPIO74 M14
SMB_CLK_ME1 4.7K_4 R216
BB20 L52 <27> PCIE_TXP2_LAN BD30 E10
BB24
VSS[173] VSS[273]
M12
PETP2 (+3V_S5) SML1CLK / GPIO58
G12 SMB_DATA_ME1 4.7K_4 R227
VSS[174] VSS[274] (+3V_S5) SML1DATA / GPIO75
BB30 VSS[175] VSS[275] M16 <24> PCIE_RXN3_CARD AU30 PERN3
BB34 VSS[176] VSS[276] M20 Cardreader<24> PCIE_RXP3_CARD
C460 0.1U/10V_4
AT30
PCIE_TXN3_CARD_C AU32 PERP3
BB38 VSS[177] VSS[277] N38 <24> PCIE_TXN3_CARD PETN3
BB42 M34 C461 0.1U/10V_4 PCIE_TXP3_CARD_C AV32
BB49
VSS[178] VSS[278]
M38
PEG Clock detect (SG only) <24> PCIE_TXP3_CARD PETP3
T13
VSS[179] VSS[279] CL_CLK1
BB5
BC10
VSS[180] VSS[280] M42
M46
BA32
BB32
PERN4 Controller T11
VSS[181] VSS[281] DGPU_PW ROK_1 <35> PERP4 CL_DATA1
BC14 VSS[182] VSS[282] M49 BD32 PETN4 Link

2
BC18 VSS[183] VSS[283] M5 BE32 PETP4 CL_RST1# T9
BC2 VSS[184] VSS[284] M8
BC22 N24 1 3 PEG_CLKREQ# BF33
VSS[185] VSS[285] PERN5
BC32 VSS[186] VSS[286] P11 BH33 PERP5
BC36 AD15 Q35 5/7: modify BG32
VSS[187] VSS[287] *2N7002E PETN5
BC40 VSS[188] VSS[288] P22 BJ32 PETP5
BC44 VSS[189] VSS[289] P30
PCI-E* PEG
BC52 VSS[190] VSS[290] P32 BA34 PERN6
BH9 VSS[191] VSS[291] P34 AW34 PERP6 H1 PEG_CLKREQ#
BD48 P42 BC34 (+3V_S5)PEG_A_CLKRQ# / GPIO47 AD43
VSS[192] VSS[292] PETN6 CLKOUT_PEG_A_N CLK_PCIE_VGA# <14>
BD49 VSS[193] VSS[293] P45 BD34 PETP6 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA <14>
BD5 P47 +3V AN4
VSS[194] VSS[294] CLKOUT_DMI_N CLK_PCIE_3GPLL# <3>
C BE12 R2 PCIE_CLKREQ_W LAN# R429 10K_4 AT34 AN2 CLK_PCIE_3GPLL <3> C
VSS[195] VSS[295] CLK_PCIE_REQ2# R198 10K_4 PERN7 CLKOUT_DMI_P
BE16 VSS[196] VSS[296] R52 AU34 PERP7
BE20 VSS[197] VSS[297] T12 AU36 PETN7
BE24 T41 +3VS5 AV36 AT1
VSS[198] VSS[298] PETP7 CLKOUT_DP_N / CLKOUT_BCLK1_N DREFSSCLK# <3>
BE30 VSS[199] VSS[299] T46 CLKOUT_DP_P / CLKOUT_BCLK1_P AT3 DREFSSCLK <3>
BE34 T49 PCIE_CLK_REQ0# R231 10K_4 BG34
VSS[200] VSS[300] PCIE_CLKREQ_LAN# R215 10K_4 PERN8
BE38 VSS[201] VSS[301] T5 BJ34 PERP8
BE42 T8 PCIE_CLK_REQ4# R193 10K_4 BG36 AW24 CLK_BUF_PCIE_3GPLL# <2>
VSS[202] VSS[302] PCIE_CLK_REQB#_R R240 10K_4 PETN8 CLKIN_DMI_N
BE46 VSS[203] VSS[303] U30 BJ36 PETP8 CLKIN_DMI_P BA24 CLK_BUF_PCIE_3GPLL <2>
BE48 VSS[204] VSS[304] U31 AK48 CLKOUT_PCIE0N
BE50 U32 PCIE_CLK_REQ5# R217 10K_4 AK47
VSS[205] VSS[305] CLKOUT_PCIE0P
BE6 VSS[206] VSS[306] U34 CLKIN_BCLK_N AP3 CLK_BUF_BCLK_N <2>
BE8 P38 Ra R417 *10K_4 PCIE_CLK_REQ0# P9 AP1 CLK_BUF_BCLK_P <2>
VSS[207] VSS[307] PCIECLKRQ0# / GPIO73(+3V_S5) CLKIN_BCLK_P
BF3 V11 AM43

From CLK BUFFER


VSS[208] VSS[308] <30> CLK_PCIE_W LANN CLKOUT_PCIE1N
BF49 P16 PEG_CLKREQ# Rb R418 10K_4 <30> CLK_PCIE_W LANP AM45
VSS[209] VSS[309] CLKOUT_PCIE1P
BF51 VSS[210] VSS[310] V19 MiniWLAN CLKIN_DOT_96N F18 CLK_BUF_DREFCLK# <2>
BG18 VSS[211] VSS[311] V20 Ra: UMA <30> PCIE_CLKREQ_W LAN# U4 PCIECLKRQ1# / GPIO18 (+3V) CLKIN_DOT_96P E18 CLK_BUF_DREFCLK <2>
BG24 VSS[212] VSS[312] V22 Rb: Muxless
BG4 VSS[213] VSS[313] V30 <24> CLK_PCIE_CARDN AM47 CLKOUT_PCIE2N
BG50 VSS[214] VSS[314] V31 <24> CLK_PCIE_CARDP AM48 CLKOUT_PCIE2P CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_DREFSSCLK# <2>
BH11 VSS[215] VSS[315] V32 CLKIN_SATA_P / CKSSCD_P AH12 CLK_BUF_DREFSSCLK <2>
BH15 VSS[216] VSS[316] V34 <24> CLK_PCIE_REQ2# N4 PCIECLKRQ2# / GPIO20(+3V)
BH19 VSS[217] VSS[317] V35
BH23 VSS[218] VSS[318] V38 <27> CLK_PCIE_LANN AH42 CLKOUT_PCIE3N REFCLK14IN P41 CLK_ICH_14M <2>
BH31 VSS[219] VSS[319] V43 <27> CLK_PCIE_LANP AH41 CLKOUT_PCIE3P
BH35 V45 LAN C473 *5.6P/50V_4
VSS[220] VSS[320] CLK_PCI_FB
BH39 VSS[221] VSS[321] V46 <27> PCIE_CLKREQ_LAN# A8 PCIECLKRQ3# / GPIO25(+3V_S5) CLKIN_PCILOOPBACK J42 CLK_PCI_FB <9>
BH43 VSS[222] VSS[322] V47
BH47 V49 Q36 2N7002E AM51
VSS[223] VSS[323] SMB_CLK_ME1 CLKOUT_PCIE4N
B BH7 VSS[224] VSS[324] V5 3 1 MBCLK2 <13,29> AM53 CLKOUT_PCIE4P XTAL25_IN AH51 XTAL25_IN DIS only B
C12 VSS[225] VSS[325] V7 XTAL25_OUT AH53 XTAL25_OUT
C50 V8 PCIE_CLK_REQ4# M9
VSS[226] VSS[326] PCIECLKRQ4# / GPIO26(+3V_S5)
D51 W2 R446 AF38 XCLK_RCOMP +1.05V
2

VSS[227] VSS[327] XCLK_RCOMP R262 90.9/F_4


E12 VSS[228] VSS[328] W52 2.2K_4
E16 VSS[229] VSS[329] Y11 AJ50 CLKOUT_PCIE5N
E20 Y12 AJ52 T45 CLK_FLEX0 T36
E24
VSS[230] VSS[330]
Y15
CLKOUT_PCIE5P (+3V) CLKOUTFLEX0 / GPIO64 P43 CLK_FLEX1 T35
VSS[231] VSS[331] +3V (+3V_S5) (+3V) CLKOUTFLEX1 / GPIO65
E30 Y19 PCIE_CLK_REQ5# H6 T42 CLK_FLEX2 T34
E34
VSS[232] VSS[332]
Y23
PCIECLKRQ5# / GPIO44 (+3V) CLKOUTFLEX2 / GPIO66 N50 CLK_FLEX3 T37
VSS[233] VSS[333] R448
(+3V) CLKOUTFLEX3 / GPIO67
E38 VSS[234] VSS[334] Y28
E42 VSS[235] VSS[335] Y30 2.2K_4 AK53 CLKOUT_PEG_B_N
2

E46 VSS[236] VSS[336] Y31 AK51 CLKOUT_PEG_B_P Clock Flex


E48 Y32 Q37
VSS[237] VSS[337] SMB_DATA_ME1 3 PCIE_CLK_REQB#_R P13
E6 VSS[238] VSS[338] Y38 1 MBDATA2 <13,29> PEG_B_CLKRQ# / GPIO56(+3V_S5)
E8 VSS[239] VSS[339] Y43
F49 Y46 2N7002E
VSS[240] VSS[340] IbexPeak-M_Rev1_0
F5 VSS[241] VSS[341] P49
G10 VSS[242] VSS[342] Y5
G14 VSS[243] VSS[343] Y6
G18 Y8 +3VS5 UMA only
VSS[244] VSS[344]
G2 VSS[245] VSS[345] P24
G22 T43 Q12 2N7002E
VSS[246] VSS[346] PDAT_SMB XTAL25_IN C668 27P/50V_4
G32 VSS[247] VSS[347] AD51 3 1 CGDAT_SMB <2,12,13>
G36 AT8 U21 C658
VSS[248] VSS[348] *MC74VHC1G08DFT2G
G40 VSS[249] VSS[349] AD47 *0.1U/10V_4

5
G44 Y47 R191 8/25 SI for TXC.
2

VSS[250] VSS[350] PLT_RST-R# R454 Y5


G52 VSS[251] VSS[351] AT12 10K_4 <9> PLT_RST-R# 2
AF39 AM6 4 1M_4 25MHZ
VSS[252] VSS[352] PLTRST# <3,14,24,27,29,30>
A H16 VSS[253] VSS[353] AT13 1 A
H20 AM5 +3V XTAL25_OUT C669 33P/50V_4
VSS[254] VSS[354] R439 R421
H30 AK45
3
VSS[255] VSS[355]
H34 VSS[256] VSS[356] AK39 100K_4 *100K_4
H38 VSS[257] VSS[366] AV14
H42 R190 R423 0_4
352-(&75
VSS[258] 10K_4
2

IbexPeak-M_Rev1_0

PCLK_SMB
Q13
3
2N7002E
1
4XDQWD&RPSXWHU,QF
CGCLK_SMB <2,12,13>

<2,7,9,11,39> +1.05V Size Document Number Rev


Custom 1A
<2,3,7,9,10,11,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V PCH 2/5 (PCIE, SMBUS, CK)
Date: Sunday, September 19, 2010 Sheet 8 of 39
5 4 3 2 1
1 2 3 4 5 6 7 8

IBEX PEAK-M (DMI,FDI,GPIO)


09
U24C
FDI_RXN0 BA18 FDI_TXN0 <3>
BC24 Ibex-M BH17

A
IBEX PEAK-M (PCI,USB,NVRAM) <3>
<3>
<3>
DMI_RXN0
DMI_RXN1
DMI_RXN2
BJ22
AW20
DMI0RXN
DMI1RXN 3 OF 10
FDI_RXN1
FDI_RXN2 BD16
BJ16
FDI_TXN1
FDI_TXN2
FDI_TXN3
<3>
<3>
<3> A
DMI2RXN FDI_RXN3
<3> DMI_RXN3 BJ20 DMI3RXN FDI_RXN4 BA16 FDI_TXN4 <3>
U24E BE14 FDI_TXN5 <3>
FDI_RXN5
H40 AD0 Ibex-M NV_CE#0 AY9 <3> DMI_RXP0 BD24 DMI0RXP FDI_RXN6 BA14 FDI_TXN6 <3>
+3V N34 5 OF 10 BD1 <3> DMI_RXP1 BG22 BC12 FDI_TXN7 <3>
RP5 AD1 NV_CE#1 DMI1RXP FDI_RXN7
C44 AD2 NV_CE#2 AP15 <3> DMI_RXP2 BA20 DMI2RXP
5 6 PCI_PIRQD# A38 BD8 <3> DMI_RXP3 BG20 BB18 FDI_TXP0 <3>
PCI_STOP# REQ1# AD3 NV_CE#3 DMI3RXP FDI_RXP0
4 7 C36 AD4 FDI_RXP1 BF17 FDI_TXP1 <3>
PCI_IRDY# 3 8 PCI_SERR# J34 AV9 <3> DMI_TXN0 BE22 BC16 FDI_TXP2 <3>
PCI_PIRQA# PCI_FRAME# AD5 NV_DQS0 DMI0TXN FDI_RXP2
2 9 A40 BG8 BF21 BG16
PCI_PIRQC# 1 10 +3V D45
AD6
AD7 NVRAM NV_DQS1 <3>
<3>
DMI_TXN1
DMI_TXN2 BD20
DMI1TXN
DMI2TXN
DMI FDI FDI_RXP3
FDI_RXP4 AW16
FDI_TXP3
FDI_TXP4
<3>
<3>
E36 AD8 NV_DQ0 / NV_IO0 AP7 <3> DMI_TXN3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_TXP5 <3>
10P8R-8.2K H48 AP6 BB14 FDI_TXP6 <3>
AD9 NV_DQ1 / NV_IO1 FDI_RXP6
E40 AD10 NV_DQ2 / NV_IO2 AT6 <3> DMI_TXP0 BD22 DMI0TXP FDI_RXP7 BD12 FDI_TXP7 <3>
+3VS5 C40 AT9 BH21
AD11 NV_DQ3 / NV_IO3 <3> DMI_TXP1 DMI1TXP
RP2 M48 BB1 <3> DMI_TXP2 BC20
USB_OC0# AD12 NV_DQ4 / NV_IO4 DMI2TXP
5 6 M45 AD13 NV_DQ5 / NV_IO5 AV6 <3> DMI_TXP3 BD18 DMI3TXP FDI_INT BJ14 FDI_INT <3>
USB_OC4# 4 7 USB_OC1# F53 BB3 BF13 FDI_FSYNC0 <3>
USB_OC5# USB_OC2# AD14 NV_DQ6 / NV_IO6 FDI_FSYNC0
3 8 M40 AD15 NV_DQ7 / NV_IO7 BA4 FDI_FSYNC1 BH13 FDI_FSYNC1 <3>
USB_OC6# 2 9 USB_OC3# M43 BE4 BH25 BJ12 FDI_LSYNC0 <3>
USB_OC7# AD16 NV_DQ8 / NV_IO8 DMI_COMP DMI_ZCOMP FDI_LSYNC0
1 10 +3VS5 J36 AD17 NV_DQ9 / NV_IO9 BB6 +1.05V BF25 DMI_IRCOMP FDI_LSYNC1 BG14 FDI_LSYNC1 <3>
K48 BD6 R247 49.9/F_4
10P8R-8.2K AD18 NV_DQ10 / NV_IO10
F40 AD19 NV_DQ11 / NV_IO11 BB7
+3V
C42
K46
AD20 NV_DQ12 / NV_IO12 BC8
BJ8 T6
System Power Management P12
AD21 NV_DQ13 / NV_IO13 <3> XDP_DBRESET# SYS_RESET# SLP_S3# SUSB# <29>
RP6 M51 BJ6 M6 H7 SUSC# <29>
PCI_PLOCK# AD22 NV_DQ14 / NV_IO14 R200 0_4 SYS_PWROK SLP_S4#
5 6 J52 AD23 NV_DQ15 / NV_IO15 BG6 <33> IMVP_PW RGD B17 PWROK
REQ3# 4 7 PCI_PERR# K51 <17,29> EC_PW ROK R199 *0_4 PCH_PW ROK K5 K8 SLP_M# TP4
PCI_DEVSEL# 3 REQ0# AD24 MEPWROK SLP_M#
8 L34 AD25 NV_ALE BD3 TP23 N2
B PCI_TRDY# 2 9 PCI_PIRQB# F42 AY6 RSV_ICH_LAN_RST# A10 B
INTH# AD26 NV_CLE LAN_RST#
1 10 +3V J40 <3> PM_DRAM_PW RGD D9 M1 SUS_PW R_ACK <29>
G46
AD27
C16
DRAMPWROK (+3V_S5) SUS_PWR_DN_ACK / GPIO30 P7 AC_PRESENT_R
AD28 <29> RSMRST# RSMRST# (+3V_S5) ACPRESENT / GPIO31
10P8R-8.2K F44 AU2 Y1 CLKRUN# <29>
M47
AD29 NV_RCOMP R194 *0_4/S P5
(+3V) CLKRUN# / GPIO32 P8
H36
AD30
AD31 PCI NV_RB# AV7
<29> DNBSW ON# PWRBTN# (+3V_S5) SUS_STAT# / GPIO61
(+3V_S5) SUSCLK / GPIO62 F3
E4
PCH_SUSCLK_L
SLP_S5#
PM_RI#
(+3V_S5) SLP_S5# / GPIO63 PM_BATLOW #
SLP_S5 <29>
J50 AY8 F14 A6
G42
C/BE0# NV_WR#0_RE#
AY5 J12
RI# (+3V_S5) BATLOW# / GPIO72
C/BE1# NV_WR#1_RE# <27,30> PCIE_W AKE# WAKE#
H47 C/BE2# <3> PM_SYNC BJ10 PMSYNCH SLP_LAN# / GPIO29 F6
G34 AV11 (+3V_S5)
C/BE3# NV_WE#_CK0
NV_WE#_CK1 BF5
PCI_PIRQA# G38 IbexPeak-M_Rev1_0
PCI_PIRQB# PIRQA#
H51 PIRQB#
PCI_PIRQC# B37 H18
PCI_PIRQD# A44
PIRQC# USBP0N
J18
USBP0- >&d^/h^
<26>
PIRQD# USBP0P USBP0+ <26>
A18
REQ0# F51
USBP1N
C18
USBP1-
USBP1+
>&d^/h^
<26>
<26>
REQ1# REQ0# USBP1P PCH_SUSCLK_L R438 0_4
A46 REQ1# / GPIO50 (+5V) USBP2N N20 PCH_SUSCLK <29>
REQ2# B45 P20
REQ3# REQ2# / GPIO52 (+5V) USBP2P
M53 REQ3# / GPIO54 (+5V) USBP3N J20
USBP3P L20
F48 F20
<10>
<10>
GNT0#
GNT1# K45
GNT0# USBP4N
G20
USBP4-
USBP4+
t
<20>
<20>
+3V
GNT1# / GPIO51(+3V) USBP4P
<30> BT_COMBO_EN# F36 GNT2# / GPIO53(+3V) USBP5N A20
<10> GNT3# H53 C20 +3V REQ2# R268 8.2K_4
GNT3# / GPIO55(+3V) USBP5P PIRQE# R267 8.2K_4
USBP6N M22
PIRQE# B41 N22 CLKRUN# R425 8.2K_4 PIRQF# R461 8.2K_4
PIRQF# PIRQE# / GPIO2 (+5V) USBP6P XDP_DBRESET# R220 1K_4 PIRQG# R257 8.2K_4
K53 PIRQF# / GPIO3 (+5V) USBP7N B21 SI Modify
C
PIRQG# A36 D21 C
INTH# PIRQG# / GPIO4 (+5V) USBP7P
A48 PIRQH# / GPIO5 (+5V) USBP8N H22 USBP8- <26>
8/25 SI for H/W.
K6
USBP8P J22
E22
USBP8+ ydh^ Change Port2 to Port4
<26>
PCIRST# USBP9N
F22
Change Port4 to Port12
PCI_SERR# USBP9P change Port5 to Port13 +3VS5
E44 A22
<29> PCI_SERR#
PCI_PERR# E50
SERR#
PERR# USB USBP10N
USBP10P C22
G24
USBP10-
USBP10+
<30>
<30> t>E RSMRST# R236 10K_4 PM_RI# R233 10K_4
USBP11N RSV_ICH_LAN_RST# R443 10K_4 PM_BATLOW # R441 10K_4
USBP11P H24
PCI_IRDY# A42 L24 PCH_PW ROK R447 10K_4 PCIE_W AKE# R211 1K_4
IRDY# USBP12N
H44 M24
PCI_DEVSEL# F46
PAR USBP12P
A24
Z
DEVSEL# USBP13N USBP2- <26>
PCI_FRAME# C46 C24 SUS_PW R_ACK R209 10K_4
FRAME# USBP13P USBP2+ <26>  BT_COMBO_EN# R260 *1K_4 AC_PRESENT_R R210 10K_4
PCI_PLOCK# D49 PLOCK#
USBRBIAS# B25 USB_BIAS R449 22.6/F_4
PCI_STOP# D41
PCI_TRDY# STOP#
C48 TRDY# USBRBIAS D25

TP2 PME# M7 PME# USB_OC0#


N16
PLT_RST-R# D5
(+3V_S5)OC0# / GPIO59 J16 USB_OC1#
<8> PLT_RST-R# PLTRST# (+3V_S5)OC1# / GPIO40 F16 USB_OC2#
R460 33_4 CLK_33M_DEBUG_R N52 (+3V_S5)OC2# / GPIO41 L16 USB_OC3#
<30> CLK_33M_DEBUG CLKOUT_PCI0 (+3V_S5)OC3# / GPIO42
<29> CLK_33M_KBC R462 33_4 CLK_33M_KBC_R P53 E14 USB_OC4# AC_PRESENT_R R201 *0_4 AC_PRESENT <29>
CLKOUT_PCI1 (+3V_S5)OC4# / GPIO43 USB_OC5#
P46 CLKOUT_PCI2 G16
CLK_PCI_FB_C P51 (+3V_S5)OC5# / GPIO9 F12 USB_OC6#
<8> CLK_PCI_FB CLKOUT_PCI3 (+3V_S5)OC6# / GPIO10
R274 22_4 P48 T15 USB_OC7#
CLKOUT_PCI4 (+3V_S5)OC7# / GPIO14
D D
IbexPeak-M_Rev1_0

CLK_33M_KBC
352-(&75
C673
4XDQWD&RPSXWHU,QF
*5.6P/50V_4 <2,7,8,11,39> +1.05V
<2,3,7,8,10,11,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V Size Document Number Rev
Custom 1A
<3,7,8,10,11,26,31,32,34,35,36,38> +3VS5 PCH 3/5 (PCI,ONFI,USB,DMI)
Date: Sunday, September 19, 2010 Sheet 9 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

IBEX PEAK-M (GND)


BMBUSY#
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
Y3
U24F

BMBUSY# / GPIO0 (+3V)


Ibex-M
6 OF 10 CLKOUT_PCIE6N
CLKOUT_PCIE6P
AH45
AH46
AB16
AA19
U24H

VSS[0]
VSS[1]
VSS[80]
VSS[81]
AK30
AK31 <9> GNT3# R464 *10K_4
10
<29> SIO_EXT_SMI# C38 TACH1 / GPIO1 AA20 VSS[2] VSS[82] AK32
(+3V) AA22 AK34
VSS[3] VSS[83]
<29> SIO_EXT_SCI# D37 TACH2 / GPIO6 (+3V) AM19 VSS[4] VSS[84] AK35 A16 swap override Strap/Top-Block
CLKOUT_PCIE7N AF48 AA24 VSS[5] VSS[85] AK38 Swap Override jumper
J32 AF47 AA26 AK43
<26,30> BT_OFF# TACH3 / GPIO7 (+3V) GPIO CLKOUT_PCIE7P
AA28
VSS[6]
VSS[7]
VSS[86]
VSS[87] AK46
TP3 PCH_GPIO8 F10 AA30 AK49 Low = A16 swap
GPIO8 (+3V_S5) MISC AA31
VSS[8]
VSS[9]
VSS[88]
VSS[89] AK5 override/Top-Block
LAN_DISABLE_R# K9 U2 AA32 AK8 GNT3#
LAN_PHY_PWR_CTRL / GPIO12 (+3V_S5) A20GATE EC_A20GATE <29> VSS[10] VSS[90] Swap Override enabled
A AB11 VSS[11] VSS[91] AL2 High = Default A
<30> RF_OFF# T7 GPIO15 (+3V_S5) AB15 VSS[12] VSS[92] AL52
AB23 VSS[13] VSS[93] AM11
CLKOUT_BCLK0_N/CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# <3> AB30 VSS[14] VSS[94] BB44
AB31 VSS[15] VSS[95] AD24
2,17,29,34,35> DGPU_PWROK R264 0_4 PCH_GPIO17 F38 AM1 CLK_CPU_BCLK <3> AB32 AM20
TACH0 / GPIO17(+3V) CLKOUT_BCLK0_P/CLKOUT_PCIE8P VSS[16] VSS[96] SV_SET_UP R219 10K_4
AB39 VSS[17] VSS[97] AM22 +3V
UMA remove BIOS_REC Y7 BG10 PCH_PECI_R H_PECI <3> AB43 AM24
SCLOCK / GPIO22(+3V) PECI VSS[18] VSS[98]
GPIO27 left NC for AB47 VSS[19] VSS[99] AM26
internal VR. TP6 GPIO27 AB12 T1 EC_RCIN# <29> AB5 AM28
GPIO27 (+3V_S5) RCIN# VSS[20] VSS[100]
AB8 BA42
TP_PCH_GPIO28 V13
GPIO28 (+3V_S5)
CPU PROCPWRGD BE10 H_PWRGOOD <3> AC2
VSS[21]
VSS[22]
VSS[101]
VSS[102] AM30 SV_SET_UP 1-X High = Strong (Default)
AC52 VSS[23] VSS[103] AM31
<35> DGPU_PWR_EN R420 0_4 SATA2GP AB7 BD10 PCH_THRMTRIP#_R PM_THRMTRIP# <3,29> AD11 AM32
SATA2GP / GPIO36 (+3V) THRMTRIP# R232 56.2/F_4 VSS[24] VSS[104]
AD12 AM34
SATA3GP VSS[25] VSS[105]
UMA remove AB13
SATA3GP / GPIO37 TP1
BA22 +1.05V_VTT AD16
VSS[26] VSS[106]
AM35
(+3V) AW22 R228 56.2/F_4 AD23 AM38
LCD_BK TP2 VSS[27] VSS[107] GNT0# R271 *1K_4
<20> LCD_BK P3 BB22 AD30 AM39 <9> GNT0#
SDATAOUT0 / GPIO39 (+3V) TP3 VSS[28] VSS[108] GNT1# R463 *1K_4
AY45 AD31 AM42 <9> GNT1#
TP4 VSS[29] VSS[109]
AY46 AD32 AU20
PCIE_CLK_REQ7# TP5 VSS[30] VSS[110]
<3> PCIE_CLK_REQ7# F1 AV43 AD34 AM46
PCIECLKRQ7# / GPIO46 (+3V_S5) TP6 VSS[31] VSS[111]
AV45 AU22 AV22
SV_SET_UP TP7 VSS[32] VSS[112]
AB6 AF13 AD42 AM49
SDATAOUT1 / GPIO48 (+3V) TP8 VSS[33] VSS[113]
TP9
M18 AD46
VSS[34] VSS[114]
AM7 Boot BIOS Strap
<24> GPIO49 R434 *0_4 SATA5GP AA4 N18 AD49 AA50
SATA5GP / GPIO49 (+3V) TP10 VSS[35] VSS[115]
PCI_GNT0# GNT#1 Boot BIOS Location
RSVD TP11
AJ24
AK41
AD7
AE2
VSS[36] VSS[116]
BB10
AN32
TP12 VSS[37] VSS[117] LPC
TP13
AK42 AE4
VSS[38] VSS[118]
AN50 0 0
R258 0_4 PCH_GPIO35
SATACLKREQ# / GPIO35(+3V)
<14> DGPU_HOLD_RST# V6 M32 AF12 AN52
TP14 VSS[39] VSS[119] Reserved (NAND)
TP15
N32 Y13
VSS[40] VSS[120]
AP12 0 1
UMA remove TP16
M30 AH49
VSS[41] VSS[121]
AP42
BOARD_ID0 H10 (+3V_S5) N30 AU4 AP46 1 0 PCI
BOARD_ID1 GPIO24 TP17 VSS[42] VSS[122]
PCIECLKRQ6# / GPIO45 (+3V_S5)
H3 H12 AF35 AP49
BOARD_ID2 TP18 VSS[43] VSS[123] SPI
8/25 SI for H/W. F8
GPIO57 (+3V_S5) TP19
AA23 AP13
VSS[44] VSS[124]
AP5 1 1
BOARD_ID3 M11 (+3V) AB45 AN34 AP8
BOARD_ID4 STP_PCI# / GPIO34 NC_1 VSS[45] VSS[125]
AA2
SATA4GP / GPIO16 (+3V) NC_2
AB38 AF45
VSS[46] VSS[126]
AR2
BOARD_ID5 V3 (+3V) AB42 AF46 AR52
SLOAD / GPIO38 NC_3 VSS[47] VSS[127]
B AB41 AF49 AT11 B
NC_4 VSS[48] VSS[128]
T39 AF5 BA12
NC_5 VSS[49] VSS[129]
P6 AF8 AH48
+3VS5 INIT3_3V# +3V VSS[50] VSS[130]
C10 AG2 AT32
TP24 VSS[51] VSS[131]
8/25 SI for H/W. AG52
VSS[52] VSS[132]
AT36
A4 BH2 EC_RCIN# R203 10K_4 AH11 AT41
R235 10K_4 TP_PCH_GPIO28 VSS_NCTF_1 VSS_NCTF_16 EC_A20GATE R426 10K_4 VSS[53] VSS[133]
A49 BH52 AH15 AT47
VSS_NCTF_2 VSS_NCTF_17 VSS[54] VSS[134]
A5 BH53 AH16 AT7
VSS_NCTF_3 VSS_NCTF_18 SATA2GP R224 *10K_4 VSS[55] VSS[135]
A50 NCTF BJ1 AH24 AV12
VSS_NCTF_4 VSS_NCTF_19 PCH_GPIO35 R205 10K_4 VSS[56] VSS[136]
A52
VSS_NCTF_5 VSS_NCTF_20
BJ2 AH32
VSS[57] VSS[137]
AV16 Danbury Technology Enabled
A53 BJ4 AV18 AV20
VSS_NCTF_6 VSS_NCTF_21 SATA3GP R234 10K_4 VSS[58] VSS[138] High = Enable
B2 BJ49 AH43 AV24
VSS_NCTF_7 VSS_NCTF_22 SATA5GP R435 10K_4 VSS[59] VSS[139]
B4
VSS_NCTF_8 VSS_NCTF_23
BJ5 AH47
VSS[60] VSS[140]
AV30 NV_ALE
B52 BJ50 BMBUSY# R427 10K_4 AH7 AV34 Low = Disable
VSS_NCTF_9 VSS_NCTF_24 SIO_EXT_SMI# R261 10K_4 VSS[61] VSS[141]
B53 BJ52 AJ19 AV38
VSS_NCTF_10 VSS_NCTF_25 SIO_EXT_SCI# R263 10K_4 VSS[62] VSS[142]
BE1 BJ53 AJ2 AV42
VSS_NCTF_11 VSS_NCTF_26 BT_OFF# R255 10K_4 VSS[63] VSS[143]
BE53 D1 AJ20 AV46
VSS_NCTF_12 VSS_NCTF_27 LCD_BK R432 10K_4 VSS[64] VSS[144]
BF1
VSS_NCTF_13 VSS_NCTF_28
D2 AJ22
VSS[65] VSS[145]
AV49 DMI Termination Voltage
BF53 D53 AJ23 AV5
VSS_NCTF_14 VSS_NCTF_29 VSS[66] VSS[146]
BH1 E1 AJ26 AV8
VSS_NCTF_15 VSS_NCTF_30 PCH_GPIO17 R265 10K_4 VSS[67] VSS[147] Set to Vcc when LOW
E53 AJ28 AW14
VSS_NCTF_31 VSS[68] VSS[148]
AJ32 AW18 NV_CLE
IbexPeak-M_Rev1_0 VSS[69] VSS[149] Set to Vcc/2 when HIGH
AJ34 AW2
VSS[70] VSS[150]
AT5 BF9
VSS[71] VSS[151]
AJ4 AW32
VSS[72] VSS[152]
AK12 AW36
+3V +3VS5 VSS[73] VSS[153]
AM41 AW40
VSS[74] VSS[154]
AN19 AW52
VSS[75] VSS[155]
AK26 AY11
BIOS_REC R222 10K_4 RF_OFF# R221 1K_4 VSS[76] VSS[156]
AK22 AY43 No Reboot Strap
VSS[77] VSS[157]
BIOS RECOVERY AK23
VSS[78] VSS[158]
AY47
HIGH : DISABLE AK28
LAN_DISABLE_R# R196 10K_4 VSS[79]
LOW : ENABLE
IbexPeak-M_Rev1_0

<7,25> ACZ_SPKR +3V


C *1K_4 R430 C

50%31 ,' ,' ,' ,' ,' ,' %RDUG,' ,' ,' ,' ,' ,' ,'
+3VS5

58 5' <7,29> GPIO33_E R253 *100K_4


80$ *3,2 *3,2 *3,2 *3,2 *3,2 *3,2
R207 10K_4 BOARD_ID0 R206 *10K_4
31R12MB0000 (PIM) 0 0 0 0 0 0  80$ 58 5'
31R12MB0010 (PDT) 0 0 0 0 0 0 80$',6  'LV
R419 *10K_4 BOARD_ID1 R437 10K_4
6H\PRXU;7  1R 58 5' <3,5,11,29,32,33,38> +1.05V_VTT
+\QL[ 5HVHUYH  <HV
R214 *10K_4 BOARD_ID2 R213 10K_4
<5,11,32> +1.8V
<2,3,7,8,9,11,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V
31R12MB0020 (PIM) 1 0 0 0 0 0  1R +3V
58 5' <3,7,8,9,11,26,31,32,34,35,36,38> +3VS5
31R12MB0030 (PDT) 1 0 0 0 0 0 5HVHUYH  <HV
R202 *10K_4 BOARD_ID3 R218 10K_4
6DPVXQJ  1R 58 5'
31R12MB0040 (PIM) 1 0 0 0 0 0
5HVHUYH  <HV
R424 *10K_4 BOARD_ID4 R204 10K_4
31R12MB0050 (PDT) 1 0 0 0 0 0  1R 58 5'
5HVHUYH  <HV
+\QL[* R428 *10K_4 BOARD_ID5 R431 10K_4
 1R
31R12MB0060 (PIM)
31R12MB0070 (PDT)
1
1
0
0
0
0
0
0
0
0
0
0
5HVHUYH  <HV 8/25 SI for H/W.

6DPVXQJ*
31R12MB0080 (PIM) 1 0 0 0 0 0
31R12MB0090 (PDT) 1 0 0 0 0 0

D D

352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 1A
PCH 4/5 (GPIO & Strap)
Date: Sunday, September 19, 2010 Sheet 10 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

11
8/25 SI modify
Uninstall on UMA
Install on DIS

R466 *0_6 +3V


U24G POWER +3V_LDO
DIS UMA U24J POWER
+1.05V 1.524A
C463 1U/6.3V_4
AB24 VCCCORE[1] VCCADAC[1] AE50 C683 10U/6.3V_8
C671 0.1U/10V_4 TP17 VCCACLK
Ibex-M
10 OF 10VCCIO[5] 3.208A
A AB26 VCCCORE[2] Ibex-M Ra 0 ohm NA AP51 VCCACLK[1] V24 +1.05V A
C453 10U/6.3VS_6 AB28 7 OF 10 AE52 C670 0.01U/25V_4 V26
VCCCORE[3] VCCADAC[2] VCCIO[6] C452 1U/6.3V_4
AD26 AP53 Y24
AD28
VCCCORE[4]
AF53
Rb NA 0 ohm DCPSUSBYP Y20
VCCACLK[2] VCCIO[7]
Y26
VCCCORE[5] CRT VSSA_DAC[1] C431 0.1U/10V_4 DCPSUSBYP VCCIO[8]
AF26
AF28
VCCCORE[6]
AF51
Rc 0 ohm NA USB V28 0.163A
VCCCORE[7] VSSA_DAC[2] VCCSUS3_3[1] +3VS5
AF30 U28
AF31
VCCCORE[8]
Ra
Rd NA 0 ohm VCCSUS3_3[2]
U26 C439 0.1U/10V_4
VCCCORE[9] VCCSUS3_3[3] C454 0.1U/10V_4
AH26 VCCCORE[10] VCCALVDS AH38 Rb +3V +1.05V AF23 VCCLAN[1] VCCSUS3_3[4] U24
C445 *0.033U/10V_4
AH28 VCCCORE[11] VSSA_LVDS AH39 VCCSUS3_3[5] P28
AH30 VCCCORE[12] LVDS Rc AF24 VCCLAN[2] VCCSUS3_3[6] P26
AH31 VCCCORE[13] VCCTX_LVDS[1] AP43
C412 10U/6.3V_8
Rd +1.8V VCCSUS3_3[7] N28
AJ30 VCCCORE[14] VCCTX_LVDS[2] AP45 VCCSUS3_3[8] N26
AJ31 AT46 C477 0.1U/10V_4 C470 22U/6.3VS_8 AD38 M28
VCCCORE[15] VCCTX_LVDS[3] C479 0.01U/25V_4 VCCME[1] VCCSUS3_3[9]
VCCTX_LVDS[4] AT45 VCCSUS3_3[10] M26
C432 22U/6.3VS_8 AD39 L28
VCC CORE VCCME[2] VCCSUS3_3[11]
L26
+1.05V 3.208A AK24 VCCIO[24] VCC3_3[2] AB34 0.357A +3V C466 1U/6.3V_4 AD41 VCCME[3]
VCCSUS3_3[12]
VCCSUS3_3[13] J28
J26
+V1.1LAN_VCCAPLL_EXP C469 1U/6.3V_4 VCCSUS3_3[14]
TP14 BJ24 VCCAPLLEXP VCC3_3[3] AB35 AF43 VCCME[4] VCCSUS3_3[15] H28
C475 0.1U/10V_4 H26
AN20
HVCMOS AD35 C440 1U/6.3V_4 AF41
VCCSUS3_3[16]
G28
+1.05V 3.208A
C451 10U/6.3VS_6
AN22
AN23
VCCIO[25]
VCCIO[26]
VCC3_3[4]
C435 *0.1U/25V_4 AF42
VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18] G26
F28
VCCIO[27] VCCME[6] VCCSUS3_3[19]

Clock and Miscellaneous


C448 1U/6.3V_4 AN24 SI EMI request F26
C441 1U/6.3V_4 VCCIO[28] VCCSUS3_3[20]
AN26 V39 E28
C437
C426
1U/6.3V_4
1U/6.3V_4
AN28
BJ26
VCCIO[29]
VCCIO[30] VCCVRM[2] AT24 0.035A +1.8V
V41
VCCME[7] VCCSUS3_3[21]
VCCSUS3_3[22] E26
C28
C425
C446
0.1U/10V_4
0.1U/10V_4
BJ28
VCCIO[31]
VCCIO[32] VCCDMI[1] AT16 0.061A +1.05V_VTT
VCCME[8] VCCSUS3_3[23]
VCCSUS3_3[24] C26
B
C443 0.1U/10V_4
AT26
AT28
VCCIO[33] DMI AU16
V42 VCCME[9] VCCSUS3_3[25] B27
A28
B
VCCIO[34] VCCDMI[2] C430 1U/6.3V_4 VCCSUS3_3[26]
AU26 VCCIO[35] Y39 VCCME[10] VCCSUS3_3[27] A26
AU28 VCCIO[36]
AV26 VCCIO[37] Y41 VCCME[11] VCCSUS3_3[28] U23
AV28
AW26
VCCIO[38] PCI E* VCCPNAND[1] AM16
AK16 Y42 V23 3.208A
VCCIO[39] VCCPNAND[2] VCCME[12] VCCIO[56] +1.05V
AW28 AK20
BA26
VCCIO[40] VCCPNAND[3]
AK19 0.156A +1.8V +VCCRTCEXT V9 F24 R244 >1mA
100_4 +5VS5
VCCIO[41] VCCPNAND[4] C415 0.1U/10V_4 DCPRTC V5REF_SUS
BA28 VCCIO[42] VCCPNAND[5] AK15
BB26 AK13 D4 RB500V-40 +3VS5
BB28
BC26
VCCIO[43]
VCCIO[44]
VCCPNAND[6]
VCCPNAND[7] AM12
AM13
C422 0.1U/10V_4
0.073A +1.8V 0.072A AU24 VCCVRM[3] C447 1U/6.3V_4
VCCIO[45] VCCPNAND[8] C420 0.1U/10V_4
BC28 VCCIO[46] VCCPNAND[9] AM15
BD26 EMI request L40 0_6 +VCCADPLLA BB51 +V5REF_SUS
BD28
BE26
VCCIO[47]
VCCIO[48]
+1.05V
C487 1U/6.3V_4 BB53
VCCADPLLA[1]
VCCADPLLA[2]
K49 R273 100_4
>1mA
BE28
VCCIO[49] NAND / SPI V5REF +5V
VCCIO[50] L41 0_6 +VCCADPLLB D5 RB500V-40
BG26 AM8 BD51
BG28
VCCIO[51]
VCCIO[52]
VCCME3_3[1]
VCCME3_3[2] AM9 0.085A +3V 3.208A C486 1U/6.3V_4 BD53
VCCADPLLB[1]
VCCADPLLB[2] PCI/GPIO/LPC
C484 1U/6.3V_4
+3V
BH27 VCCIO[53] VCCME3_3[3] AP11
AN30 AP9 +1.05V R245 *0_4/S +1.05V_HDMI1 AH23 +V5REF
VCCIO[54] VCCME3_3[4] C417 0.1U/10V_4 C433 1U/6.3V_4 VCCIO[21]
AN31 AJ35 J38

0.357A
VCCIO[55] C434 1U/6.3V_4 AH35
VCCIO[22]
VCCIO[23]
VCC3_3[8]
VCC3_3[9] L38
+3V
0.357A
+3V AN35 VCC3_3[1] AF34 VCCIO[2] VCC3_3[10] M36
PV modify R252 *0_4/S +1.05V_HDMI2 AH34 N36 C462 0.1U/10V_4
C457 1U/6.3V_4 VCCIO[3] VCC3_3[11] C468 0.1U/10V_4
AF32 P36
+1.8V 0.035A AT22 VCCVRM[1]
VCCIO[4] VCC3_3[12]
VCC3_3[13] U35

+V1.1LAN_VCCAPLL_FDI BJ18
FDI C419 0.1U/10V_4 +VCCSST V12
VCC3_3[14] AD13
C TP5 VCCFDIPLL DCPSST C

+1.05V 3.208A AM23 VCCIO[1] C427


+V1.1LAN_INT_VCCSUS Y22
0.1U/10V_4 DCPSUS
IbexPeak-M_Rev1_0
P18
PCI/GPIO/LPC VCCSATAPLL[1] AK3
AK1
3.208A
+V1.1LAN_VCCAPLL
+3VS5 0.163A U19
U20
VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSATAPLL[2] TP11

C442 0.1U/10V_4 VCCSUS3_3[31]


U22 VCCSUS3_3[32] VCCVRM[4] AT20 +1.8V

UMA Only, If have power noise issue then stuff it. V15 VCC3_3[5] VCCIO[9] AH22 0.035A +1.05V
V16 AH19
+5V
U26
+3V_LDO
+3V 0.357A
C424 0.1U/10V_4
Y16
VCC3_3[6]
VCC3_3[7]
VCCIO[10]
VCCIO[11] AD20
AF22
C421 1U/6.3V_4

G910T21U VCCIO[12]
AD19
3 Vin Vout 1 +1.05V_VTT >1mA
C416 4.7U/6.3V_6
AT18 V_CPU_IO[1]
VCCIO[13]
VCCIO[14] AF20
AU18 SATA AF19
GND

C418 0.1U/10V_4 V_CPU_IO[2] VCCIO[15]


C423 0.1U/10V_4
CPU VCCIO[16] AH20
AB19
C692 VCCIO[17]
AB20
2mA
2

1U/6.3V_4 VCCIO[18]
+RTC_CELL A12 VCCRTC VCCIO[19] AB22
C661 0.1U/10V_4 RTC AD22
C662 0.1U/10V_4 VCCIO[20]
8/25 SI modify
Install LDO when UMA +3VS5 6mA L30 VCCSUSHDA VCCME[13] AA34
Y34
1.998A +1.05V
C444 1U/6.3V_4 VCCME[14]
HDA VCCME[15] Y35
VCCME[16] AA35

D D
IbexPeak-M_Rev1_0

<2,7,8,9,39> +1.05V 352-(&75


4XDQWD&RPSXWHU,QF
<3,5,10,29,32,33,38> +1.05V_VTT
<5,32> +1.8V
<2,3,7,8,9,10,12,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V
<3,7,8,9,10,26,31,32,34,35,36,38> +3VS5
<17,21,22,23,25,28,30,36> +5V Size Document Number Rev
Custom 1A
<20,26,31,32,33,34,35,36,38,39> +5VS5 PCH 5/5 (POWER)
Date: Sunday, September 19, 2010 Sheet 11 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

12
JDIM1A M_A_DQ[63:0] <4>
<4> M_A_A[15:0]
A M_A_A0 98 5 M_A_DQ0 A
M_A_A1 A0 DQ0 M_A_DQ1 +1.5VSUS
97 A1 DQ1 7
M_A_A2 96 15 M_A_DQ2
M_A_A3 A2 DQ2 M_A_DQ3
95 A3 DQ3 17
M_A_A4 92 4 M_A_DQ4
M_A_A5 A4 DQ4 M_A_DQ5 JDIM1B
91 A5 DQ5 6
M_A_A6 90 16 M_A_DQ6 75 44
M_A_A7 A6 DQ6 M_A_DQ7 VDD1 VSS16
86 A7 DQ7 18 76 VDD2 VSS17 48
M_A_A8 89 21 M_A_DQ8 81 49
M_A_A9 A8 DQ8 M_A_DQ9 VDD3 VSS18
85 A9 DQ9 23 82 VDD4 VSS19 54
M_A_A10 107 33 M_A_DQ10 87 55
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD5 VSS20
84 A11 DQ11 35 88 VDD6 VSS21 60
M_A_A12 83 22 M_A_DQ12 93 61
SO-DIMMA SPD Address is 0XA0 M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD7 VSS22
119 A13 DQ13 24 94 VDD8 VSS23 65
SO-DIMMA TS Address is 0X30 M_A_A14 80 34 M_A_DQ14 99 66
M_A_A15 A14 DQ14 M_A_DQ15 VDD9 VSS24
78 A15 DQ15 36 100 VDD10 VSS25 71
39 M_A_DQ16 105 72
DQ16 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


<4> M_A_BS#0 109 41 M_A_DQ17 106 127

PC2100 DDR3 SDRAM SO-DIMM


BA0 DQ17 M_A_DQ18 VDD12 VSS27
<4> M_A_BS#1 108 BA1 DQ18 51 111 VDD13 VSS28 128
<4> M_A_BS#2 79 53 M_A_DQ19 112 133
BA2 DQ19 M_A_DQ20 VDD14 VSS29
<4> M_A_CS#0 114 S0# DQ20 40 117 VDD15 VSS30 134
<4> M_A_CS#1 121 42 M_A_DQ21 118 138
S1# DQ21 M_A_DQ22 VDD16 VSS31 +0.75V_DDR_VTT
<4> M_A_CLK0 101 CK0 DQ22 50 123 VDD17 VSS32 139
<4> M_A_CLK0# 103 52 M_A_DQ23 124 144
CK0# DQ23 M_A_DQ24 VDD18 VSS33
<4> M_A_CLK1 102 CK1 DQ24 57 VSS34 145
<4> M_A_CLK1# 104 59 M_A_DQ25 +3V 199 150
CK1# DQ25 M_A_DQ26 VDDSPD VSS35 R157
<4> M_A_CKE0 73 CKE0 DQ26 67 VSS36 151
<4> M_A_CKE1 74 69 M_A_DQ27 77 155 22_4
CKE1 DQ27 M_A_DQ28 for S3 power reduction NC1 VSS37
<4> M_A_CAS# 115 CAS# DQ28 56 122 NC2 VSS38 156
B <4> M_A_RAS# 110 58 M_A_DQ29 125 161 B
RAS# DQ29 M_A_DQ30 NCTEST VSS39
<4> M_A_W E# 113 WE# DQ30 68 VSS40 162

3
R375 10K_4 DIMM0_SA0 197 70 M_A_DQ31 <3,13> PM_EXTTS#0 PM_EXTTS#0 198 167 SI modify
R380 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ32 EVENT# VSS41
201 SA1 DQ32 129 <3,13> DDR3_DRAMRST# 30 RESET# VSS42 168
<2,8,13> CGCLK_SMB 202 131 M_A_DQ33 +1.5VSUS R48 1K_4 172
SCL DQ33 M_A_DQ34 VSS43
<2,8,13> CGDAT_SMB 200 SDA DQ34 141 VSS44 173 <5,36> MAINON_G 2
143 M_A_DQ35 SMDDR_VREF_DQ0 1 178
DQ35 M_A_DQ36 SMDDR_VREF_DIMM VREF_DQ VSS45
<4> M_A_ODT0 116 ODT0 DQ36 130 126 VREF_CA VSS46 179
<4> M_A_ODT1 120 132 M_A_DQ37 184 Q11
ODT1 DQ37 M_A_DQ38 VSS47 2N7002E
<4> M_A_DM[7:0] 140 185

1
M_A_DM0 DQ38 M_A_DQ39 VSS48
11 DM0 DQ39 142 2 VSS1 VSS49 189
M_A_DM1 28 147 M_A_DQ40 3 190
M_A_DM2 DM1 DQ40 M_A_DQ41 VSS2 VSS50
46 DM2 DQ41 149 8 VSS3 VSS51 195
M_A_DM3 M_A_DQ42

(204P)
63 157 9 196
(204P)

M_A_DM4 DM3 DQ42 M_A_DQ43 VSS4 VSS52 for S3 power reduction


136 DM4 DQ43 159 13 VSS5
M_A_DM5 153 146 M_A_DQ44 14
M_A_DM6 DM5 DQ44 M_A_DQ45 VSS6
170 DM6 DQ45 148 19 VSS7
M_A_DM7 187 158 M_A_DQ46 20
DM7 DQ46 M_A_DQ47 VSS8
<4> M_A_DQS[7:0] DQ47 160 25 VSS9
M_A_DQS0 12 163 M_A_DQ48 26 203 +0.75V_DDR_VTT
M_A_DQS1 DQS0 DQ48 M_A_DQ49 VSS10 VTT1
29 DQS1 DQ49 165 31 VSS11 VTT2 204
M_A_DQS2 47 175 M_A_DQ50 32
M_A_DQS3 DQS2 DQ50 M_A_DQ51 VSS12
64 DQS3 DQ51 177 37 VSS13

C378

C379
M_A_DQS4 137 164 M_A_DQ52 38
M_A_DQS5 DQS4 DQ52 M_A_DQ53 VSS14
154 166 43

GND

GND
M_A_DQS6 DQS5 DQ53 M_A_DQ54 VSS15 0510 add for WiMAX
171 DQS6 DQ54 174
M_A_DQS7 M_A_DQ55

*15P/50V_4

*15P/50V_4
<4> M_A_DQS#[7:0] 188 DQS7 DQ55 176
M_A_DQS#0 10 181 M_A_DQ56 DDR3-DIMM0

205

206
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
C
M_A_DQS#2 45 191 M_A_DQ58 C
M_A_DQS#3 DQS#2 DQ58 M_A_DQ59
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
M_A_DQS#5 DQS#4 DQ60 M_A_DQ61
152 DQS#5 DQ61 182
M_A_DQS#6 169 192 M_A_DQ62
M_A_DQS#7 DQS#6 DQ62 M_A_DQ63
186 DQS#7 DQ63 194

DDR3-DIMM0 +1.5VSUS

Place these Caps near So-Dimm0. 0511 add for WiMAX


Some Projects replace 10UF 0805 by 4.7UF 0603
+1.5VSUS R35
It can cost down 30% 1K/F_4
+1.5VSUS
+0.75V_DDR_VTT SMDDR_VREF_DQ0
C210 10U/6.3VS_6
C185 10U/6.3VS_6 C365 1U/6.3V_4
C234 *100P/50V_4

C222 *100P/50V_4
*6.8P/50V_4

*6.8P/50V_4

2
C166 10U/6.3VS_6 C381 1U/6.3V_4 C296 470P/50V_4
SMDDR_VREF_DIMM <13>
C221 10U/6.3VS_6 C380 1U/6.3V_4 R40 C34 C46 R111 *0_4/S DDR_VTTREF <35>
C254 10U/6.3VS_6 C366 1U/6.3V_4 1K/F_4 0.1U/10V_4 *0.047U/10V_4 R105 *10K/F_4 +1.5VSUS

1
C232 10U/6.3VS_6 C360 *10U/6.3V_8 R109 *10K/F_4
C156 0.1U/10V_4 C387 *10U/6.3V_8
C253

C173

C197 0.1U/10V_4 C370 10U/6.3VS_6


C172 0.1U/10V_4 C367 1 2 *0.047U/10V_4
C192 0.1U/10V_4 C382 1 2*0.047U/10V_4
C267 0.1U/10V_4 <13,35,36> +0.75V_DDR_VTT
C152 2 1 *0.047U/10V_4 <3,5,13,34,35,36> +1.5VSUS
D
C244 2 1 *0.047U/10V_4 <2,3,7,8,9,10,11,13,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V D

SMDDR_VREF_DQ0 <29,31,37> +5VPCU

C33 0.1U/10V_4
C29 2.2U/6.3V_6
352-(&75
+3V SMDDR_VREF_DIMM
4XDQWD&RPSXWHU,QF
C352 2.2U/6.3V_6 C308 0.1U/10V_4
C368 *0.1U/10V_4 C334 2.2U/6.3V_6 Size Document Number Rev
C358 2 1 *0.047U/10V_4 C324 1 2*0.047U/10V_4 Custom 1A
DDR3 DIMM-0
Date: Sunday, September 19, 2010 Sheet 12 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

13
JDIM2A M_B_DQ[63:0] <4>
<4> M_B_A[15:0] +1.5VSUS
M_B_A0 98 5 M_B_DQ0
M_B_A1 A0 DQ0 M_B_DQ1
A 97 A1 DQ1 7 A
M_B_A2 96 15 M_B_DQ2
M_B_A3 A2 DQ2 M_B_DQ3
95 A3 DQ3 17 JDIM2B
M_B_A4 92 4 M_B_DQ4
M_B_A5 A4 DQ4 M_B_DQ5
91 A5 DQ5 6 75 VDD1 VSS16 44
M_B_A6 90 16 M_B_DQ6 76 48
M_B_A7 A6 DQ6 M_B_DQ7 VDD2 VSS17
86 A7 DQ7 18 81 VDD3 VSS18 49
M_B_A8 89 21 M_B_DQ8 82 54
M_B_A9 A8 DQ8 M_B_DQ9 VDD4 VSS19
85 A9 DQ9 23 87 VDD5 VSS20 55
M_B_A10 107 33 M_B_DQ10 88 60
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD6 VSS21
84 A11 DQ11 35 93 VDD7 VSS22 61
M_B_A12 83 22 M_B_DQ12 94 65
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD8 VSS23
119 A13 DQ13 24 99 VDD9 VSS24 66
M_B_A14 80 34 M_B_DQ14 100 71
M_B_A15 A14 DQ14 M_B_DQ15 VDD10 VSS25
78 A15 DQ15 36 105 VDD11 VSS26 72
39 M_B_DQ16 106 127

PC2100 DDR3 SDRAM SO-DIMM


DQ16 M_B_DQ17 VDD12 VSS27

PC2100 DDR3 SDRAM SO-DIMM


<4> M_B_BS#0 109 BA0 DQ17 41 111 VDD13 VSS28 128
<4> M_B_BS#1 108 51 M_B_DQ18 112 133
BA1 DQ18 M_B_DQ19 VDD14 VSS29
<4> M_B_BS#2 79 BA2 DQ19 53 117 VDD15 VSS30 134
<4> M_B_CS#0 114 40 M_B_DQ20 118 138
S0# DQ20 M_B_DQ21 VDD16 VSS31
<4> M_B_CS#1 121 S1# DQ21 42 123 VDD17 VSS32 139
<4> M_B_CLK0 101 50 M_B_DQ22 124 144
CK0 DQ22 M_B_DQ23 VDD18 VSS33
<4> M_B_CLK0# 103 CK0# DQ23 52 VSS34 145
<4> M_B_CLK1 102 57 M_B_DQ24 199 150
CK1 DQ24 +3V VDDSPD VSS35
<4> M_B_CLK1# 104 59 M_B_DQ25 151
CK1# DQ25 M_B_DQ26 VSS36
<4> M_B_CKE0 73 CKE0 DQ26 67 77 NC1 VSS37 155
<4> M_B_CKE1 74 69 M_B_DQ27 122 156
CKE1 DQ27 M_B_DQ28 NC2 VSS38
<4> M_B_CAS# 115 CAS# DQ28 56 125 NCTEST VSS39 161
<4> M_B_RAS# 110 58 M_B_DQ29 162
RAS# DQ29 M_B_DQ30 VSS40
B <4> M_B_W E# 113 WE# DQ30 68 <3> PM_EXTTS#1 198 EVENT# VSS41 167 B
R162 10K_4 DIMM1_SA0 197 70 M_B_DQ31 <3,12> DDR3_DRAMRST# 30 168
DIMM1_SA1 201 SA0 DQ31 M_B_DQ32 RESET# VSS42
+3V R171 10K_4
SA1 DQ32 129 VSS43 172
<2,8,12> CGCLK_SMB 202 131 M_B_DQ33 173
SCL DQ33 M_B_DQ34 SMDDR_VREF_DQ1 VSS44
<2,8,12> CGDAT_SMB 200 SDA DQ34 141 1 VREF_DQ VSS45 178
143 M_B_DQ35 <12> SMDDR_VREF_DIMM 126 179
DQ35 M_B_DQ36 VREF_CA VSS46
<4> M_B_ODT0 116 ODT0 DQ36 130 VSS47 184
<4> M_B_ODT1 120 132 M_B_DQ37 185
ODT1 DQ37 M_B_DQ38 VSS48
<4> M_B_DM[7:0] DQ38 140 2 VSS1 VSS49 189
M_B_DM0 11 142 M_B_DQ39 3 190
SO-DIMMB SPD Address is 0XA4 M_B_DM1 DM0 DQ39 M_B_DQ40 VSS2 VSS50
28 DM1 DQ40 147 8 VSS3 VSS51 195
M_B_DM2 M_B_DQ41

(204P)
SO-DIMMB TS Address is 0X34 46 DM2 DQ41 149 9 VSS4 VSS52 196
M_B_DM3 63 157 M_B_DQ42 13
(204P)

M_B_DM4 DM3 DQ42 M_B_DQ43 VSS5


136 DM4 DQ43 159 14 VSS6
M_B_DM5 153 146 M_B_DQ44 19
M_B_DM6 DM5 DQ44 M_B_DQ45 +1.5VSUS VSS7
170 DM6 DQ45 148 20 VSS8
M_B_DM7 187 158 M_B_DQ46 25
DM7 DQ46 M_B_DQ47 VSS9
<4> M_B_DQS[7:0] DQ47 160 26 VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DQS0 12 163 M_B_DQ48 31 204
M_B_DQS1 DQS0 DQ48 M_B_DQ49 VSS11 VTT2
29 DQS1 DQ49 165 32 VSS12
M_B_DQS2 47 175 M_B_DQ50 R39 37
M_B_DQS3 DQS2 DQ50 M_B_DQ51 1K/F_4 VSS13
64 DQS3 DQ51 177 38 VSS14
M_B_DQS4 137 164 M_B_DQ52 43

GND

GND
M_B_DQS5 DQS4 DQ52 M_B_DQ53 SMDDR_VREF_DQ1 VSS15
154 DQS5 DQ53 166
M_B_DQS6 171 174 M_B_DQ54
M_B_DQS7 DQS6 DQ54 M_B_DQ55 DDR3-DIMM1
<4> M_B_DQS#[7:0] 188 176

205

206
DQS7 DQ55

2
M_B_DQS#0 10 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57 R41 C35 C51
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ58 1K/F_4 0.1U/10V_4 *0.047U/10V_4

1
M_B_DQS#3 DQS#2 DQ58 M_B_DQ59
C 62 DQS#3 DQ59 193 C
M_B_DQS#4 135 180 M_B_DQ60
M_B_DQS#5 DQS#4 DQ60 M_B_DQ61
152 DQS#5 DQ61 182
M_B_DQS#6 169 192 M_B_DQ62
M_B_DQS#7 DQS#6 DQ62 M_B_DQ63
186 DQS#7 DQ63 194

U14
DDR3-DIMM1 C559 *0.01U/25V_4
SI modify <8,29> MBCLK2 MBCLK2 8 1 +3V
SCLK VCC DDR_THERMDA
Place these Caps near So-Dimm1. <8,29> MBDATA2 MBDATA2 7 SDA DXP 2

3
Some Projects replace 10UF 0805 by 4.7UF 0603 Q23
PM_EXTTS#0_Q 6 3 C558 2
It can cost down 30% ALERT# DXN *MMBT3904-7-F
PM_EXTTS#1_Q 4 5 *2200P/50V_4

1
+1.5VSUS +0.75V_DDR_VTT +3V OVERT# GND
DDR_THERMDC
C273 10U/6.3VS_6 C364 1U/6.3V_4 *G780P81U
C208 10U/6.3VS_6 C363 1U/6.3V_4 8/25 SI for H/W.
C170 10U/6.3VS_6 C621 1U/6.3V_4 $''5(66+

2
C263 10U/6.3VS_6 C362 1U/6.3V_4 SMDDR_VREF_DIMM
C231 10U/6.3VS_6 C359 *10U/6.3V_8 8/25 SI for H/W.
C191 10U/6.3VS_6 C635 10U/6.3VS_6 C343 0.1U/10V_4 1 3 PM_EXTTS#0_Q
C196 0.1U/10V_4 C384 10U/6.3VS_6 C342 2.2U/6.3V_6 <3,12> PM_EXTTS#0
C218 0.1U/10V_4 C376 1 2*0.047U/10V_4 C344 1 2*0.047U/10V_4
C184 0.1U/10V_4 C377 1 2*0.047U/10V_4 8/25 SI for H/W. Q19 *BSS138_NL
C246 0.1U/10V_4
C161 0.1U/10V_4 SMDDR_VREF_DQ1 8/25 SI for H/W.
C375 0.1U/10V_4 <12,35,36> +0.75V_DDR_VTT
C289 1 2 *0.047U/10V_4 C32 0.1U/10V_4 +3V
D <3,5,12,34,35,36> +1.5VSUS D
C155 1 2 *0.047U/10V_4 C625 0.1U/10V_4 C28 2.2U/6.3V_6 <2,3,7,8,9,10,11,12,14,17,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V
C288 0.1U/10V_4 <29,31,37> +5VPCU

2
EMI request

<3> PM_EXTTS#1
1 3 PM_EXTTS#1_Q
352-(&75
+3V
Q20 *BSS138_NL 4XDQWD&RPSXWHU,QF
C350 2.2U/6.3V_6
C354 *0.1U/10V_4 8/25 SI for H/W. Size Document Number Rev
C353 1 2*0.047U/10V_4 Custom 1A
DDR3 DIMM-1
Date: Sunday, September 19, 2010 Sheet 13 of 39
1 2 3 4 5 6 7 8
5 4 3 2 1

U17A

+1.8V_DPE_VDD18 AG15
U17G

DP E/F POWER

DPE_VDD18#1
DP A/B POWER

DPA_VDD18#1 AE11 +1.8V_DPA_VDD18


14
AG16 DPE_VDD18#2 DPA_VDD18#2 AF11

2.5GT/s bit rate


AF30 AH30 C_PEG_RXN0 C190 0.1U/10V_4 +1.0V_DPE_VDD10 AG20 AF6 +1.0V_DPB_VDD10
<3> PEG_TX0 PCIE_RX0P PCIE_TX0P PEG_RX0 <3> DPE_VDD10#1 DPA_VDD10#1
AE31 AG31 C_PEG_RXP0 C194 0.1U/10V_4 AG21 AF7
<3> PEG_TX#0 PCIE_RX0N PCIE_TX0N PEG_RX#0 <3> DPE_VDD10#2 DPA_VDD10#2
D D

AE29 AG29 C_PEG_RXP1 C195 0.1U/10V_4 AG14 AE1


<3> PEG_TX1 PCIE_RX1P PCIE_TX1P C_PEG_RXN1 PEG_RX1 <3> DPE_VSSR#1 DPA_VSSR#1
AD28 AF28 C207 0.1U/10V_4 AH14 AE3
<3> PEG_TX#1 PCIE_RX1N PCIE_TX1N PEG_RX#1 <3> DPE_VSSR#2 DPA_VSSR#2
AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
AD30 AF27 C_PEG_RXP2 C211 0.1U/10V_4 AM18 AH5
<3> PEG_TX2 PCIE_RX2P PCIE_TX2P PEG_RX2 <3> DPE_VSSR#5 DPA_VSSR#5
AC31 AF26 C_PEG_RXN2 C215 0.1U/10V_4
<3> PEG_TX#2 PCIE_RX2N PCIE_TX2N PEG_RX#2 <3>
+1.0V_VGA
AC29 AD27 C_PEG_RXP3 C187 0.1U/10V_4 +1.8V_DPE_VDD18 AF16 AE13 +1.8V_DPA_VDD18
<3> PEG_TX3 PCIE_RX3P PCIE_TX3P C_PEG_RXN3 PEG_RX3 <3> DPF_VDD18#1 DPB_VDD18#1
AB28 AD26 C174 0.1U/10V_4 AG17 AF13 1.0V@220mA
<3> PEG_TX#3 PCIE_RX3N PCIE_TX3N PEG_RX#3 <3> DPF_VDD18#2 DPB_VDD18#2

AB30 AC25 C_PEG_RXP4 C227 0.1U/10V_4 +1.0V_DPB_VDD10 L46


<3> PEG_TX4 PCIE_RX4P PCIE_TX4P PEG_RX4 <3>
AA31 AB25 C_PEG_RXN4 C236 0.1U/10V_4 +1.0V_DPE_VDD10 AF22 AF8 0_6
<3> PEG_TX#4 PCIE_RX4N PCIE_TX4N PEG_RX#4 <3> DPF_VDD10#1 DPB_VDD10#1

PCI EXPRESS INTERFACE


AG22 DPF_VDD10#2 DPB_VDD10#2 AF9
C547 C535 C548
AA29 Y23 C_PEG_RXP5 C217 0.1U/10V_4 0.1U/10V_4 *10U/6.3V_8 *1U/6.3V_4
<3> PEG_TX5 PCIE_RX5P PCIE_TX5P PEG_RX5 <3>
Y28 Y24 C_PEG_RXN5 C225 0.1U/10V_4 R64 0_4 AF23 AF10
<3> PEG_TX#5 PCIE_RX5N PCIE_TX5N PEG_RX#5 <3> DPF_VSSR#1 DPB_VSSR#1
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
Y30 AB27 C_PEG_RXP6 C240 0.1U/10V_4 AM22 AM6 8/25 SI for AMD.
<3> PEG_TX6 PCIE_RX6P PCIE_TX6P C_PEG_RXN6 PEG_RX6 <3> DPF_VSSR#4 DPB_VSSR#4
W 31 AB26 C248 0.1U/10V_4 AM24 AM8
<3> PEG_TX#6 PCIE_RX6N PCIE_TX6N PEG_RX#6 <3> DPF_VSSR#5 DPB_VSSR#5

W 29 Y27 C_PEG_RXP7 C250 0.1U/10V_4


<3> PEG_TX7 PCIE_RX7P PCIE_TX7P PEG_RX7 <3>
V28 Y26 C_PEG_RXN7 C264 0.1U/10V_4
<3> PEG_TX#7 PCIE_RX7N PCIE_TX7N PEG_RX#7 <3>
R90 150/F_4 AF17 AE10 R82 150/F_4
DPEF_CALR DPAB_CALR
C V30 PCIE_RX8P PCIE_TX8P W 24 C
U31 PCIE_RX8N PCIE_TX8N W 23
+1.8V_DPE_VDD18 AG18 DP PLL POWER AG8 +1.8V_DPA_VDD18
DPE_PVDD DPA_PVDD
AF19 DPE_PVSS DPA_PVSS AG7
U29 PCIE_RX9P PCIE_TX9P V27
T28 PCIE_RX9N PCIE_TX9N U26 8/25 SI for AMD. 8/25 SI for AMD.
+1.8V_DPE_VDD18 AG19 AG10 +1.8V_DPA_VDD18
DPF_PVDD DPB_PVDD
T30 PCIE_RX10P PCIE_TX10P U24 AF20 DPF_PVSS DPB_PVSS AG11
R31 PCIE_RX10N PCIE_TX10N U23

R29 T26 Seymour-S3


PCIE_RX11P PCIE_TX11P AJ080900T01
P28 PCIE_RX11N PCIE_TX11N T27
FCBGA631-AMD-M92-S2

P30 PCIE_RX12P PCIE_TX12P T24


N31 PCIE_RX12N PCIE_TX12N T23

N29 PCIE_RX13P PCIE_TX13P P27


M28 PCIE_RX13N PCIE_TX13N P26 (Seymour-S3: LVDS mode 240mA@1.0V)
+1.0V_DPE_VDD10 +1.8V_DPA_VDD18 1.8V(300mA)
(Seymour-S3: DP mode 220mA@1.0V)
M30 P24 +1.0V_DPE_VDD10 L15 0_6 +1.8V_DPA_VDD18 L16 0_6
PCIE_RX14P PCIE_TX14P +1.0V_VGA +1.8V_VGA
L31 PCIE_RX14N PCIE_TX14N P23
C140 C141
C147 C120 C133 0.1U/10V_4 *1U/6.3V_4 C127
L29 M27 0.1U/10V_4 *1U/6.3V_4 *10U/6.3V_6 *10U/6.3V_8
PCIE_RX15P PCIE_TX15P
B
K30 PCIE_RX15N PCIE_TX15N N26 B

(Seymour-S3: LVDS mode 300mA@1.8V)


CLOCK
CLK_PCIE_VGA
(Seymour-S3: DP mode 300mA@1.8V)
<8> CLK_PCIE_VGA AK30 PCIE_REFCLKP
CLK_PCIE_VGA# AK32 +1.8V_DPE_VDD18 L12 0_6 +1.8V_VGA
<8> CLK_PCIE_VGA# PCIE_REFCLKN C121 C110
C130 8/25 SI for AMD.
CALIBRATION 0.1U/10V_4 *1U/6.3V_4 *10U/6.3V_8
Y22 M72_PCIE_CALRP R100 1.27K/F_4
PCIE_CALRP
10K_4 R332 N10 AA22 M72_PCIE_CALRN R104 2K/F_4 +1.0V_VGA
PW RGOOD PCIE_CALRN

PEGX_RST# AL27 PERSTB

Seymour-S3
100MHz (+/-300ppm) input frequency, AJ080900T01 8/25 SI for AMD. 8/25 SI for AMD.
0-0.7V single-ended swing FCBGA631-AMD-M92-S2

+3V

C100
U3 0.1U/10V_4
A MC74VHC1G08DFT2G A
5

+1.0V_VGA
<15,17,35> +1.0V_VGA
<3,8,24,27,29,30> PLTRST# 2
4 PEGX_RST# +1.8V_VGA
<15,17,35> +1.8V_VGA
<10> DGPU_HOLD_RST# R61 330_4 DGPU_HIN_RST# 1

R67
352-(&75
3

100K_4 4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom Seymour PCIE_Interface 1A

Date: Sunday, September 19, 2010 Sheet 14 of 39


5 4 3 2 1
5 4 3 2 1

MEM_ID[3:0]
0000
0001
0010
Vendor
Samsung- E die
Hynix- Vega die
Hynix- Vega die
Type
64*16-800MHZ
64*16-800MHZ
128*16-800MHZ
Vendor P/N
K4W1G1646E-HC12
H5TQ1G63DFR-12C
H5TQ2G63BFR-12C T4 AE9
U17B

Seymour-S3
DVCNTL_0/ DVPDATA_18
TXCAP_DPA3P
TXCAM_DPA3N
AF2
AF4 +1.8V_AVDD_Q +A2VDD
15
0011 Samsung- C die 128*16-800MHZ K4W2G1646C-HC12 T22 L9
DVCNTL_1 / NC 1.8V(70mA) 3.3V(65mA)
0100 Micron 128*16-800MHZ MT41J128M16HA-125:D T21 N9
DVCNTL_2 / NC TX0P_DPA2P
AG3
0101 Reserved AE8 DPA AG5 +1.8V_AVDD_Q L14 +A2VDD L13 +3V_DELAY
T5 DVDATA_12 / DVPDATA_16 TX0M_DPA2N +1.8V_VGA
0110 Hynix- Vega die 64*16-900MHZ H5TQ1G63DFR-11C T6 AD9
DVDATA_11 / DVPDATA_20
0111 Samsung- E die 64*16-900MHZ K4W1G1646E-HC11 AC10 AH3 PBY160808T-121Y-N/2.5A_6 *BLM18PG181SN1D(180,1.5A)_6
T10 DVDATA_10 / DVPDATA_22 TX1P_DPA1P
1000 Samsung- G die 64*16-900MHZ K4W1G1646G-BC11 T7 AD7
DVDATA_9 / DVPDATA_12 TX1M_DPA1N
AH1
1001 Reserved AC8 C134 C148 C122 C112 C104 C93
T8 DVDATA_8 / DVPDATA_14
1010 Hynix- Vega die 128*16-900MHZ H5TQ2G63BFR-11C AC7 AK3 0.1U/10V_4 1U/6.3V_4 10U/6.3V_6 *0.1U/10V_4 *1U/6.3V_4 *10U/6.3V_8
T11 DVDATA_7 / DVPCNTL_0 TX2P_DPA0P
1011 Samsung- C die 128*16-900MHZ K4W2G1646C-HC11 T13 AB9
DVDATA_6 / DVPDATA_8 TX2M_DPA0N
AK1
1100 Reserved T12 AB8
DVDATA_5 / DVPDATA_6
D 1101 Reserved +VDDR4 T9 AB7
DVDATA_4 DVPDATA_4 TXCBP_DPB3P
AK5 D
1110 Reserved Memory ID TXCBM_DPB3N
AM3
1111 Reserved R305
DVO
10K_4 MEM_ID3 AB4 AK6
R303 *10K_4 MEM_ID2 DVDATA_3 / DVPDATA_19 TX3P_DPB2P
AB2 AM5
R87 10K_4 MEM_ID1 DVDATA_2 / DVPDATA_21 TX3M_DPB2N
Y8
DVDATA_1 / DVPDATA_2 DPB
R86 10K_4 MEM_ID0 Y7 AJ7
DVDATA_0 / DVPDATA_0 TX4P_DPB1P
AH6
TX4M_DPB1N +VDDD1 +1.8V_A2VDD_Q
PBY160808T-121Y-N/2.5A_6 1.8V(150mA DPC_VDD18) AK8 1.8V(45mA VDD1DI) 1.8V(2mA)
+1.8V_DPC_VDD18 TX5P_DPB0P
+1.8V_VGA AL7
L47 TX5M_DPB0N +VDDD1 L9 +1.8V_A2VDD_Q L17
+1.8V_VGA +1.8V_VGA
C553 C552 C551 Seymour-S3
10U/6.3V_8 1U/6.3V_4 0.1U/10V_4 W6 PBY160808T-121Y-N/2.5A_6 *PBY160808T-121Y-N/2.5A_6
DPC_PVDD / DVPDATA_11
V6
DPC_PVSS / GND Seymour-S3
V4 C90 C89 C106 C132 C145 C144
DVPDATA_3/TXCCP_DPC3P 0.1U/10V_4 1U/6.3V_4 10U/6.3V_6 *0.1U/10V_4 *1U/6.3V_4 *10U/6.3V_8
U5
DVPCNTL_2/TXCCM_DPC3N
+1.8V_DPC_VDD18 AC6
DPC_VDD18#1/DVPDAT10
AC5
DPC_VDD18#2/DVPDAT23 DVPDATA_7 / TX0P_DPC2P
W3 Robson-- Install
V2 Seymour- NC
DVPDATA_1 / TX0M_DPC2N
BACO mode -- install
Y4
DVPCNTL_MV1 / TX1P_DPC1P
AA5 W5
PBY160808T-121Y-N/2.5A_6 DPC_VDD10#1/DVPDAT15 DVPDATA_9 / TX1M_DPC1N
1.1V(110mA DPC_VDD10) AA6
DPC_VDD10#2/DVPDAT17
+1.0V_VGA +1.1V_DPC_VDD10 AA3
L25 DVPDATA_13 / TX2P_DPC0P
Y2
C229 C237 C238 DVPCNTL_1 / TX2M_DPC0N
10U/6.3V_8 1U/6.3V_4 0.1U/10V_4 U1 AA12
DPC_VSSR#1 / DVPCLK VDDR4 / DPCD_CALR
W1
GPIO15 GPIO20 U3
DPC_VSSR#2 / DVPDAT5
DPC_VSSR#3 / GND
Y6
DPC_VSSR#4 / GND
Seymour PWRCNTL0 PWRCNTL1 V-CORE Access to SCL and SDA is mandatory AA1
DPC_VSSR#5/ DVPCNTL_MV0 DPC
R308 *4.7K_4
on BACO designs for debug purposes R311 *4.7K_4
+3V_DELAY Reserve for DB debug only
L 0 0 0.9V
T40 R1
SCL
T39 R3
SDA I2C
M 0 1 0.95V R291 *150/F_4
C AM26 GPU_CRT_R <22> C
GENERAL PURPOSE I/O R
AK26
GPIO0 RB R292 *150/F_4
H 1 0 1.12V (Default) <16> GPIO0 U6
GPIO_0
<16> GPIO1 GPIO1 U10 AL25
GPIO_1 G GPU_CRT_G <22>
<16> GPIO2 GPIO2 T10 AJ25
GPUT_DATA GPIO_2 GB R293 *150/F_4
TBD 1 1 NA U8
GPIO_3_SMBDATA
GPUT_CLK U7 AH24
GPIO_4_SMBCLK B GPU_CRT_B <22>
GPIO5 T9 AG25
<16> GPIO5 GPIO_5_AC_BATT BB
R117 *0_4 T8 DAC1
<29> GPU_PROCHOT GPIO_6
EXT_LVDS_BLON T7 AH26 HSYNC_COM_R
GPIO_7_BLON HSYNC GPU_HSYNC_COM <22>
<16> GPIO8 GPIO8 P10 AJ27 VSYNC_COM_R
GPIO_8_ROMSO VSYNC GPU_VSYNC_COM <22>
GPIO9 P4
+3V_DELAY <16> GPIO9 GPIO_9_ROMSI
GPIO10 P2
T19 GPIO_10_ROMSCK
GPIO11 N6 AD22 R75 499/F_4
<16> GPIO11 GPIO_11 RSET
R107 *10K_4 GPIO24_TRSTB R101 *10K_4 GPIO12 N5
<16> GPIO12 GPIO_12
GPIO13 N3 AG24 +1.8V_AVDD_Q +1.8V_AVDD_Q
<16> GPIO13 GPIO_13 AVDD
R114 *10K_4 GPIO25_TDI T15 HDMI_HP2 Y9 AE22
GFX_CORE_CNTRL0 GPIO_14_HPD2 AVSSQ
<34> GFX_CORE_CNTRL0 N1
R324 *10K_4 GPIO27_TMS T23 OSC_SPREAD GPIO_15_PWRCNTL_0 +VDDD1
M4 AE23 +VDDD1
VGA_ALERT GPIO_16_SSIN VDD1DI
<29> VGA_ALERT R6 AD23
R335 *10K_4 GPIO28_TDO HPD3 GPIO_17_THERMAL_INT VSS1DI
T16 W10
TEMP_FAIL GPIO_18_HPD3
M2
GPIO_19_CTF Seymour-S3
R322 *10K_4 GPIO26_TCK <34> GFX_CORE_CNTRL1 GFX_CORE_CNTRL1 P8 AM12
BB_EN GPIO_20_PWRCNTL_1 R2 / NC
T17 P7 AK12
GPIO22 GPIO_21_BB_EN R2B / NC
<16> GPIO22 N8
GPIO_23_CLKREQb GPIO_22_ROMCSB C525 22P/50V_4 EVGA-XTALI
N7 AL11
GPIO_23_CLKREQB G2 / NC
AJ11
G2B / NC

1
R120 10K_4 GPIO22 AK10 Y2 R296
GPIO24_TRSTB B2 / NC 27MHZ 10M_6
T18 L6 AL9
GPIO25_TDI JTAG_TRSTB B2B / NC
GPIO22(ROMCS#) T20 L5 DAC2 is NC on Seymour

2
R331 *10K_4 GPIO_23_CLKREQb GPIO26_TCK JTAG_TDI
PD without external VBIOS ROM +3V_DELAY T42 L3
GPIO27_TMS JTAG_TCK C534 EVGA-XTALO
T41 L1 AH12
GPIO28_TDO JTAG_TMS C / NC 22P/50V_4
T43 K4
JTAG_TDO DAC2 Y / NC
AM10
TESTEN AF24 AJ9
T3 TESTEN COMP / NC
R116 10K_4 TEMP_FAIL
For Int Clk 27Mhz
AB13
GENERICA DAC2_VSY
B
W8
GENERICB H2SYNC
AL13 DAC2_VSY <16> 8/25 SI for H/W. B
GENERICC W9 AJ13 DAC2_HSY
<16> GENERICC GENERICC V2SYNC DAC2_HSY <16>
W7
GENERICD
AD10
GENERICE_HPD4 R60 *0_4 +VDDD1
AD19 +VDDD1
VDD2DI / NC R93 *0_4
AC14 AC19
HPD1 VSS2DI / NC
EXT_LVDS_BLON R110 10K_4 +1.8V_VGA
1.8V+R6043(249R)=1.8V/3=0.6V AE20 R73 *0_4 +A2VDD
R295 499/F_4 A2VDD / NC
AE17 R77 *0_4 +1.8V_A2VDD_Q +1.8V_A2VDD_Q
R297 249/F_4 +0.6V_M92_VREFG AC16 A2VDDQ / NC
VREFG
If no contact this pin to LVDS need pull low A2VSSQ
AE19

BLM18PG471SN1D/1A_6 1.8V(75mA DPLL_PVDD) C533 0.1U/10V_4 AG13 R91 *715/F_4 Seymour-S3--NC


R2SET / NC
+1.8V_VGA ROBSON--install
L43
+3V_DELAY C529 DDC/AUX
C526 C532 AE6 <29> GPUT_CLK GPUT_CLK
10U/6.3V_8 1U/6.3V_4 0.1U/10V_4 PLL/CLOCK DDC1CLK GPUT_DATA
AE5 <29> GPUT_DATA
+1.8V_DPLL_PVDD DDC1DATA
AF14
R79 DPLL_PVDD
AE14 AD2
DPLL_PVSS AUX1P
*10K_4 AD4
AUX1N +3V_DELAY
+1.0V_VGA L20 BLM18PG471SN1D/1A_6 +1.0V_DPLL_VDDC AD14 AC11
DPLL_VDDC DDC2CLK
AC13
TESTEN C151 C160 C169 DDC2DATA R102 4.7K_4
1.0V(125mA DPLL_VDDC)
10U/6.3V_8 1U/6.3V_4 0.1U/10V_4 R294 *0_4 EVGA-XTALI AM28 AD13
<2> PCH_CLK_27M XTALIN AUX2P R108 4.7K_4
EVGA-XTALO AK28 AD11
XTALOUT AUX2N
AC22
R80 NC#2/XO_IN
8/25 SI for H/W. AB22
NC#1/XO_IN2 DDCCLK_AUX5P
AE16 Reserve for DB debug only
Ra *10K_4 Seymour uninstall Ra AD16
DDCDATA_AUX5N
to meet AF24 N/C
PBY160808T-121Y-N/2.5A_6 1.8V(20mA TSVDD) AC1 GPU_DDCCLK <22>
DDC6CLK
+1.8V_VGA T4 AC3 GPU_DDCDATA <22>
L44 DPLUS THERMAL DDC6DATA
T2
DMINUS
AD20
C524 C527 C530 NC/DDCCLK_AUX3P
A AC20 A
NC/DDCDATA_AUX3N
R5
10U/6.3V_8 1U/6.3V_4 0.1U/10V_4 +1.8V_TSVDD TS_FDO
AD17
TSVDD
AC17
TSVSS

+1.0V_VGA
<14,17,35> +1.0V_VGA
+1.8V_VGA
352-(&75
<14,17,35> +1.8V_VGA
Seymour-S3
AJ080900T01 +3V_DELAY
FCBGA631-AMD-M92-S2
<16,17> +3V_DELAY
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 1A
Seymour Main
Date: Sunday, September 19, 2010 Sheet 15 of 39
5 4 3 2 1
5 4 3 2 1

AA27
AB24
U17E

PCIE_VSS#1 GND#1 A3
A30
U17F

LVDS CONTROL AB11


16
PCIE_VSS#2 GND#2 VARY_BL RECOMMENDED SETTINGS
AB32 AA13 AB12
AC24
PCIE_VSS#3
PCIE_VSS#4
GND#3 / EVDDQ#2
GND#4 AA16
DIGON CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
AC26 AB10 1 = INSTALL 10K RESISTOR
PCIE_VSS#5 GND#5
AC27 AB15 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
PCIE_VSS#6 GND#6 / EVDDQ#3
AD25 AB6 NA = NOT APPLICABLE
PCIE_VSS#7 GND#7 THEY MUST NOT CONFLICT DURING RESET
D
AD32 PCIE_VSS#8 GND#8 AC9 TXCLK_UP_DPF3P AH20 D
AE27 PCIE_VSS#9 GND#9 AD6 TXCLK_UN_DPF3N AJ19
AF32 PCIE_VSS#10 GND#10 AD8
AG27 AE7 AL21 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
PCIE_VSS#11 GND#11 TXOUT_U0P_DPF2P
AH32 PCIE_VSS#12 GND#12 AG12 TXOUT_U0N_DPF2N AK20
K28 PCIE_VSS#13 GND#13 AH10 Transmitter Power Savings Enable
K32 AH28 AH22 TX_PWRS_ENB GPIO0
L27
PCIE_VSS#14
PCIE_VSS#15
GND#14
GND#15 B10
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N AJ21
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
1
M32 PCIE_VSS#16 GND#16 B12
N25 B14 AL23 PCI Express Transmitter De-emphasis Enable
PCIE_VSS#17 GND#17 TXOUT_U2P_DPF0P TX_DEEMPH_EN GPIO1
N27 B16 AK22
P25
PCIE_VSS#18
PCIE_VSS#19
GND#18
GND#19 B18
TXOUT_U2N_DPF0N 0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)
1
P32 PCIE_VSS#20 GND#20 B20 TXOUT_U3P AK24
R27 B22 AJ23 Enable CLKREQ# Power Management
PCIE_VSS#21 GND#21 TXOUT_U3N BIF_GEN2_EN_A GPIO2 0 - CLKREQ# power management capability is disabled
T25 B24
T32
PCIE_VSS#22
PCIE_VSS#23
GND#22
GND#23 B26 1 - CLKREQ# power management capability is enabled 0
U25 B6 LVTMDP
PCIE_VSS#24 GND#24
U27 PCIE_VSS#25 GND#25 B8
V32 C1 AL15 RSVD GPIO8 0
PCIE_VSS#26 GND#26 TXCLK_LP_DPE3P BIF_VGA_DIS GPIO9 VGA ENABLED 0
W 25 PCIE_VSS#27 GND#27 C32 TXCLK_LN_DPE3N AK14
W 26 E28 RSVD GPIO21 0
PCIE_VSS#28 GND#28
W 27 PCIE_VSS#29 GND#29 F10 TXOUT_L0P_DPE2P AH16
Y25 F12 AJ15 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
PCIE_VSS#30 GND#30 TXOUT_L0N_DPE2N
Y32 PCIE_VSS#31 GND#31 F14
F16 AL17 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0 0 1
GND#32 TXOUT_L1P_DPE1P
GND#33 F18 TXOUT_L1N_DPE1N AK16
F2 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
GND#34
GND#35 F20 TXOUT_L2P_DPE0P AH18
M6 GND#56 GND#36 F22 TXOUT_L2N_DPE0N AJ17 0
N11 F24 RSVD GENERICC 0
GND#57 GND#37 AUD[1] HSYNC AUD[1] AUD[0]
C N12 GND#58 GND#38 F26 TXOUT_L3P AL19 11 C
N13 F6 AK18 AUD[0] VSYNC 0 0 No audio function
GND#59 GND#39 TXOUT_L3N 0 1 Audio for DisplayPort and HDMI if dongle is detected
N16 F8
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
P6 GND#63 GND#43 G31
P9 G8 Seymour-S3
GND#64 GND#44 AJ080900T01
R12 GND#65 GND#45 H14
R15 H17 FCBGA631-AMD-M92-S2
GND#66 GND#46
R17 GND#67 GND#47 H2
R20 GND#68 GND#48 H20
T13 GND#69 GND#49 H6
T16 J27
T18
GND#70
GND#71
GND#50
GND#51 J31 +3V_DELAY AMD RESERVED CONFIGURATION STRAPS
T21 GND#72 GND#52 K11
T6 GND#73 GND#53 K2 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
U15 GND#74 GND#54 K22
U17 K6 <15> GPIO9
GPIO9 R312 *10K_4 THEY MUST NOT CONFLICT DURING RESET
GND#75 GND#55
U20 GND#76 GND#85 T11
U9 R11 GPIO13 R315 *10K_4
GND#77 GND#86 <15> GPIO13
V13 H2SYNC GENERICC
GND#78 GPIO12 R115 *10K_4
V16 GND#79 <15> GPIO12
V18 GND#80
Y10 GPIO11 R333 10K_4 PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
GND#81 <15> GPIO11
Y15 GND#82
Y17 GND#83 VSS_MECH#1 A32 THEY MUST NOT CONFLICT DURING RESET
Y20 GND#84 VSS_MECH#2 AM1
VSS_MECH#3 AM32
GPIO21_BB_EN
B B

Seymour-S3
AJ080900T01 +3V_DELAY
FCBGA631-AMD-M92-S2
Power Up/Down Sequence Memory Aperture size
GPIO0 R307 *10K_4
GPIO9 GPIO13 GPIO12 GPIO11 <15> GPIO0
GPIO1 R98 *10K_4
<15> GPIO1
BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0 GPIO2 R106 *10K_4
<15> GPIO2
0 128M 0 0 0 <15> GPIO8 GPIO8 R113 *10K_4

+VGA_CORE VDDC R99 *10K_4


0 256M 0 0 1 <15> GENERICC
GPIO22 R122 *10K_4
<15> GPIO22
0 64M 0 1 0 <15> GPIO5
GPIO5 R321 10K_4
+VGA_CORE VDDCI R78 *10K_4
0 32M 0 1 1 <15> DAC2_VSY
R76 *10K_4
<15> DAC2_HSY

+1.5V_VGA VDDR1 0 512M 1 0 0


A 0 1G 1 0 1 <15,17> +3V_DELAY
+3V_DELAY A

+3.3V_Delay VDDR3
0 2G 1 1 0
+1.8V_VGA VDDR4 0 4G 1 1 1 352-(&75
+1.8V_VGA VDD_CT
It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.
4XDQWD&RPSXWHU,QF
20ms 20ms Size Document Number Rev
Custom 1A
Seymour GND / LVDS/ Straps
Date: Sunday, September 19, 2010 Sheet 16 of 39
5 4 3 2 1
5 4 3 2 1

+1.5V_VGA 1.5V ( DDR3, MVDDQ = 1.5V@2.0A)


U17D

MEM I/O
PCIE
PCIE_VDDR--PCI-E I/O power. 1.8 V 5%

+1.8V_PCIE_VDDR
+1.8V_PCIE_VDDR

1.8V(500mA) PBY160808T-221Y-N/2A_6
L18
17
H13 VDDR1#1 PCIE_VDDR#1 AB23 +1.8V_VGA
H16 VDDR1#2 PCIE_VDDR#2 AC23
H19 VDDR1#3 PCIE_VDDR#3 AD24
C404 C327 C330 C331 C336 J10 AE24 C242 C150 C154 C136 C135 C230 C137 C162
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 VDDR1#4 PCIE_VDDR#4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3VS_6
J23 VDDR1#5 PCIE_VDDR#5 AE25
J24 VDDR1#6 PCIE_VDDR#6 AE26
D J9 VDDR1#7 PCIE_VDDR#7 AF25 D
K10 VDDR1#8 PCIE_VDDR#8 AG26
K23 VDDR1#9
K24 +1.0V_VGA
VDDR1#10
K9 VDDR1#11 PCIE_VDDC#1 L23
C645 C624 C395 L11 L24 +1.0V_PCIE_VDDC
10U/6.3VS_6 10U/6.3VS_6 VDDR1#12 PCIE_VDDC#2 0_8
10U/6.3VS_6 L12 VDDR1#13 PCIE_VDDC#3 L25 1.0V(2.0A)
L13 L26 +1.0V_PCIE_VDDC L26
VDDR1#14 PCIE_VDDC#4
L20 VDDR1#15 PCIE_VDDC#5 M22
L21 VDDR1#16 PCIE_VDDC#6 N22
L22 N23 C304 C280 C269 C294 C260 C299 C319 C307
+1.8V_VDD_CT VDDR1#17 PCIE_VDDC#7 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3VS_6
1.8V(110mA VDD_CT) PCIE_VDDC#8 N24
PCIE_VDDC#9 R22
L22 PBY160808T-121Y-N/2.5A_6 +1.8V_VDD_CT T22
+1.8V_VGA LEVEL PCIE_VDDC#10
PCIE_VDDC#11 U22
TRANSLATION V22
C163 C167 C241 C168 C249 PCIE_VDDC#12 +VGA_CORE
AA20 VDD_CT#1 VDDC+VDDCI
Gated 3.3V 10U/6.3VS_6 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 AA21 VDD_CT#2 0.85~1.1V(15A peak )( Ripple < 87.2mV)
60mA by AB20 VDD_CT#3 VDDC#1 AA15
+3V_DELAY AB21 CORE N15
VDDC VDD_CT#4 VDDC#2
VDDC#3 N17
+3V_VGA L19 0_6 +3V_DELAY Seymour-S3 R13 C86 C92 C293 C276 C91 C268 C277 C519
VDDC#4

POWER
R16 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_41U/6.3V_4 1U/6.3V_4 10U/6.3VS_6
VDDC#5
VDD_R3 --IO power for AA17 VDDR3#1 VDDC#6 R18
3.3 V pins (e.g. C228 C226 C279 C243 AA18 I/O Y21
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 VDDR3#2 VDDC#7
10U/6.3VS_6 AB17 T12
GPIOs). 3.3 V 5% VDDR3#3 VDDC#8
AB18 VDDR3#4 VDDC#9 T15
VDDC#10 T17
V12 VDDR4#1 / VDDR5 VDDC#11 T20
+VDDR4 Y12 U13 C85 C323 C262 C305 C272 C257 C258
VDDR4#2 VDDC#12 1U/6.3V_4 2.2U/6.3V_4 1U/6.3V_4 10U/6.3V_8 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
U12 VDDR4#3 / VDDR5 VDDC#13 U16
C
+1.8V_VGA L23 +VDDR4 U18 C
VDDC#14
AA11 NC#1 / VDDR4 VDDC#15 V21
PBY160808T-121Y-N/2.5A_6 C209 C212 C256 Y11 V15
T14 DVCLK / VDDR4 VDDC#16
1.8V(170mA VDDR4) 10U/6.3VS_6 1U/6.3V_4 0.1U/10V_4 V17
VDDC#17
V11 NC#3 / VDDR5 VDDC#18 V20
U11 NC / VDDR5 VDDC#20 Y13
Y16 C259 C286 C275 C87 C79 C247
VDDC#21 1U/6.3V_4 2.2U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
Y18
VDDC#22
1.8V(75mA MPV18) VDDC#23 /BIF_VDDC
R21
U21
L50 BLM18PG471SN1D/1A_6 MPV18 MEM CLK VDDC#19/BIF_VDDC
+1.8V_VGA
L17
VDDRHA
C600 C602 L16 ISOLATED
1U/6.3V_4 0.1U/10V_4 VSSRHA CORE I/O C81 C88 C83 C521 C520 C82
M13 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
PLL VDDCI#1
1.8V(40mA PCIE_PVDD) VDDCI#2
M15
+1.8V_PCIE_VDDR AM30 M16
PCIE_PVDD VDDCI#3
1.8V(90mA SPV18) VDDCI#4
M17
M18
L27 PBY160808T-121Y-N/2.5A_6 SPV18 MPV18 VDDCI#5
+1.8V_VGA 8/25 SI for SMT. L8
MPV18 VDDCI#6
M20 Note1.
M21
VDDCI#7 BIF_VDDC R112 0_4
N20 +VGA_CORE
C317 C295 SPV18 VDDCI#8
1.0V_VGA(100mA SPV10) H7
SPV18
1U/6.3V_4 0.1U/10V_4 Ra
L29 BLM18PG471SN1D/1A_6 +1.0V_VGA_SPV10 H8
+1.0V_VGA SPV10
J7
C337 C332 C328 SPVSS 0_8
0.95V~1.1V(2A VDDCI)
10U/6.3VS_6 0.1U/10V_4 1U/6.3V_4 +VDDCI L24
+VGA_CORE
B BACK BIAS B

M11 C329 C313 C306 C265 C266 C315


+5V BBP#1 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
<11,21,22,23,25,28,30,36> +5V M12
+3V BBP#2
<2,3,7,8,9,10,11,12,13,14,20,21,22,23,24,25,27,28,29,30,33,34,36> +3V
+1.0V_VGA
<14,15,35> +1.0V_VGA
+3V_VGA
<34> +3V_VGA
+VGA_CORE Seymour-S3
<34> +VGA_CORE
AJ080900T01
FCBGA631-AMD-M92-S2

^KD +5V +5V


Q10 Q27
+3V <34> PX_MODE1 *AO3416 *AO3416
+3V
3

R337 R336 +1.0V_VGA 1 3 3 1


R330 *1K_4 *1K_4
*10K_4 BIF_VDDC
not stuff PX_EN 2 Q41

2
3

R323 PX_EN## PX_EN#


*2N7002E *100K_4 Q25 PX_EN# Q9 Q26
*AO3416 *AO3416
R334 *0_4 8/25 SI for AMD. 2 *2N7002E C325 C287 C297 C270 C271
<34> PX_MODE
1
3

+VGA_CORE 1 3 3 1 *22U/6.3VS_8
3

*10U/6.3VS_6 *2.2U/6.3V_4
*10U/6.3VS_6 *2.2U/6.3V_4
<18> PX_EN 2 2 Q28 2 Q30
1

2
<9,29> EC_PW ROK 2 *2N7002E *2N7002E PX_EN##
Q29
R94 Q31 *2N7002E
*2N7002E
R500
1

A +3V A
*5.1K_4
1

PX_MODE PX_MODE1 C592

8/25 SI for AMD. *0_4


5

*0.1U/10V_4 Note1.
2
352-(&75
<2,10,29,34,35> DGPU_PW ROK
4 BACO_EN 1. No BACO Support :BIF_VDDC shorts with VDDC (Install Ra)
PX_MODE
4XDQWD&RPSXWHU,QF
1
PX_EN = 0, for Normal Operation 2. BACO Support: Refer to the BACO reference
PX_EN = 1, for BACO MODE U18
schematics/Application note for detail about BIF_VDDC Rail
3

*TC7SH08FU
if BACO is Supported (Uninstall Ra) Size Document Number Rev
Custom 1A
Seymour_Power_and_NC
Date: Sunday, September 19, 2010 Sheet 17 of 39
5 4 3 2 1
5 4 3 2 1

<19>
<19>

<19>
VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_RAS1#
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
K27
J29
H30
H32
U17C

DQA_0
DQA_1
DQA_2
MAA_0
MAA_1
MAA_2
K17
J20
H23
G23
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
18
<19> VMA_RAS1# DQA_3 MAA_3
VMA_DQ4 G29 G24 VMA_MA4
VMA_CAS0# VMA_DQ5 DQA_4 MAA_4 VMA_MA5
<19> VMA_CAS0# F28 DQA_5 MAA_5 H24
<19> VMA_CAS1# VMA_CAS1# VMA_DQ6 F32 J19 VMA_MA6
VMA_DQ7 DQA_6 MAA_6 VMA_MA7
F30 DQA_7 MAA_7 K19

MEMORY INTERFACE
<19> VMA_WE0# VMA_WE0# VMA_DQ8 C30 J14 VMA_MA8
VMA_WE1# VMA_DQ9 DQA_8 MAA_8 VMA_MA9
D <19> VMA_WE1# F27 DQA_9 MAA_9 K14 D
VMA_DQ10 A28 J11 VMA_MA10
VMA_CS0# VMA_DQ11 DQA_10 MAA_10 VMA_MA11
<19> VMA_CS0# C28 DQA_11 MAA_11 J13
VMA_DQ12 E27 H11 VMA_MA12
VMA_CS1# VMA_DQ13 DQA_12 MAA_12 VMA_BA2
<19> VMA_CS1# G26 DQA_13 MAA_13/BA2 G11
VMA_DQ14 D26 J16 VMA_BA0
VMA_CKE0 VMA_DQ15 DQA_14 MAA_14/BA0 VMA_BA1
<19> VMA_CKE0 F25 DQA_15 MAA_15/BA1 L15
<19> VMA_CKE1 VMA_CKE1 VMA_DQ16 A25
VMA_DQ17 DQA_16 VMA_DM0
C25 DQA_17 DQMA_0 E32
<19> VMA_CLK0 VMA_CLK0 VMA_DQ18 E25 E30 VMA_DM1
VMA_CLK0# VMA_DQ19 DQA_18 DQMA_1 VMA_DM2
<19> VMA_CLK0# D24 DQA_19 DQMA_2 A21
VMA_DQ20 E23 C21 VMA_DM3
VMA_CLK1 VMA_DQ21 DQA_20 DQMA_3 VMA_DM4
<19> VMA_CLK1 F23 DQA_21 DQMA_4 E13
<19> VMA_CLK1# VMA_CLK1# VMA_DQ22 D22 D12 VMA_DM5
VMA_DQ23 DQA_22 DQMA_5 VMA_DM6
F21 DQA_23 DQMA_6 E3
VMA_WDQS[7..0] VMA_DQ24 E21 F4 VMA_DM7
<19> VMA_WDQS[7..0] DQA_24 DQMA_7
VMA_DQ25 D20
VMA_RDQS[7..0] VMA_DQ26 DQA_25 VMA_RDQS0
<19> VMA_RDQS[7..0] F19 DQA_26 RDQSA_0 H28
VMA_DQ27 A19 C27 VMA_RDQS1
VMA_DM[7..0] VMA_DQ28 DQA_27 RDQSA_1 VMA_RDQS2
<19> VMA_DM[7..0] D18 DQA_28 RDQSA_2 A23
VMA_DQ29 F17 E19 VMA_RDQS3
VMA_DQ[63..0] VMA_DQ30 DQA_29 RDQSA_3 VMA_RDQS4
<19> VMA_DQ[63..0] A17 DQA_30 RDQSA_4 E15
VMA_DQ31 C17 D10 VMA_RDQS5
VMA_MA[13..0] VMA_DQ32 DQA_31 RDQSA_5 VMA_RDQS6
<19> VMA_MA[13..0] E17 DQA_32 RDQSA_6 D6
VMA_DQ33 D16 G5 VMA_RDQS7
VMA_DQ34 DQA_33 RDQSA_7
F15 DQA_34
<19> VMA_BA0 VMA_BA0 VMA_DQ35 A15 H27 VMA_WDQS0
VMA_BA1 VMA_DQ36 DQA_35 W DQSA_0 VMA_WDQS1
<19> VMA_BA1 D14 DQA_36 W DQSA_1 A27
VMA_BA2 VMA_DQ37 F13 C23 VMA_WDQS2
<19> VMA_BA2 DQA_37 W DQSA_2
VMA_DQ38 A13 C19 VMA_WDQS3
VMA_DQ39 DQA_38 W DQSA_3 VMA_WDQS4
C C13 DQA_39 W DQSA_4 C15 C
VMA_DQ40 E11 E9 VMA_WDQS5
VMA_DQ41 DQA_40 W DQSA_5 VMA_WDQS6
A11 DQA_41 W DQSA_6 C5
VMA_DQ42 C11 H4 VMA_WDQS7
VMA_DQ43 DQA_42 W DQSA_7
F11 DQA_43
support 1Gbit VMA_DQ44 A9 L18 VMA_ODT0
VMA_DQ45 DQA_44 ODTA0 VMA_ODT1
VRAM ( 64M X 16 ) C9 DQA_45 ODTA1 K16
VMA_DQ46 F9
VMA_DQ47 DQA_46 VMA_CLK0
D8 DQA_47 CLKA0 H26
DIVIDER RESISTORS GDDR5 DDR3 VMA_DQ48 E7 H25 VMA_CLK0# DRAM_RST R129 10_4 DRAM_RST_M
DQA_48 CLKA0B DRAM_RST_M <19>
VMA_DQ49 A7 R132 51_4
VMA_DQ50 DQA_49 VMA_CLK1
C7 DQA_50 CLKA1 G9
MVREF TO 1.8V (Ra) 40.2R 40.2R VMA_DQ51 F7 H9 VMA_CLK1#
VMA_DQ52 DQA_51 CLKA1B R128 C335
A5 DQA_52
VMA_DQ53 E5 G22 VMA_RAS0#
VMA_DQ54 DQA_53 RASA0B VMA_RAS1# 5.1K_4 120P/50V_4
MVREF TO GND (Rb) 100R 100R VMA_DQ55
C3 DQA_54 RASA1B G17
E1 DQA_55
VMA_DQ56 G7 G19 VMA_CAS0#
+1.5V_VGA VMA_DQ57 DQA_56 CASA0B VMA_CAS1#
G6 DQA_57 CASA1B G16 8/25 SI for AMD.
VMA_DQ58 G1
VMA_DQ59 DQA_58 VMA_CS0#
G3 DQA_59 CSA0B_0 H22
PLACE MVREFD DIVIDERS VMA_DQ60 J6 DQA_60 CSA0B_1 J22
R160 AND CAPS CLOSE TO ASIC VMA_DQ61 J1
VMA_DQ62 DQA_61 VMA_CS1#
Ra J3 DQA_62 CSA1B_0 G13
40.2/F_4 VMA_DQ63 J5 K13
DQA_63 CSA1B_1
MVREFD K26 K20 VMA_CKE0
MVREFDA CKEA0 VMA_CKE1
J26 MVREFSA CKEA1 J17
+1.5V_VGA +1.5V_VGA
R384 243/F_4 J25 G25 VMA_WE0#
B
C326 R156 R131 5.1K_4 MEM_CALRN0 W EA0B VMA_WE1# B
K7 NC/TESTEN#2 W EA1B H10

0.1U/10V_4
Rb 100/F_4 R175 R127 150/F_4 J8 AB16 PX_EN
Ra K25
MEM_CALRP1/DPC_CALR PX_EN
G14
PX_EN <17>
40.2/F_4 R385 243/F_4 MEM_CALRP0 RSVD#2 VMA_MA13
RSVD#3 G20
DRAM_RST L10
MVREFS DRAM_RST
CLKTESTA K8
CLKTESTB CLKTESTA
L7 CLKTESTB
C333 R167
Rb Seymour-S3
0.1U/10V_4 100/F_4 AJ080900T01
C316 C591 FCBGA631-AMD-M92-S2
*0.1U/10V_4 *0.1U/10V_4
8/25 SI for SMT.

R118 R314
*51.1/F_4 *51.1/F_4

route 50ohms
single-ended/100ohms diff
and keep short
A +1.5V_VGA A
<17,19,34> +1.5V_VGA Debug only, for clock observation,
if not needed, DNI

352-(&75
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 1A
Seymour/MEM_Interface
Date: Sunday, September 19, 2010 Sheet 18 of 39
5 4 3 2 1
5 4 3 2 1

VMA_MA[13..0]

19
<18> VMA_MA[13..0]
1GB DDR3
<18> VMA_DQ[63..0]
<18> VMA_DM[7..0] <18> VMA_WDQS[7..0]
<18> VMA_RDQS[7..0]
U7 U19 U6 U20

VREFC_VMA1 M9 E4 VMA_DQ20 VREFC_VMA2 M9 E4 VMA_DQ27 VREFC_VMA3 M9 E4 VMA_DQ38 VREFC_VMA4 M9 E4 VMA_DQ48


VREFD_VMA1 VREFCA DQL0 VMA_DQ18 VREFD_VMA2 VREFCA DQL0 VMA_DQ31 VREFD_VMA3 VREFCA DQL0 VMA_DQ32 VREFD_VMA4 VREFCA DQL0 VMA_DQ52
H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8
F3 VMA_DQ22 F3 VMA_DQ25 F3 VMA_DQ36 F3 VMA_DQ53
VMA_MA0 DQL2 VMA_DQ17 VMA_MA0 DQL2 VMA_DQ29 VMA_MA0 DQL2 VMA_DQ34 VMA_MA0 DQL2 VMA_DQ54
N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9
VMA_MA1 P8 H4 VMA_DQ23 VMA_MA1 P8 H4 VMA_DQ30 VMA_MA1 P8 H4 VMA_DQ39 VMA_MA1 P8 H4 VMA_DQ49
VMA_MA2 A1 DQL4 VMA_DQ16 VMA_MA2 A1 DQL4 VMA_DQ28 VMA_MA2 A1 DQL4 VMA_DQ33 VMA_MA2 A1 DQL4 VMA_DQ51
P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9
VMA_MA3 N3 G3 VMA_DQ21 VMA_MA3 N3 G3 VMA_DQ24 VMA_MA3 N3 G3 VMA_DQ37 VMA_MA3 N3 G3 VMA_DQ50
VMA_MA4 A3 DQL6 VMA_DQ19 VMA_MA4 A3 DQL6 VMA_DQ26 VMA_MA4 A3 DQL6 VMA_DQ35 VMA_MA4 A3 DQL6 VMA_DQ55
P9 H8 P9 H8 P9 H8 P9 H8
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
P3 P3 P3 P3
D VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 D
R9 R9 R9 R9
VMA_MA7 A6 VMA_DQ0 VMA_MA7 A6 VMA_DQ15 VMA_MA7 A6 VMA_DQ43 VMA_MA7 A6 VMA_DQ60
R3 D8 R3 D8 R3 D8 R3 D8
VMA_MA8 A7 DQU0 VMA_DQ5 VMA_MA8 A7 DQU0 VMA_DQ10 VMA_MA8 A7 DQU0 VMA_DQ44 VMA_MA8 A7 DQU0 VMA_DQ58
T9 C4 T9 C4 T9 C4 T9 C4
VMA_MA9 A8 DQU1 VMA_DQ1 VMA_MA9 A8 DQU1 VMA_DQ13 VMA_MA9 A8 DQU1 VMA_DQ40 VMA_MA9 A8 DQU1 VMA_DQ63
R4 C9 R4 C9 R4 C9 R4 C9
VMA_MA10 A9 DQU2 VMA_DQ4 VMA_MA10 A9 DQU2 VMA_DQ9 VMA_MA10 A9 DQU2 VMA_DQ47 VMA_MA10 A9 DQU2 VMA_DQ56
L8 C3 L8 C3 L8 C3 L8 C3
VMA_MA11 A10/AP DQU3 VMA_DQ2 VMA_MA11 A10/AP DQU3 VMA_DQ12 VMA_MA11 A10/AP DQU3 VMA_DQ42 VMA_MA11 A10/AP DQU3 VMA_DQ61
R8 A8 R8 A8 R8 A8 R8 A8
VMA_MA12 A11 DQU4 VMA_DQ7 VMA_MA12 A11 DQU4 VMA_DQ8 VMA_MA12 A11 DQU4 VMA_DQ45 VMA_MA12 A11 DQU4 VMA_DQ57
N8 A12/BC DQU5
A3 N8 A12/BC DQU5
A3 N8 A12/BC DQU5
A3 N8 A12/BC DQU5
A3
VMA_MA13 T4 B9 VMA_DQ3 VMA_MA13 T4 B9 VMA_DQ14 VMA_MA13 T4 B9 VMA_DQ41 VMA_MA13 T4 B9 VMA_DQ62
A13 DQU6 VMA_DQ6 A13 DQU6 VMA_DQ11 A13 DQU6 VMA_DQ46 A13 DQU6 VMA_DQ59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA

M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3


<18> VMA_BA0 BA0 VDD#B3 VMA_BA1 BA0 VDD#B3