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Virtuoso Multi-Mode Simulation

with Spectre Platform


Comprehensive analyses for robust design and verification

The Cadence Spectre circuit simulation platform, built on an advanced infrastructure, combines
industry-leading simulation engines to deliver a complete design and verification solution. It meets
the changing simulation needs of designers by preserving design intent as they progress through
the design cyclefrom architectural exploration, to analog and RF block-level development with
flexible and reliable abstraction, to final analog and mixed-signal full-chip verification for increased
productivity and throughput.

Virtuoso Multi-Mode
Simulation Spectre
The Virtuoso Multi-Mode Simulation
release delivers an industry-leading
Spectre circuit simulation platform for Spectre APS Spectre RF Spectre XPS
a comprehensive design and verifi- Accurate, high- Analog and RF-IC High-speed, high-
cation solution that provides SPICE, performance noise analysis capacity full-chip
simulation analysis
radio frequency (RF), FastSPICE, and
mixed-signal simulators in a unique
shared licensing package. This unified Spectre Infrastructure
solution preserves the design intent Common infrastructure, advanced simulation database,
and delivers scalable performance and versatile front-end parser, robust device library
capacity through reliable abstraction,
providing robust verification of analog, Spectre Applications
RF, memory, custom digital, and Comprehensive coverage, integrated with Virtuoso, LEA,
mixed-signal silicon realization. Liberate, Allegro, and Encounter Timing System technologies

The Spectre simulation platform


delivers a variety of analyses and Figure 1. Spectre offers a complete analog-mixed signal, and custom
measurements in a flexible access digital-simulation platform

model to provide designers with the


Spectre Accelerated Parallel Spectre eXtensive Partitioning
appropriate simulation technology
Simulator (APS) delivers Simulator (XPS) is the
tailored for each abstraction level of
high-precision SPICE and scalable next-generation FastSPICE simulator
the verification flow.
multi-core simulation performance providing a high-performance
Spectre Circuit Simulator provides for complex and large pre- and and high-capacity verification and
a high-precision SPICE simulation post-layout of analog and RF IC signoff of complex full-chip designs
of pre- and post-layout analog/RF designs
UltraSim Full-Chip Simulator for
designs with a comprehensive set of
Spectre RF provides a compre- faster convergence and signoff of
analyses for faster convergence
hensive set of RF analyses for pre- post-layout designs at the chip level
and post-layout RF integrated circuit
(IC) design
Virtuoso Multi-Mode Simulation with Spectre Platform

AMS Designer delivers mixed-signal Productivity devices dominated by parasitics. Spectre


design and verification through simulation platform meets the SoC design
Provides scalable performance-capacity
reliable abstraction and with a faster verification challenge with a combination
transistor-level verification of a wide
convergence of unique parasitic stitching techniques
range of analog, custom-digital,
and an accurate frequency-based parasitic
Spectre delivers a common infrastructure memory, and mixed-signal designs
reduction algorithm. This approach
and an advanced database. It is fully
Offers flexible and reliable design delivers the performance and capacity for
integrated into Cadences Virtuoso
abstraction for analog and post-layout verification of large designs.
Analog Design Environment and Incisive
digital-centric mixed-signal design It also provides an optimized power-net
design and verification flow. The comple-
flows, delivering faster simulation simulation technique and methodology
mentary feature sets of these simulation
turnaround time for analysis of effects such as electromi-
engines deliver improved productivity
gration IR drop, signal integrity, timing,
and facilitate adoption as designs move
Features and substrate degradation.
through the architecture, implementation,
and verification stagesand as simulation Silicon-accurate modeling Design reliability
needs change (see Figure 1).
Spectre offers the same device model As gate-oxide thickness and dimen-
equations across all simulators, elimi- sions of scale shrink in IC design,
Benefits
nating model correlation issues and reliability problems occur and need to be
Design quality and convergence enabling faster convergence on simulation considered early in the design process.
results. Common equations also ensure Some of the more problematic issues
Uses silicon-accurate common device
that new device model updates are include negative bias temperature insta-
models universally supported by all
available with all the simulators at the bility (NBTI) and hot carrier injection
foundry process design kits (PDKs)
same time. (HCI). These can lead to problems such as
Supports shared syntax and performance degradation, burn-in yield
abstractions across all simulation Greater performance and capacity loss, leakage current increase leading to
engines and minimizes translation when Spectre APS, Spectre RF, and Spectre increased power consumption, and even
moving among design domains XPS simulation engines provide the best functional failure of ICs.

Features tight integration with the combination of performance and capacity The Spectre simulation platform provides
Virtuoso Analog Design Environment, for verification of analog/RF and mixed- a full-chip native reliability simulation
with common use-model, cross- signal design without sacrificing accuracy and analysis solution, enabling designers
probing, and back-annotation of results. to consider reliability effects in the early
capabilities Language and netlist support stages of design and ensure silicon
realization that has sufficient margins
Features tight integration into the The Spectre simulation platform supports to function correctly over the products
Incisive Logic Design Environment, a variety of design abstraction methods. entire lifetime.
with common-use model, It is compatible with most commonly
debugging, waveform viewing, and used SPICE input decks for both pre- and Advanced analog and RF circuit
languagesupport post-layout. It can natively read Spectre, analysis techniques
Provides a proven, comprehensive suite SPICE, and Verilog-A netlist formats The advanced architecture of the Spectre
of high-precision analyses with a simple and device models. It also supports simulation platform uses proprietary
use model, delivering accurate results standard language inputs in Verilog-AMS, techniquesincluding adaptive time step
VHDL-AMS, Verilog-A, Verilog, and control, sparse matrix solving, and multi-
Offers post-layout simulation and VHDLformats. core processingto provide high perfor-
signoff analysis to ensure first-pass
Post-layout simulation mance while maintaining signoff accuracy.
silicon realization success
It bridges the gap between manufactur-
Scalability in performance Verification for post-layout designs has ability and time to market at advanced
become increasingly important with process nodes by providing a compre-
Delivers simulation performance for advanced nanometer processes. For hensive set of statistical analysis tools
complex and large analog/RF, custom larger designs such as analog subsystems tailored to IC design. Tight integration
digital, and mixed-signal designs and full chips, the post-layout parasitics with the Virtuoso Analog Design
Offers high-performance parallel data is growing exponentially at 65nm Environment offers a user-friendly inter-
simulation by harnessing the power andbelow. active setup and advanced visualization of
of clusters of multi-core compute statistical results.
The Spectre simulation platform offers
platforms to deliver peak performance a flexible solution for SPICE-level post- The Spectre simulation platform provides
layout simulations of complex and large the flexibility to combine design IP from
designswith tens of thousands of circuit the different sources and abstraction

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Virtuoso Multi-Mode Simulation with Spectre Platform

levels necessary for the design and verifi- Bipolar junction transistor (BJT) models,
cation of todays advanced mixed-signal including latest versions of VBIC,
SoCs. It accepts designs in combina- HICUM L0, HICUM L2, Mextram, HBT,
tions of various hardware description and Gummel-Poon models
languages, allowing analog bottom-up
GaAS MESFET models, includes latest
and digital top-down design methodol-
versions of GaAs, TOM2, TOM3,
ogies to link and enable complete analog/
andAngelov
mixed-signal full-chip verification.
Rensselaer Polytechnic Institute
Specifications (RPI)s Poly and Amorphous Silicon
Thin-Filmmodels
Comprehensive device models
Diode, JFET, FinFET, and flash
MOSFET models, including latest
cellmodels
versions of BSIM3, BSIM4, PSP, HISIM,
MOS9, MOS11, and EKV Verilog-A compact device models

Silicon-on-insulator (SoI), including Specialized reliability models (AgeMOS)


latest versions of BTASOI, SSIMSOI for HCI and NBTI analysis
BSIMSOI, BSIMSOI PD, and BSIM-IMG
Platform support
High-voltage MOSFET models,
x86 32-bit: Redhat Enterprise V5 and
including latest versions of HVMOS,
V6, SUSE Linux 9 and 10
LDMOS, and HiSim_HV
x86 64-bit: Redhat Enterprise V4, V5,
TMI models from TSMC
and V6, SUSE Linux 9 and 10

Sun Solaris 10

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Virtuoso Multi-Mode Simulation with Spectre Platform

Spectre Circuit Simulator


The Spectre Circuit Simulator is an
industry-proven, fast, SPICE-accurate and
RF simulator for tough analog RF, mixed-
signal circuit simulation, and library and
IP characterization. It is tightly integrated
with the Virtuoso custom design platform
and provides a comprehensive set of
detailed transistor-level analyses in
multiple domains for faster convergence
on design goals. Its superior advanced
architecture allows for low memory
consumption and high-capacity analysis.

Benefits
Provides high-performance,
high-capacity SPICE-level analog and RF
simulation with out-of-the-box tuning
for accuracy and faster convergence Figure 2: Spectre Circuit Simulator delivers significant performance and capacity for accurate analog
simulation.
Facilitates the tradeoff between
accuracy and performance through
Delivers fast interactive simulation Comprehensive statistical analysis
user-friendly simulation setup
setup, cross-probing, visualization, and
applicable to the most complex analog The Spectre Circuit Simulator bridges the
post-processing of simulation results
and custom-digital ICs gap between manufacturability and time
through tight integration with the
to market at advanced process nodes by
Enables accurate and efficient Virtuoso Analog Design Environment
providing a comprehensive set of statis-
post-layout simulation
Ensures higher design quality using tical analysis tools tailored to IC design.
Supports out-of-the-box S-Parameter silicon-accurate, industry-standard, Advanced Monte Carlo algorithms enable
models, enabling simulation of complex foundry-certified device models shared smart selection of process and design
n-port devices across the simulation engines parameters to characterize the yield with
significantly reduced simulation runs. The
Delivers signal integrity analysis
Features DC Match capability efficiently analyzes
capability with an advanced local process mismatch effects and
transmission line library and graphical Production-proven circuit simulation identifies the yield-limiting devices and
editor techniques parameters. Tight integration between
Provides a platform to measure and The Spectre Circuit Simulator uses propri- the Spectre Circuit Simulator and the
analyze system-level performance etary techniquesincluding adaptive Virtuoso Analog Design Environment
metric time step control, sparse matrix solving, offers user-friendly interactive setup
and multi-processing of MOS models and advanced visualization of statistical
Performs application-specific analysis results.
to provide high performance while
of RF performance parameters (spectral
maintaining signoff accuracy. It includes
response, gain compression, inter- Transient noise analysis
native support for both Spectre and
modulation distortion, impedance
SPICE syntax, giving users the flexibility The Spectre Circuit Simulator provides
matching, stability, and isolation)
to use Spectre technology for any design transient noise analysis for accurate
Offers advanced statistical analysis flow without worrying about the design calculation of the large signal noise in
to help design companies improve format. Additionally, it converges to nonlinear non-periodic circuits. All noise
the manufacturability and yield of ICs results that are silicon-accurate by types are supported, including thermal,
at advanced process nodes without modeling extensive physical effects in shot, and flicker.
sacrificing time to market devices for deep sub-micron processes.

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Virtuoso Multi-Mode Simulation with Spectre Platform

Built-in Verilog-A and MDL Rapid IP2 and IP3 calculation based on netic simulations and include state-of-
perturbation technology the-art descriptions of dielectric and
The Spectre Circuit Simulator offers
conductor losses, delivering accurate
design abstraction for faster convergence Periodic noise analysis for the accurate
models, tightly integrated into Virtuoso
on results, including behavioral modeling calculation of noise in non-linear time
ADE. An intuitive and easy-to-use
capabilities in full compliance with variant circuits with detailed analysis
graphical editor gives the user the ability
Verilog-A 2.0. The compiled Verilog-A options including modulated noise,
to accurately define and graphically
implementation is optimized for compact sampled noise, and jitter
capture the substrates.
device models offering comparable
Full spectrum periodic noise provides a
performance to built-in device models. Wireless Analysis
fast and silicon-accurate Pnoise analysis
In addition to supporting standard SPICE for circuits with sharp transitions The modern mobile platform with
measurement functions (.measure), exponentially evolving wireless standards
Noise and distortion summary to
it offers a measurement description is increasing the complexity of wireless
identify the contribution of each device
language (MDL) to automate cell and RFIC designs. To meet specification
to the total output noise, harmonic, or
library characterization. Spectre MDL requirements and productivity goals,
inter-modulation distortion
enables the designer to post-process the designers must evaluate the system-level
results and tune the simulator to provide Small signal analysis includes AC, performance metrics in an integrated,
the best performance/accuracy tradeoff transfer function, S-Parameters, and automated, and easy-to-use simulation-
for a specific measurement. stability based on a periodic or quasi- based flow.
periodic operating point
Advanced device modeling and Spectre RF wireless analysis feature
support Monte Carlo, corner-case, and provides a fully automated flow integrated
parametric sweep analysis in Virtuoso ADE, enabling the designer
The Spectre Circuit Simulator supports
to easily apply the standard-compliant
MOS, BJT, specialty transistor models, Advanced Transmission Line Library
modulation sources and measure the
resistors, capacitors, inductors, trans-
Signal-integrity issues can be very difficult output to calculate system-level perfor-
formers and magnetic cores, lossy and
and time consuming to identify, analyze, mance. The simulation is based on an
lossless transmission lines, independent
and resolve for high-speed designs. The advanced, accurate, and fast envelope-
and controlled voltage and current
Spectre RF rftline (RF transmission line) following algorithm in Spectre RF.
sources, and Z and S domain sources.
library enables the designer to perform The wire analysis is designed with the
The Spectre Circuit Simulator provides a signal-integrity analysis of the design in RFIC designer in mind. It provides an
user-defined compiled model interface context of the package and PCB trace. automated setup of simulation parameters
(CMI). It allows for the rapid inclusion of Spectre rfTlineLib provides a compre- and standard-specific post-processing,
user-defined models for a model once, hensive set of multi-layer transmission eliminating the hassle and tedious nature
use everywhere capability. It offers a lines and models. Spectre rftline models of working with changing wireless
curve tracer analysis capability for rapid are based on rigorous 2-D electromag- standard sources. Spectre RF wireless
model development and debugging.

RF simulation
Spectre RF, an option to the Spectre
Circuit Simulator, provides a set of
comprehensive RF analyses built on two
production-proven simulation engines:
harmonic balance and shooting-Newton.
Spectre RF supports all industry-standard
models.

Harmonic balance-based analyses,


optimized for high dynamic range,
high-capacity circuits with distributed
components

Shooting-Newton-based
analysis, optimized for strongly
non-linearcircuits

Advanced fast envelope analysis


supporting all analog and digital Figure 3: Spectre RF rftline library enables accurate modeling of transmission line
modulation techniques

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Virtuoso Multi-Mode Simulation with Spectre Platform

analysis provides a rich set of visualization


that includes EVM, BER, and spectrum. A
broad set of wireless standards-compliant
library sources is supported.

Co-simulation with Simulink


The MathWorks Simulink interface to
Spectre Circuit Simulator offers system
and circuit designers a unique integrated
environment for design and verification.
Designers can insert their analog and RF
schematics and post-layout netlist directly
in the system-level block diagram and
run a co-simulation between Simulink
and Spectre technologies. Designers
can reuse the same Simulink testbench
from system-level design to post-layout
verification, minimizing the unnecessary
format conversion while maintaining
accuracy throughout the design flow.

Multi-Mode Simulation toolbox


forMATLAB Figure 4: Spectre RF Wireless Analysis and Visualization: I/Q Signals, Spectrum, Constellation
and Scatter Plot
Multi-Mode Simulation toolbox for
MathWorks MATLAB reads PSF and Specifications Perturbation-based rapid IP2 and IP3
SST2 files directly in MATLAB. Users
benefit from the rich set of MATLAB Comprehensive circuit analyses Noise and distortion summaries
mathematical functions to post-process Wireless analysis
DC, AC, and transient analysis
simulation results from Spectre Circuit
Simulator, Spectre APS, Spectre XPS, Noise, transfer function, and sensitivity Advanced transmission lines library
and AMS Designer. All sweep types analysis Co-simulation with Simulink from
are supported in the toolbox, including MathWorks
Transient noise analysis
Monte Carlo and parametric. Special data
structures are used to store RF signals Native reliability analysis Multi-Mode Simulation toolbox for
and harmonics resulting from PSS and MATLAB from MathWorks
Monte Carlo and parametric statistical
QPSS analysis. Furthermore, the Spectre
support Design inputs/outputs
Simulation toolbox complements the rich
MATLAB libraries with communication Full support for sweeping analysis and Spectre netlist format
product-specific post-processing functions circuit parameters
SPICE netlist format
such as Fast Fourier Transform, third-order
intercept point, and 1dB gain compression Built-in measurement description
Verilog-A 2.0
point. language
S-Parameter data files
Harmonic balance analysis and
Post-layout simulation
shooting-Newton analysis PSF waveform format
The Spectre Circuit Simulator enables
analog and RF block and subsystem
Periodic and quasi-periodic steady Platform support
state analysis (PSS and QPSS) based on
post-layout verification at near the speed x86 32-bit: Redhat Enterprise V5 and
shooting-Newton method
of pre-layout simulation. An accurate V6, SUSE Linux 9 and 10
parasitic reduction technique enhances Periodic and quasi-periodic noise
the simulation performance of parasitic- x86 64-bit: Redhat Enterprise V4, V5,
analysis
dominant circuits by a significant amount and V6, SUSE Linux 9 and 10
over traditional SPICE-level simulation. Periodic and quasi-periodic small signal
Sun Solaris 10
The technology enables designers to analysis
trade-off accuracy and performance using Periodic stability analysis
a simple user-friendly setup.
Time-domain and frequency-domain
envelope analysis

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Virtuoso Multi-Mode Simulation with Spectre Platform

Spectre Accelerated Parallel Simulator


Spectre APS provides advanced perfor- Features Circuit analysis
mance for the next generation of analog
Supports all analysis capabilities offered DC, AC, and transient analysis
and RF simulation. It delivers significant
in Spectre Circuit Simulator
scalable performance and capacity with Transient noise analysis
accurate results across a broad range of Offers advanced parallel simulation on
Native reliability analysis
complex analog, RF, and mixed-signal a single multi-core compute platform
blocks, and sub-systems with sizes up Monte Carlo and parametric statistical
to millions of transistors and passive and Supports distributed, advanced parallel
support
parasitic elements. Spectre APS provides simulation across a cluster of multi-core
all the transistor-level analysis capabilities compute platforms Full support for sweeping analysis and
available in Spectre Circuit Simulator. circuit parameters
Enables parasitic stitching and
Additionally, its proprietary parallel reduction for post-layout design and Built-in measurement description
simulation technology delivers scalable verification, providing additional language
multi-core processing capability on performance gain for analog and RF
modern multi-core compute platforms. EM and IR drop analysis
designs dominated by parasitics
Built-in advanced parasitic reduction for
Benefits Multi-core harmonic balance, shooting-
faster post layout simulation
Newton, and envelope analysis
Provides significant single-core Static and dynamic circuits checks
performance with an identical use Electromigration and IR drop analysis
model and full Spectre accuracy for RF harmonic balance analysis
Static and dynamic circuit checks
everyday simulation of complex and/ RF shooting-Newton analysis
or large block designs, leading to faster Specifications
convergence RF FAST envelope analysis supporting
Comprehensive device models all modulation schemes
Enables high-precision simulation for
large post-layout analog and RF designs MOSFET models, including latest RF noise and small signal analysis based
and subsystems dominated by parasitic versions of BSIM3, BSIM4, PSP, HISIM, on harmonic balance solution
devices high-voltage MOS (HVMOS), MOS9,
Design inputs/outputs
MOS11, and EKV
Delivers scalable performance
Spectre netlist format
leveraging a single machine or Silicon-on-insulator (SOI), including
cluster of machines with multi-core latest versions of BTASOI, SSIMSOI SPICE netlist format
architectures, allowing higher levels of BSIMSOI, BSIMSOI PD, and BSIM-IMG
Verilog-A
analog design integration and verifi-
Bipolar junction transistor (BJT)
cation and a quick turnaround time S-Parameter data files
models, including latest versions of
onsimulation
VBIC, HICUM, Mextram, HBT, and PSF waveform format
Enables fast and accurate analysis Gummel-Poon models
of complete transceivers and large Platform support
Diode, JFET
post-layout RF IC blocks by signifi- x86 32-bit: Redhat Enterprise V5 and
cantly improving the performance and GaAS MESFET models, includes latest V6, SUSE Linux 9 and 10
capacity of harmonic balance analysis versions of GaAs, TOM2, TOM3, and
using a multi-core compute platform Angelov x86 64-bit: Redhat Enterprise V4, V5,
and V6, SUSE Linux 9 and 10
RPIs Poly and Amorphous Silicon
Thin-Film models Sun Solaris 10

Verilog-A compact device models

Specialized reliability models (AgeMOS)


for HTI and NBTI

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Virtuoso Multi-Mode Simulation with Spectre Platform

Spectre eXtensive Partitioning Simulator


Spectre XPS is the next-generation high- Features
performance transistor-level FastSPICE
EM and IR drop analysis with an
circuit simulator for pre- and post-layout
advanced power network solver
verification of memories, custom digital,
and analog/mixed-signal SoC designs. Built-in advanced parasitic reduction for
It delivers the capacity, accuracy, and faster post layout simulation
speed required for verification of modern
complex and tightly coupled full-chip Static and dynamic circuits checks
designs. It uses advanced proprietary
partitioning techniques to deliver unpar- Specifications
alleled performance compared to tradi- Design inputs/outputs
tional FastSPICE simulators delivering the
needed throughput for design and verifi- Spectre netlist format
cation of the complex full-chip designs.
SPICE netlist format

Benefits Verilog-A 2.0

Provides high performance and capacity DSPF/SPEF parasitic formats


pre-and post-layout simulation for
SST2 waveform format
design and IP characterization at the
block and chip level PSF and PSF XL waveform format

Provides a comprehensive set of FSDB format


transistor-level electrical rule checks
Platform support
Delivers advanced EM and IR drop
x86 32-bit: Redhat Enterprise V5 and
analysis for optimal throughput
V6, SUSE Linux 9 and 10
Supports large and complex post-layout
x86 64-bit: Redhat Enterprise V4, V5,
designs delivering a significant
and V6, SUSE Linux 9 and 10
reduction in simulation run time
compared to traditional FastSPICE Sun Solaris 10
simulator

Proven Spectre use model for easy


setup and post processing of results

Tightly integrated into the Analog


Design Environment

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Virtuoso Multi-Mode Simulation with Spectre Platform

UltraSim Full-Chip Simulator


The UltraSim Full-Chip Simulator is a high-
Digital
performance transistor-level FastSPICE
Testbench
circuit simulator for pre- and post-layout
verification of memories, custom digital,
and analog/mixed-signal SoC designs. It
delivers the capacity, accuracy, and speed
Functional
required for verification using abstraction Verification
a Hierarchical
where appropriate while preserving the d Mem Netlist AMS

Stitching
D Timing
design intent. It uses true hierarchical PM
Designer
a
simulation and a patented isomorphic and and
D Power
adaptive partitioning algorithms. Parasitics UltraSim
Analog
DSPF, SPEF
Reliability
Benefits
Accelerates pre-and post-layout
simulation for a wide range of Electromigration/
applications from blocks to full-chip IR Drop Analysis
SoCs (see Figure 5)
Figure 5: Virtuoso UltraSim post-layout verification and analysis for silicon realization
Provides a comprehensive set of
transistor-level analysis covering
Features Specifications
electrical rule check (ERC), power,
timing, and nodal activity Compatible with SPICE, Spectre, Design inputs/outputs
Handles large post-layout designs using
Verilog-A, and SPEF
Spectre netlist
a combination of unique hierarchical The UltraSim Full-Chip Simulator is
parasitic stitching techniques and an SPICE netlist format
compatible with most types of SPICE
accurate frequency-based parasitic input decks for both pre- and post-layout. DSPF/SPEF parasitic formats
reduction algorithm Natively reads Spectre format netlists and
Verilog-A
models, and uses the same views within
Supports multiple simulation
Virtuoso Analog Design Environment, SST2 waveform format
abstraction modes (SPICE, analog,
making it easy to adopt in Spectre-based
mixed-signal, and digital), enabling the PSF and PSF XL waveform format
design flows.
user to locally tune performance and
accuracy settings for different blocks in FSDB format
Post-layout simulation
the design Veritools waveform format
When used in conjunction with Cadence
Includes flexible, easy-to-use controls post-layout products, the UltraSim UltraSim/Verilog
for providing adequate tradeoff Full-Chip Simulator provides a means Verilog-HDL IEEE 1364
between accuracy and simulation speed for exploration and validation of such PLI 1.0, VPI (PLI 2.0)
Plugs smoothly into design and verifi- effects as electromigration, IR drop, signal SDF
cation flows through integration integrity, and substrate degradation.
AMS-UltraSim
with the Virtuoso Analog Design It also has built-in, state-of-the-art,
Verilog-AMS 2.0
Environment and command-line S-Parameter-based parasitic reduction
VHDL-AMS 1076.1
environments for faster simulation with minimal loss in
Verilog (IEEE 1364-1995, IEEE
accuracy.
1364-2001 extensions)
Design reliability simulation VHDL (IEEE 1076-1987, IEEE
1076-1993, IEEE 1076.4-2000 [VITAL
The UltraSim Full-Chip Simulator provides
2000])
a robust set of analyses capable of
PLI 1.0, VPI (PLI 2.0)
predicting and validating timing, power,
SDF
and reliability. It is the only FastSPICE
SystemC, SystemVerilog
simulator capable of simulating HCI and
NBTIkey stress effects that must be
taken into account for high-performance
advanced node designs.

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Virtuoso Multi-Mode Simulation with Spectre Platform

AMS Designer Simulator


The AMS Designer provides an advanced AMS Block and Top-Down Verification
mixed-signal simulation solution for
Virtuoso AMS Designer
the design and verification of analog,
RF, memory, and mixed-signal silicon
Virtuoso Incisive Design
realization. It is integrated with the Spectre L/LX Team Simulator
Virtuoso full-custom environment as
well as the Incisive functional verification
platform. AMS Designer provides a
single simulation executable with flexible
abstraction support through the standard
mixed-signal languages (Verilog-AMS and
VHDL-AMS) and/or SPICE-level models.
As the bridge between analog and digital
domain, it enables users to choose the
right analog solver for the right design or Multi-Language Debugging
verification task. Designers can choose Unified Waveform
Spectre technologies for SPICE-accurate
block-level analog and RF designs: Spectre Virtuoso AMS Designer
APS, Spectre RF and Spectre XPS.
Virtuoso Incisive Design
AMS Designer is fully configurable across
UltraSim X/XL Team Simulator
the design and verification domains,
offering the right simulation technology AMS Full-Chip Verification
and environment for every stage in the
Figure 6: Virtuoso AMS Designer verification flow addresses silicon-realization
design and verification cycle.
requirements throughout the design cycle

Benefits
Features is configured using the hierarchy editor,
Ensures design quality with proven which facilitates the viewing and design
Spectre and Incisive digital simulation Methodology-independent design preparation of a complex mixed-signal
technologies convergence design. Automatically inserted interface
The AMS Designer provides the flexibility elements are used to translate signals
Supports both analog design flow use
to combine IP from different sources from one domain to the next, leaving
models in Virtuoso Analog Design
and in different formats for todays the user free to simulate with different
Environment as well as digital-verifi-
SoC designs. It does more than just design configurations to easily tradeoff
cation use models in the Incisive
co-simulate analog and digital blocks. simulation speed for simulation accuracy.
environment
By treating Virtuoso Schematic Editor The AMS Designer also supports IP
Supports both top-down and blocks and textual descriptions equally, encryption using RSA technology, which
bottom-up methodologies to quickly the AMS Designer allows different allows the user to establish both IP reuse
detect and fix design failures early points of data entry. It accepts descrip- and virtual-prototyping methodologies.
in the design cycle, helping to meet tions in the standard language formats
tapeout schedules of Verilog-AMS, VHDL-AMS, Verilog-A, Integrated with proven Spectre and
Extensive language support allows Verilog, VHDL, and SystemC, as well as Incisive simulation technologies
a higher level of abstraction and SPICE, and performs simulation on any
The AMS Designer is a single executable
accelerates simulation to achieve faster combination of these languages. This
mixed-signal simulator based on the
turnaround time allows bottom-up and top-down design
proven technology of Spectre, Specre
methodologies to converge into a fully
Supports simulation of RF circuits at full APS, and UltraSim Full-Chip Simulator,
functional design.
SPICE accuracy by combining envelope and the Incisive digital simulation capabil-
analysis of RF transceivers with Different levels of abstraction, such as ities.
digital baseband simulation for faster Verilog-AMS or VHDL-AMS behavioral
Analog-centric flow with Virtuoso
convergence of results models and schematic representation, are
easily interchangeable to allow the design The AMS Designer is tightly integrated
to change over time from full behav- with the Virtuoso Analog Design
ioral to full transistor. The entire design Environment for mixed-signal block

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Virtuoso Multi-Mode Simulation with Spectre Platform

design. It uses native Analog Design The SimVision multi-language Common mixed-signal waveform
Environment netlisting technologies to debugging environment allows users database
combine schematics and behavioral views, to view analog and digital signals in a
Incisive environment
enabling users to independently manage single waveform environment
the level of abstraction of each block. Mixed-signal debugger
AMS Designer Verification Option
The entire design is configured using
the hierarchy editor, which facilitates Breakpoints on time, position, and
The AMS Designer Verification Option
the viewing and design preparation of a condition
provides a complete solution for advanced
complex mixed-signal design. mixed-signal silicon realization. Debug stepping through behavioral
Using AMS Designer with Spectre code, analog, and digital
Enables cross-domain connectivity
ensures that the user gets golden between testbenches and design Schematic tracer
simulation results for performance IP blocks from multiple vendors by
measurements Signal flow and error browser
providing native connectivity between
VHDL or SystemVerilog and SPICE Digital transaction support
Advanced circuit analysis such as
Monte Carlo can be performed with Supports assertion-based verifi- AMS Designer Verification Option
the AMS/Spectre interface, leveraging cation for analog and digital designs
the performance benefits of behavioral by extending the syntax of PSL and Native VHDL-SPICE connectivity
models and using the same setup as SVA languages, providing an efficient Native SystemVerilog to SPICE and AMS
the Spectre tool and effective methodology for connectivity
capturing design intent and verification
Advanced-model validation capabilities
automation PowerSmart connect modules for
allow users to verify their circuit
low-power support
design against a behavioral model Extends mature digital verification
automatically by comparing simulation methodologies, such as low-power Design inputs
waveforms verification, to the analog domain.
Cadence CDBA database or
Supports capturing power intent
Digital-centric flow with Incisive OpenAccess database
with CPF and automatically inserting
The AMS Designer works natively in the PowerSmart connect modules on key Verilog-AMS 2.0
Incisive environment for digital-centric interfaces
VHDL-AMS 1076.1
verification. A single control file is used to
define how analog blocks are integrated Specifications Verilog (IEEE 1364-1995, IEEE
into the digital SoC. Analog and RTL 1364-2001 extensions)
blocks can be easily interchanged to trade Virtuoso environment
VHDL (IEEE 1076-1987, IEEE 1076-1993,
off accuracy and performance. It supports Direct Verilog-AMS netlisting IEEE 1076.4-2000 [VITAL 2000])
all features in the Incisive environment like
testbench analysis, Specman technology, Hierarchy editor AMS plug-in Spectre and SPICE netlist formats
and verification planning. Hierarchy editor configuration SystemVerilog (IEEE 1800)
Automatically inserted interface Support for global design variables and Common Power Format (CPF)
elements are used to translate signals global signals
from one domain to the next, leaving Within Incisive platform: SystemC (OSCI
the user free to simulate with different Inherited connections SystemC v2.01), SystemC Verification
design configurations to easily trade
AMS Simulator Library (OSCI SCV 1.0), and Specman e
off simulation speed for simulation
accuracy Single executable mixed-signal/mixed- Design outputs
language simulator SST2 waveform format analog and
In the verification flow, the UltraSim
Full-Chip Simulator is used as the Built-in Spectre APS and Spectre RF and digital data
built-in analog simulation engine. This Incisive digital engines PSF waveform format for analog data
enables final verification of the largest
Digital and real number-modeling Verilog-AMS netlist format
mixed-signal SoCs. The Incisive digital
capabilities
simulation engine inside AMS Designer
delivers high-performance native System-level simulations with links to
Verilog, SystemVerilog, VHDL, SystemC, Simulink from MathWorks
and e simulation
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2013 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Incisive, Specman, Spectre, and Virtuoso are registered
trademarks of Cadence Design Systems, Inc. SystemC is a trademark of the Open SystemC Initiative, Inc. in the US and other countries and are used
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