DOC/LP/01/28.02.

02

LAB PLAN
EC 2207-DIGITAL ELECTRONICS LAB

LP- EC2207 Revision No:00 Date: 26/06/09 Page 1 of 4

EC2207 DIGITAL ELECTRONICS LAB 1. 2. Design and implementation of Adder and Subtractor using logic gates. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa 3. 4.

0

0

3

100

Design and implementation of 4 bit binary Adder/ subtractor and BCD adder using IC 7483 Design and implementation of 2 bit Magnitude Comparator using logic gates 8 Bit Magnitude Comparator using IC 7485

5. 6.

Design and implementation of 16 bit odd/even parity checker generator using IC74180. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154

7.

Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147

8. 9.

Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters Design and implementation of 3-bit synchronous up/down counter

10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops 11. Design of experiments 1, 6, 8 and 10 using Verilog Hardware Description Language

02.EC2207 Revision No:00 Date: 26/06/09 Page 2 of 4 LIST OF EQUIPMENTS AND COMPONENTS FOR A BATCH OF 30 STUDENTS (2 per Batch) S. each) 1 IC7400 25 2 IC7404 25 3 IC74682 25 4 IC7402 25 5 IC7408 25 6 IC7411 25 7 IC7432 25 8 IC7483 25 9 IC7485 25 10 IC7486 25 11 IC74150 25 12 IC74151 25 13 IC74147 25 14 IC7445 25 15 IC7474 25 16 IC7476 25 17 IC7491 25 18 IC7494 25 19 IC7447 25 20 IC74180 25 21 IC555 25 22 Seven Segment Display 25 23 LEDs 25 24 Bread Board 25 25 Wires .02 LAB PLAN EC 2207-DIGITAL ELECTRONICS LAB LP.DOC/LP/01/28.No Name of the equipments / Components Quzntity Required Remarks 1 Digital IC Tester 2 Nos 2 Power Supply 10 5V DC 3 Multimeter 10 Digital 4 Computer with HDL software Installed 2 Consumables (Minimum of 25 Nos.

DOC/LP/01/28. make a study of various IC’s and study using Verilog Hardware Description Language 1Batch 2Batch 3Batch 4Batch 5Batch 7Batch 8Batch 9Batch 10Batch 12Batch 14Batch 16Batch 6Batch 11Batch 13Batch 15Batch 17Batch Ses.02 18Batch .02 LAB PLAN EC 2207-DIGITAL ELECTRONICS LAB LP.EC2207 Revision No:00 Date: 26/06/09 Page 3 of 4 Digital Electronics Lab Objective: To Design Combinational and Sequential logic Circuits using logic gates. No 1 2 3 4 5 6 7 8 Introduction 1 2 3 4 5 6 2 3 4 5 6 1 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 1 2 3 4 5 6 2 3 4 5 6 1 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 1 2 3 4 5 6 2 3 4 5 6 1 3 4 5 6 1 2 4 5 6 1 2 3 5 6 1 2 3 4 6 1 2 3 4 5 Mid-Sem Model Exam 7 8 9 10 11 12 13 14 8 9 10 11 12 13 14 7 9 10 11 12 13 14 7 8 10 11 12 13 14 7 8 9 11 12 13 14 7 8 9 10 12 13 14 7 8 9 10 11 13 14 7 8 9 10 11 12 14 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 8 9 10 11 12 13 14 7 9 10 11 12 13 14 7 8 10 11 12 13 14 7 8 9 11 12 13 14 7 8 9 10 12 13 14 7 8 9 10 11 13 14 7 8 9 10 11 12 14 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 8 9 10 11 12 13 14 7 9 10 11 12 13 14 15 16 DOC/LP/01/28.02.02.

12. PISO and PIPO shift registers using Flip-flops Design of adder . 6. 14. M. 8. 4. IC 74154 Encoder and decoder using logic gates and study of IC7445.Amutha HOD/EC 29. No 1. 5.Sivagnana Subramanian.2009 . demultiplexer using Verilog Hardware Description Language Design of counters and shift registers using Verilog Hardware Description Language 11 11 Cross reference as per syllabus 1 2 (i) 2 (ii) 3 4 5 6 7 8 9 10 11 Prepared by Signature Name S. 10. 9. 11. 3. L.06. IC74147 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 3-bit synchronous up/down counter SISO.Anju.R. P. 13.LAB PLAN EC 2207-DIGITAL ELECTRONICS LAB LP.06.EC2207 Revision No:00 Date: 26/06/09 Page 4 of 4 List of Experiments: S. 7. Title Adders and Subtractors using logic gates BCD to excess-3 code converter and vice versa using logic gates Binary to gray code converter and vice-versa using logic gates 4 bit binary Adder/ Subtractor and BCD adder using IC 7483 2-Bit Magnitude Comparator using IC 7485 16-bit odd/even parity checker/ generator using IC74180 Mux and De-mux using logic gates and study of IC74150.2009 Approved by Prof. L. SIPO. subtractor using Verilog Hardware Description Language Design of multiplexer. Dr.P.Muthukumaran Designation SL. L.Athappan. L Date 29. 2.

Sign up to vote on this title
UsefulNot useful