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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2737534, IEEE

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Voltage-Doubler SEPIC PFC Rectifiers

Paulo J. S. Costa, Carlos H. Illa Font, Member, IEEE, Telles B. Lazzarin, Member, IEEE

Abstract In this paper, the switched-capacitor concept is voltage-doubler rectifiers and provide, when compared to the

extended to the voltage-doubler DCM SEPIC rectifier. As a conventional Boost rectifier, gains in relation to cost and

result, a set of single-phase hybrid SEPIC PFC rectifiers able to efficiency and supply twice the output voltage (hence the term

provide lower voltage stress on the semiconductors and/or higher

voltage-doubler) or a lower voltage stress on the

static gain, which can be easily increased with additional

switched-capacitor cells, is proposed. Hence, these rectifiers could semiconductors.

be employed in applications that require higher output voltage. Other examples of PFC rectifiers available for application

In addition, the converters provide a high power factor and a with higher output voltage are the voltage-doubler SEPIC

reduced total harmonic distortion in the input current. The converters addressed in [6], [9] and [10]. These converters

topology employs a three-state switch, and three different operate in discontinuous conduction mode (DCM), because in

implementations are described, two being bridgeless versions,

this operation mode the input current naturally has the same

which can provide gains in relation to efficiency. The structures

and the topological states, a theoretical analysis in steady state, a shape (if the high-frequency ripple of this current is neglected)

dynamic model for control and a design example are reported and phase of the input voltage [9], [11], [14]. Hence, the

herein. Furthermore, a prototype with specifications of 1000 W rectifier does not require a current control loop, which

output power, 220 V input voltage, 800 V output voltage and simplifies its control system. Furthermore, in the case of these

50 kHz switching frequency was designed in order to verify the rectifiers, the input current does not have the third harmonic,

theoretical analysis.

do not need additional bulk filters [10], [13], [14], and impose

Index Terms Voltage-doubler DCM SEPIC, Single-phase

reduced voltage stress on the semiconductors.

rectifier, Switched capacitor, Bridgeless, High power factor. On the other hand, recent publications describe a new class

of PFC rectifiers, referred to as hybrid (pulse-width-modulated

+ switched capacitor) rectifiers [3]. This class integrates

I. INTRODUCTION conventional rectifiers with the switched-capacitor converters

n recent years, the market demand for power supplies with (SCC), which are able to divide or multiply a voltage without

Ihigh dc output voltage for use in distributed generation, increasing the voltage stress across the semiconductors [3],

[15]-[18]. Hence, this new class of PFC rectifiers can be

renewable energy, energy storage, dc-dc smart grids, electrical

vehicles, UPS, X-ray systems, and motor drivers has increased employed in applications that require higher dc output voltage

[1]-[3]. In these applications the power supply can be used to (above 400 V).

directly feed a load or as an input stage of another power Although the concept of hybrid rectifiers is recent, it has

converter [3]. In both cases, the system is commonly fed by an already provided opportunities for new lines of research [3],

ac grid. Hence, a converter with power factor correction (PFC) [16], [19], [20]. In this context, based on the voltage-doubler

is required to provide a high power factor and reduce the total SEPIC rectifier in [10], multiplier SEPIC dc-dc converter in

harmonic distortion in accordance with the regulations and [15], switched capacitor (SC) cell in [17], hybrid rectifiers in

standards, such as IEC 6100-3-2 [4]. [3], [16], [19], [20] and studies described in [9], [11], [12] and

Due to the current source characteristic at the input, [21]-[27], this paper proposes a set of single-phase hybrid

structures derived from Boost converters are normally voltage-doubler SEPIC rectifiers. These rectifiers provide a

employed in stages with power factor correction. Some Boost high power factor, reduced total harmonic distortion (THD),

rectifiers suitable for applications with high output voltage are reduced voltage stress on the semiconductors and higher dc

output voltage values (above 800 V).

The Boost converters integrated to SC cells approached in

This work was supported by CAPES Brazilian Federal Agency for Sup- [3] and [16], in contrast to the proposed rectifiers in this paper,

port and Evaluation of Graduate Education within the Ministry of Education operate in continuous conduction mode (CCM). Therefore,

of Brazil, Federal University of Santa Catarina and Power Electronics Institute

(INEP).

these structures require a control loop to regulate the input

P. J. S. Costa and T. B. Lazzarin are with the Department of Electrical current, which makes the control system of the converter more

Engineering, Federal University of Santa Catarina, Florianopolis, Brazil (e- complex. Furthermore, the Boost rectifiers operate with

mail: paulojunior@inep.ufsc.br; telles@inep.ufsc.br).

C. H. Illa Font is with the Department of Electronics Engineering, Federal

variable duty cycle, which increases the losses in the SC. The

University of Technology Paran, Ponta Grossa, Brazil (e-mail: converters addressed in [15] and [17]-[18] use the

illafont@utfpr.edu.br).

0885-8993 (c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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conventional ladder SC cell in dc-dc and ac-ac conversion and operation of the conventional SEPIC is maintained.

the same cells are applied in [3] and [16]. The conventional

De _ n +1

ladder SC cell does not work in the SEPIC rectifier. Hence, in Co _ n

[19-20] was proposed a modified ladder SC cell that allows De _ n

CS _ n

the integration between SCC and classical SEPIC rectifier.

Despite employing an additional semiconductor, this modified

cell allows the rectifier to work properly and it preserves the

De3

high quality of the input current, which is an important Co 4

characteristic of the SEPIC rectifiers that operate in DCM. De 2

CS 1

However, only a partial analysis of the switched-capacitor

Do 2 Do1

integrated to the classical SEPIC rectifier is approached in

[19] and [20].

De1 Ci1 Co1

The proposed converters provide an increase of the static

Lo1

gain and a reduction in the voltage stress on the PB

semiconductors in relation to the rectifier addressed in [10], PA PC

Ro

but the structures use more elements. With regard to the Li

converters described in [19] and [20], the proposed rectifiers PD

vg Lo 2

also employed a greater number of components. Nevertheless,

De 4 Ci 2 Co 2

these rectifiers provide, for a same number of switched

capacitor cells, a reduction in the voltage stress on the

Do 4

semiconductors and are able to process twice more power, CS 2 Do3

because these converters work as two half-wave rectifiers, one

De5

for each half-line cycle. Due to the characteristic of operation Co3

in half-line cycle, the current and voltage stress are divided De6

among the elements of the circuit and, consequently, the

proposed rectifiers can process higher power levels.

CS _ n +1

De _ n + 2 Co _ n +1

II. THE PROPOSED SINGLE-PHASE HYBRID VOLTAGE-

DOUBLER SEPIC RECTIFIERS De _ n +3

The structure of the hybrid voltage-doubler SEPIC rectifier (a)

(seen in Fig. 1) requires a three-state switching cell, which can PB PB PB

be implemented in three modes: the first (1S) employs one

D1 D2 D1 S1 S1 S2

active switch, as seen in Fig.1 (b); the second (2S) is shown in PA S PC PA PC PA PC

Fig. 1 (c) and uses two active switches; and the third (4S) is D3 D4 D2 S2 S3 S4

shown in Fig. 1 (d) and employs four active switches. These

cells can be used in applications that require a static gain (M) PD PD PD

less than, equal to or greater than one (M 1, M 1). It is (b ) (c ) (d )

important to highlight that regardless of the cell employed the Fig. 1. (a) The proposed single-phase hybrid voltage-doubler SEPIC rectifier

with three-state generic active switching cell and generic switched-capacitor

main topological states of the circuit are not changed. cell, (b) three-state switch with one active switch (1S), (c) three-state switch

The proposed structure increases the static gain of the with two active switches (2S - bridgeless version), and (d) three-state switch

voltage-doubler SEPIC rectifier by adding of ladder-type with four active switches (4S - bridgeless version).

switched-capacitor cells. The elements CS1, CS2, Co3, Co4, De1,

De2, De3, De4, De5, De6, Do2 and Do4 integrate the first and A. Operation Stages of the Proposed Rectifier

second modified switched-capacitor cells. These two cells The bridgeless version with two active switches (Fig. 1 (a)

have two extra diodes (De1-Do2 and De4-Do4) (when compared and (c)) and two ladder-type switched-capacitor cells (n = 2)

to the conventional switched-capacitor cell [3], [15]-[18]) were chosen to analyze the proposed converter. The structure

which allow the charge and discharge of the switched 2S presents a lower number of components and thus the

capacitors CS1 and CS2, without changing the voltage in Ci1 and conduction losses can be reduced. It employs two switches,

Ci2 (this modified cell was proposed for the conventional but these use the same gate drive signal. The structure

SEPIC rectifier in [19] and [20]). The resulting structure is analyzed is shown in Fig. 2.

able to provide a high quality input current [20] and thus the The rectifier presents eight topological states in DCM, four

switched-capacitor can be applied in the SEPIC rectifier. The of them for the positive cycle of the grid. In these states, the

other cells, seen in Fig 1 (a) (CS_n-De_n-De_n+1-Co_n, and CS_n+1- current flows through the green and black connections (as

De_n+2-De_n+3-Co_n+1), are conventional ladder switched- illustrated in Fig. 3). The other four topological states are for

capacitor cells and are added to increase the static gain of the the negative cycle, when the current flows through the blue

rectifier. It is important to highlight that in the case of the and black connections. In steady-state operation, the voltage

proposed rectifier in Fig. 1 the step-down and step-up

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respectively, vg and Vo/(2 + n), where vg is the input voltage

and Vo is the average value of the output voltage. The first four De3

Co 4

states are described below in detail.

De 2

Stage 1 (Fig. 3 (a)): This stage starts when the switch S1 is CS 1

turned on. The diodes D1, De1 and De2 are forward-biased vg Do 2 Do1

while all other diodes are reversed-biased. The elements S1,

De1 and De2 connect the capacitors Co1 and CS1 in parallel. De1 Ci1 Co1

However, the charge current of CS1 does not flow through Ci1 Lo1

due to the modified switched-capacitor cell. The switched D1 S1

capacitor CS1 is charged by Co1 from S1, De1 and De2 and it Ro

Li

presents voltage equal to vCo1 which, in turn, is equivalent to D2 S2

vo/(2 + n). The current in the inductors Li and Lo1 increases vg Lo 2

linearly in agreement with the vg/Li and vg/Lo1 ratios, De 4 Ci 2 Co 2

respectively. The load Ro is fed by the capacitors Co1, Co2, Co3

and Co4. Do 4

CS 2 Do3

Stage 2 (Fig. 3 (a)): This state is initiated when the switch

S1 is turned off. Diodes D1, Do1, Do2 and De3 are forward- De5

biased and all other diodes are blocked. The elements Do2, Do1 Co3

De 6

and De3 connect CS1 and Co4 in parallel. Hence, the voltages on

theses capacitors are equal to Vo/(2 + n). The current that Fig. 2. The proposed single-phase hybrid voltage-doubler SEPIC rectifier with

flows through these elements is provided by inductors Li and two active switches (2S-bridgeless version) and with n = 2.

Lo1. The current in the inductors Li and Lo1 decreases

accordingly with relations [Vo/(2 + n)]/Li and [ III. DESIGN EQUATIONS

Vo/(2 + n)]/Lo1, respectively. The load Ro and output capacitors A. Voltage-Doubler SEPIC Converter Cell Design

are supplied by energy previously stored in Li and Lo1 in the

The main design equations for the voltage-doubler SEPIC

first stage.

converter cell are reported in Table I. Details of the

Stage 3 (Fig. 3 (c)): During this stage the switch S1 remains

determination of these numerical expressions can be found in

turned off and the diodes D1, Do2 and De3 are forward-biased.

[10].

Diode Do1 and all other semiconductors are blocked. The

capacitors CS1 and Co4 remain connected in parallel through B. Switched-Capacitor Cell Design

the diodes Do2, Do1 and De3. The energy stored in the inductors Fig. 7 (a) highlights the ladder-type switched-capacitor cells

Li and Lo1 flows through Do2, CS1 and De3 to the load Ro and integrated with the voltage-doubler SEPIC rectifier. These

the output capacitors. cells can be represented by an equivalent circuit, such as that

Stage 4 (Fig. 3 (d)): This subinterval is the traditional shown in Fig. 7 (b), where Ron-c is the total conduction

discontinuous stage of the SEPIC converter. During this stage resistance of the switched capacitor (semiconductors

all of the semiconductors are turned off and the current in the resistances (Ron) plus the capacitor resistances (Rce)).

inductors Li and Lo1 is constant. Hence, the voltage across The switched-capacitor cell shown in Fig. 7 (b) can be

these inductors is zero. The voltage on the capacitors CS1, CS2 represented by an equivalent resistance (Req) as shown in Fig.

Co1, Co2, Co3 and Co4 is equal to Vo/(2 + n). The load Ro is fed 7 (c). The value of Req is defined by the expression (1) [23]

by the output capacitors. and it is a function of the system switching frequency (fs), duty

B. Main Ideal Waveforms cycle (D) and time constant defined in (2).

The main theoretical waveforms of the proposed converter, 1

for the case where the input voltage achieves the highest level, 1 e f s

Req =

1 (1)

which is denominated as (Vp), are shown in Fig. 4, Fig. 5 and fsCS D (1 D ) 1

Fig. 6. The waveforms for one switching period are shown in 1 e f s

e f s

+e f s

Fig. 4 and Fig. 5. These figures show the current and voltage = C S ( Ron + Rce ) (2)

in the inductors Li, Lo1 and Lo2, the current in the capacitors

Ci1, Ci2, CS1 and CS2, and the current and voltage on the

where Ron is the conduction resistance of the semiconductors

semiconductors S1, S2 and Do1, Do2, Do3 and Do4. Fig. 6

and Rce is the equivalent series resistance of the capacitors.

shows, for one grid period, the input voltage (vg), input

Based on (1), the behavior of the equivalent resistance in

current (iLi), current in the output inductors (iLo1 and iLo2),

relation to fs to one fixed duty cycle was traced, as shown in

output voltage (vo) and voltage on capacitors Ci1, Ci2, Co1, Co2,

Fig. 8 (a). The value of D = 0.35 was chosen because this

Co3, Co4, CS1 and CS2 (vCi1, vCi2, vCo1, vCo2, vCo3, vCo4, vCS1,

ensures the MCD of the voltage-doubler SEPIC converter.

vCS2). It can be verified that the proposed rectifier has a high

From this curve one can define three different operating

power factor and ensures the multiplication of the output

modes of the switched capacitor: Total charge (Tc), Partial

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De3 De3

Co 4 vCo 4 Co 4 vC o 4

De 2 De 2

C S1 C S1

vg Do 2 Do1 vg Do 2 Do1

Lo1 vLo1 Lo1 vLo1

vLi D1 S1 vS 1

iLo1 vLi D1 S1 vS 1

iLo1

Ro vo Ro vo

iLi Li iLi Li

D2 S2 vS 2 D2 S2 vS 2

vg Lo 2 vLo 2 vg Lo 2 vLo 2

De 4 Ci 2 Co 2 vCo 2 De 4 Ci 2 Co 2 vC o 2

iLo2 iLo2

Do 4 Do 4

CS 2 Do3 CS 2 Do3

De5 De5

Co3 vCo 3 Co3 vC o 3

De6 De6

(a ) (b)

iCo4 iRo iCo4 iRo

De3 De3

Co 4 vC o 4 Co 4 vCo 4

De 2 De 2

C S1 C S1

vg Do 2 Do1 vg Do 2 Do1

Lo1 vLo1 Lo1 vLo1

vLi D1 S1 vS 1

iLo1 vLi D1 S1 vS 1

iLo1

Ro vo Ro vo

iLi Li iLi Li

D2 S2 vS 2 D2 S2 vS 2

vg Lo 2 vLo 2 vg Lo 2 vLo 2

De 4 Ci 2 Co 2 vC o 2 De 4 Ci 2 Co 2 vCo 2

iLo2 iLo2

Do 4 Do 4

CS 2 Do3 CS 2 Do3

De5 De5

Co3 vC o 3 Co3 vCo 3

De6 De6

(c ) (d )

Fig. 3. Operation stages of the rectifier 2S with n = 2 for positive cycle of voltage grid: (a) first stage, (b) second stage and (c) third stage, and (d) fourth stage.

charge (Pc) and No charge (Nc) [22]. For each mode the The Pc boundaries are shown in Fig. 8 (a). The border with

behavior of the current in the capacitor differs, as is Tc presents Req = 14.4 Ron-c and fs = 0.07. On the other hand,

demonstrated in Fig. 8 (b), (c) and (d). the border with Nc occurs at Req = 4.44 Ron-c and fs = 1.306.

Based on the curve of Req (Fig. 8 (a)) and the current Thus, there is a considerable difference between these limits.

behavior in each operating mode (Fig. 8 (b), (c) and (d)) it can Fig. 8 (a) also defines an internal operation point, where fs is

be concluded that the Tc mode presents greater loss due to the equal to 0.5. This point has an equivalent resistance of 1.08 pu

higher peak current; however, it requires a lower capacitance regarding the minimal resistance (when fs tends to infinity Req

value (considering constant switching frequency). The Nc reaches its lowest value of 4.4, considering D = 0.35). After

mode presents less loss; however, it requires higher fs = 0.5, if the fs value is increased by a factor of two, the Req

capacitance values. Therefore, in relation to losses and value reduces by only 6%. This analysis suggests the use of an

volume, Pc is the best operating mode. fs value equal to or close to 0.5, because fs > 0.5 increases

the volume of the CS or the switching frequency; however, it

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Stages Stages

iLi 1 2 3 4 1 2 3 4

ILi max vLi = vLo1

Vp

ILi min

0

t 0

t

iLo1

ILo1max VCo1

vLo 2

0

t

ILo1min = ILi min

iLo 2 0

t

vS1

0 V p + VCo1

t

Vp

ILi max iCi1 0

t

ILi min vS 2

0

t

ILo1max 0

t

iCi 2 vDo1

0

t

VCo1

0

t (

V p + VCo1 )

ILi max + ILo1max iS1

vDo 2

0

+ ICS1min t

ICS1min 0.5VCo 2

0 V p

t

iS 2

vDo3

0

t

0

t VCo 2

ILi max + ILo1max iDo1

vDo 4

ICS1max 0

t

0

t 0.5VCo3

iDo 2

ICS1max DTS = t1 t2 t3 t4

0

t (1 D ) TS

iDo3 ; iDo 4 TS

Fig. 5. Ideal waveforms (voltages) for a switching period of the rectifier 2S

with n = 2.

0

t

iCS1 does not reduce significantly the Req value. Table II shows fs

ICS1max

0

t

and Req (in pu) for some operation points and for the suggested

ICS1min design point.

iCS 2 The switched capacitors CS1 and CS2 can be defined from (1)

as

0

t 1

iCo1

ILi max + ILo1max 1 1 e f s . (3)

C S1 = C S 2 =

IRo f s R eq D (1 D ) 1

IRo0 t

1 e f s

e f s

+e f s

( ICS1min + IRo )

iCo 4 Applying the suggested design point of fs = 0.5 and D = 0.35

( ICS1max IRo ) 0 in (3), one obtains the appropriate value for the switched

IRo t capacitors, which is given by

iCo 2 ; iCo3

2.36 . (4)

C S1 = CS 2 =

0 f s Req

IRo t

DTs = t1 t2 t3 t4 The rms current value for capacitors CS1-CS2, Co3-Co4 and

(1 D ) TS the average current value for diodes De1, De2, De3, De4, De5 and

TS De6 are described, respectively, in

Fig. 4. Ideal waveforms (currents) for a switching period of the rectifier 2S

with n = 2.

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TABLE I

Vp vg iLi THE MAIN DESIGN EQUATIONS

vg

ILi max Parameter Design Equation

iLi w Ro

0 Static Gain (M) D

0.5 1.5 2 4 Leq f s

Critical 4 f s Leq

Resistance

(Romin) (1 D )2

vo vCo1 vCo 2 vCo3 vCo 4 vCS1 vCS 2

Vo Maximal Duty f s Leq

vo 1 2

Cycle (Dmax) Ro

0.25Vo Equivalent

vCo1 = vCo 2 = vCo3 = vCo 4 = vCS1 = vCS 2 Li Lo1

w Inductance Li + Lo1

0 (Leq)

V p + 0.5VCi1 vCi1 Auxiliary Vp

Variable (Ieq) Leq f s

Inductance of VpD

0

w Li i Li f s

0.5 1.5 2

vCi 2 3 D V o 2 Li ( L i + 2 L o 1 )

V p + 0.5VCi1

Current in Li D 3V p 2

+4 L 2 V 2 9 D V 2

(rms) o1 o ( p )

w 24V o 2 Li 2 L o12 f s 2

0

0.5 1.5 2 Inductance of Li RoV p 2 D 2

iLo1

ILo1max Lo1 and Lo2 4 LiVo 2 f s RoV p 2 D 2

32 4V p 6 DV p

( )

w Vo Li 2

0 3 2 + 3 Vo ( 4 3 D )

1.5 2 Current in Lo1 D Vp

iLo 2 and Lo2 (rms)

ILo 2 max + 108 D V p 2 Lo1 ( Lo1 + 2 Li )

144 Vo 2 Li 2 Lo12 f s 2

2

0

w Capacitance of {

D 2V p D ( 2 + n ) V p Lo1 V o Li + 2V o Li }

0.5 2 Ci1 and Ci2 8V o 2 Li 2 L o1 VC i1 f s 2

Fig. 6. Ideal waveforms in one grid period of the rectifier 2S with n = 2.

V p Lo12 108 D V p + 128Vo + 12 Li 2Vo 2

( )

Current in Ci1 D 3V p 2

9 D L 2V 2 + 192 DL L V V

and Ci2 (rms) i o i o1 p o

De3 144Vo 2 Li 2 Lo12 f s 2

Co 4

De 2 Capacitance of ( 4 + 2 n ) Po thut

CS 1 2

Ron c Co1 Co4 Vo 2 ( 0, 9Vo )

Do1 Sa

Do 2 Co1

Cs

Sb (

2V p 2 D 2 Ro 3Vo Leq f s + 4 DV p Ro ) 2 D ( IC S 1min )

Co1 Sc

De1 Ci1

Co 2

Current in Co1 (

+ 3Vo 2 Leq 2 f s 2 3Vo 8 DV p ) +

3

Lo1 Sd and Co2 (rms) 18 Leq 2 f s 2 RoVo V 2

+ o 2

D1 S1 2R

(b) o

Ro

Li Maximum vol-

D2 S2 V p ( 2 + n ) + Vo

tage stress on

vg Lo 2 Req S1, S2, Do1 and 2+n

De 4 Ci 2 Co 2 Do2

Co1 Co 4

D 2 V p 2 + 2f s 2 Leq 2 ICS 1min 2

Do 4

Current in S1 D

CS 2 Do3 (c ) +4 DV p f s Leq ICS1min

and S2 (rms)

De5 2 2

12f s Leq

Co3

De6 Current in Do1 D 2 I eq

and Do3 (avg) 4M

(a)

Fig. 7. Switched-capacitor cell: (a) switched-capacitor cell integrated with Current in D1 D 2 I eq

voltage-doubler SEPIC rectifier, (b) equivalent circuit of the switched- and D2 (avg) 2

capacitor cell employed in the proposed rectifier and (c) equivalent resistance n is an even number which is greater than or equal to two.

of the switched-capacitor cells. Vp: peak value of the input voltage; Vo: average value of the output voltage;

Po: output power; Ro: load resistance; Req: equivalent resistance of the

DV p IC S 1 max 2 IC S 1 min 2 ( 4 DV p Vo ) switched capacitor cell; Leq: equivalent inductance; iLi: ripple current of the

IC S 1 _ RMS = C S 2 _ RMS = , (5) inductor Li; VCi1: ripple voltage of the capacitor Ci1; fs: switching frequency;

2 V o D: duty cycle and thut: hold-up-time, ICS1max: maximum current in CS1; ICS1min:

IC o 3 _ RMS = IC o 4 _ RM S = minimum current in CS1.

(6)

( 2

2 DV p R o 2 ( IC S 1max IR o ) Vo 2 + V o 3 ) and

Vo Ro 2

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20 Ronc relation to the number of switched-capacitor cells (n) can be

[0.07, 14.4] seen in Table III.

12 Ronc

A. Dynamic Model for Control

SEPIC rectifiers, when operating in DCM, do not require a

[0.05, 4.72] [1.306, 4.44]

control loop for the input current because in this operation

4 Ronc mode the converter emulates a load with resistive

characteristic. Therefore, the proposed rectifiers need only an

0 output voltage control, which is demonstrated in Fig. 9.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 f s

The equivalent electric circuit shown in Fig. 10 is used to

Total charge - Tc Partial charge - Pc No charge - Nc

Ronc = Ron + Rce (a) analyze the dynamic model for the output voltage in relation

ics ics ics to the duty cycle of the proposed topology. It considers the

average quantities and it is valid for small signals.

The value of the current io illustrated in Fig. 10 is defined

by

d 2 I eq

io = . (8)

t t t 4M

(b ) (c ) (d )

Fig. 8. Switched-capacitor cell: (a) behavior of Req as a function of fs, (b)

current in CS for total charge mode, (c) current in CS for partial charge mode This current is modified when the output voltage (vo) or the

and (d) current in CS for no charge mode. duty cycle (d) is changed. However, vo is also dependent on d.

TABLE II

Therefore, there is a correlation between the variables io, d and

RANGES FOR THE OPERATING MODES OF CS vo, which has to be considered in the dynamic model.

Req regarding Therefore, the output current is defined as

Operating mode Operating Interval

minimal resistance

Tc fs 0.07 fs 0.07 3.27 pu d vo vo

fs 0.5 1.08 pu ( )

io d , vo = C oeq + , (9)

Pc 0.07 < fs < 1.306 dt Ro

fs 1.0 1.02 pu

Nc fs 1.306 fs 1.4 1.01 pu

where

TABLE III

SWITCHED-CAPACITOR CELL: GENERALIZATION OF THE NUMBER OF ( C ox1 + C ox 2 ) 4 DV p ( C ox 3 + C ox 2 )

D +

ELEMENTS AND VOLTAGE STRESS

C ox1C ox 2 Vo C ox 3 C ox 2 . (10)

Number of Elements or Voltage Stress Design Equation C oeq =

Number of Diodes 2n + 4 + Vo (1 D ) 4 DV p ( C ox 2 + C ox 4 )

Number of capacitors 2n Vo C ox 2 C ox 4

Value of the output voltage ( 2 + n )VCo1

Maximum voltage stress on Do2 and and

Vp

Do4

Maximum voltage stress on Do2, Do4, Vp ( C o1 + C S 1 ) C o 4 Co 2Co3

De1 and De4 C ox1 = ;C =

Maximum voltage stress on De2, De3, Vo

( C o1 + C S 1 ) + C o 4 ox 2 C o 2 + C o 3 , (11)

De5, De6 and De_n 2+n ( C o 4 + C S 1 ) C o1 C o1C o 4

C ox 3 = ; C ox 4 =

Maximum voltage stress on CS_n and Vo ( o 4 S 1 ) o1

C + C + C C o1 + C o 4

Co_n 2+n

n is an even number which is greater than or equal to two. Cox1, Cox2, Cox3 and Cox4 being auxiliary variables.

From the (9) is obtained likewise as in [10] the equation

D 2 I eq

ID e1 _ AVG ...ID e 6 _ AVG = . (7)

4M d vo vo . (12)

( )

io d , vo = C oeq

dt

+

Ro

C. Generalization of Switched-Capacitor Cell Number

The proposed converter is able to provide high output Applying (7) in (11) gives

voltage, since it can be generalized by adding switched-

DI eq D2

capacitor cells, in a modular way, as demonstrated in Fig. 1. (

io d , vo =) d vo , (13)

Thus, the number of components in the multiplication stage, 2M 4 M 2 Leq f s

the average values for the output voltage and the voltage stress

on the elements are directly proportional to the number of which, matched to (8), results in

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TABLE V

Vrf C p ( s) M pwm G (s) vo LIST OF COMPONENTS

Component Specifications

Inductance: 3.385 mH

Turns: 156

H vo Inductor Li

Wire: 16 AWG

Fig. 9. Bloc diagram for the output voltage control. Core: APH46P60

Inductance: 60.3 H

Turns: 29

Inductor Lo

iC oeq iRo Wire: 64 x 32 AWG

Core: EE42/20 3c94

Transistors S1 and S2 IPZ65R019C7 (650 V/19 m)

io ( d , vo ) C oeq Ro vo Diodes Do1 and Do2 MUR1560 (600 V/15 A)

Diodes De1 ... De6 C3D08060A (600 V/11 A)

Diodes D1 and D2 MUR860 (600 V/8 A)

Capacitors Ci1 and Ci2 B32672P5155K (1.5 F/520 V)

Capacitors Co 1 Co4 B43845-A0158-M (2 x 1.5 mF/250 V)

Fig. 10. Equivalent circuit of the output for voltage control.

Capacitors CS 1 and CS2 C4AEGBW6100A3NJ (100 F/450 V)

vo vmod

810 vo ( s )

G (s ) = =

k (15)

805 d ( s ) Ro C oeq s +

Dk

+1

2Vo

800

795 which represents the converter model for small-signal average

790 values, where

785 DRo I eq

k= . (16)

780 2M

4 5 T (s) 6 7 8

(a )

B. Validation of Dynamic Model for Control

805

The small-signal model proposed for the control was

validated by numeric simulation using the specifications

shown in Tables IV and V. During the test, at t = 4.2 s the duty

800

cycle is increased in 1.4% and after 1.8 s (t = 6 s) the value

returns to the standard value. This procedure provided the

output voltage waveforms of the converter (Fig. 2) and of the

795

model (15), which are shown in Fig. 11 (a) and (b). The

results reported in this figure demonstrate that the proposed

3.5 3.52 3.54 T (s) 3.56 3.58 3.6 model adequately represents the converter in steady and

(b) transient states. It can be seen, as expected, that the model

Fig. 11. Dynamic Model of the rectifier 2S with n = 2: (a) steady-state and

does not represent the 120 Hz ripple and high frequency

transient-state behavior, and (b) steady-state detail of vo and vmod .

ripple.

TABLE IV

DESIGN SPECIFICATIONS V. PROTOTYPE AND EXPERIMENTAL RESULTS

Specification Value

Input voltage 220 V A. Verification of the Proposed Rectifier

Frequency of the input voltage 60 Hz

Output voltage 800 V

In order to verify the concept of the proposed converters a 1

Output power 1000 W kW prototype was built. The three-state switch chosen for the

Switching frequency 50 kHz implementation was that referred to as 2S (Fig. 2 (c)). The

Maximum duty cycle 0.35

number of switched-capacitors cells used in the

Hold-up time 8.333 ms

Capacitors Ci1 and Ci2 ripple 20% implementation was two (n = 2). The prototype 2S (Fig. 12)

Inductor Li ripple 10% has a specific power of 0.4 kW/kg and power density of

0.31 kW/L. It was built based on the specifications and list of

DI eq D2 d vo vo .

components reported in Tables IV and V, respectively. The

d vo = C oeq + (14) experimental results were obtained with the rectifier operating

2M 2 dt Ro

4 M Leq f s

with rated power (1000 W) and in closed-loop.

The experimental waveforms for the voltage and the input

On applying the Laplace transform in (14) is obtained the

current are shown in Fig. 13. The current has a sinusoidal

transfer function

shape and it is in phase with the respective voltage, even

without a current control. It has a THD of 1.96% and power

factor of 0.9991. Its harmonic spectrum is shown in Fig. 14,

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B vCS 1 vo

C

A E D

vCo 4

10c

F vCo1

m

12

cm

m

cm 8 .8

.3c

7 .2 cm

11

T : 5ms

Fig. 12. Photograph of the rectifier 2S with n = 2 implemented: Fig. 16. Output voltage (100 V/div) and voltages on capacitors Co1, Co4 and

A = Capacitors CS1 and CS2; B = output capacitors; C = output inductors; CS1 (50 V/div) of the rectifier 2S with n = 2.

D = input inductor; E = capacitors Ci1 and Ci2; F = drivers for the switches S1

and S2.

vCS 2 vo

vg

iLi vCo 3

vCo 2

T : 5ms

Fig. 17. Output voltage (100 V/div) and voltages on capacitors Co2, Co3 and

T : 5ms CS2 (50 V/div) of the rectifier 2S with n = 2.

Fig.13. Input voltage (100 V/div) and input current (5 A/div) of the rectifier

2S with n = 2. where all harmonics are lower than the IEC61000-3-2 limits.

The waveforms of the voltage and output current can be

2.5

seen in Fig. 15. These variables presents a ripple of 120 Hz

and average values of 802 V and 1.26 A, respectively. Thus, at

2.0

Harmonic Value (A)

was 1010 W.

1.5

The waveforms of the output voltage and the voltages

IEC61000-3-2 Limits across the capacitors CS1, CS2, Co1, Co2, Co3 and Co4 are shown

1.0

Harmonic Value in Fig. 16 and Fig. 17. The results verified the voltage balance

among Co1, Co2, Co3 and Co4, which was supported by

0.5

capacitors CS1 and CS2. The capacitor voltages are around

200 V and these present two components, one low frequency

0

3 9 15 21 27 33 39 component (at 60 Hz) and another high frequency component

Harmonic Number (at 50 kHz). The average value of the output voltage (vo) is

Fig. 14. Harmonic spectrum of input current of the rectifier 2S with n = 2 and

IEC61000-3-2 limits.

close to 800 V, which is equal to four times the voltage on the

capacitors. This value is four times higher than the voltage of

a classic SEPIC rectifier and twice the voltage of the voltage-

doubler SEPIC rectifier addressed in [6], [9] and [10].

vo The experimental waveforms of the currents in the

capacitors CS1 and CS2 are shown in Fig. 18. As in the case of

iRo the voltage, the capacitor currents present two components:

one at 60 Hz and another at 50 kHz. The peak and rms values

are close to 15 A and 5.9 A, respectively.

The voltage waveforms across the semiconductors S1-S2

and Do1-Do3 are seen in Fig. 19 and Fig. 20, respectively. The

voltage stresses on these elements were 566 V-557 V and

565 V-562 V, respectively. From the design specifications

T : 5ms (listed in Table IV), the theoretical maximum voltage applied

Fig. 15. Output voltage (100 V/div) and current (300 mA/div) waveforms of

the rectifier 2S with n = 2.

on S1, S2, Do1 and Do3 is equal to 511 V, namely, the sum of

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iDo1

iCS1

iCS 2

iDo 3

T:10 s T:10 s

Fig. 18. Current through CS1 and CS2 (8 A/div) of the rectifier 2S with n = 2. Fig. 22. Current through the diodes Do1 and Do3 (8 A/div) of the rectifier 2S

with n = 2.

vS1

T :10 s

vDe1

vS 2 vDe 2

T:10 s vDe 3

Fig. 19. Voltages across the switches S1 and S2 (200 V/div) of the rectifier 2S

with n = 2. Fig. 23. Voltages across the diodes De1, De2 and De3 (100 V/div) of the

rectifier 2S with n = 2.

the peak value of the input voltage and a quarter of the output

voltage (for a case with two switched-capacitor cells). On the

vDo1 other hand, the conventional SEPIC rectifier with the same

specifications would have a theoretical voltage stress on the

semiconductors of 1111 V. Hence, it would be necessary to

use higher voltage devices, which would lead to higher

conduction losses.

The waveforms of the currents that flow through the

components S1-S2 and Do1-Do3 are shown in Fig. 21 and

vDo3

Fig. 22. These currents have one frequency component at

T:10 s 60 Hz and another at 50 kHz. The rms values of the currents in

Fig. 20. Voltages across the diodes Do1 and Do3 (200 V/div) of the rectifier 2S switches S1 and S2 are approximately 10 A and 9.5 A,

with n = 2.

respectively, while the average values of the currents in Do1-

Do3 are 1.28 A and 1.2 A, respectively.

The waveforms of the voltages across the diodes De1, De2

and De3 are shown in Fig. 23. The voltage on De1 has a

iS1 sinusoidal envelope with frequencies of 60 Hz and 50 kHz.

The maximum voltage stress was 309 V. The measured

voltages across De2 and De3 also have one component in low

frequency and another in high frequency (60 Hz and 50 kHz,

respectively). The corresponding maximum values of these

voltages are close to 204 V and 214 V.

The dynamic response of the converter to a load step of

iS 2 41% is demonstrated in Fig. 24. The output voltage presented

T:10 s an overshoot of 2% and settling time of 500 ms.

Fig.21. Current through the switches S1 and S2 (20 A/div) of the rectifier 2S

with n = 2.

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the efficiency at rated power was 93.9%. These results are

vo

significant because the rectifier does not use the soft

commutation technique and it operates in discontinuous

conduction mode. With regard to THD and PF, the best

performance occurred at rated power with values of 1.96 %

and 0.9991, respectively.

iLi B. Comparison between the Proposed Rectifiers and Other

Solutions

iRo The main goal of this section is to present a comparison of

T:200 ms the proposed hybrid rectifier with other bridgeless SEPIC

Fig. 24. Response dynamics of the rectifier 2S with n = 2: vo -100 V/div; iLi- rectifiers reported in the literature. Hence, the structures

5 A/div; iRo-1 A/div.

described in [10], [20] and [21] were used for comparison

94.5% purposes and to highlight the main advantages and drawbacks

of the proposed structure. In this regard, three converters

employing the three-state switch with two active switches (2S)

94.0% were considered.

Efficiency ( )

93.5% number of components. In contrast to the bridgeless SEPIC

rectifier [21], the proposed converter employs seven fast

diodes, one inductor and six extra capacitors. In relation to the

93.0% converter reported in [10], the proposed hybrid SEPIC rectifier

uses eight extra fast diodes and four extra capacitors. When

92.5% compared to the converter approached in [20], the proposed

100 200 300 400 500 700 800 900 1000

Output Power (W) converter has three fast diodes, one inductor and four extra

Fig. 25. Measured efficiency of the rectifier 2S with n = 2. capacitors.

A qualitative analysis is shown in Table VII. In relation to

1.000 the three bridgeless rectifiers considered ([10], [20] and [21]),

the proposed hybrid converter provides a higher reduced

voltage stress on the semiconductors. Consequently,

0.995

semiconductors that support lower voltage stress can be

Power Factor

0.990 output voltage with the same voltage stress on the

semiconductors regarding to the previously rectifiers.

In conclusion, the main contribution of the proposed

0.985

converter is that it provides lower voltage stress on the

semiconductors when compared to the bridgeless SEPIC

0.980

100 200 300 400 500 700 800 900 1000

rectifiers in [10], [20] and [21]. Furthermore, the gain of the

Output Power (W) proposed rectifier can be increased by adding more switched

Fig. 26. Measured power factor of the rectifier 2S with n = 2. capacitors and, thus, it has a generic static gain, which is

related to the number of switched-capacitor cells. However, as

06.5%

a drawback, it employs a higher number of components.

This paper proposed the integration of the single-phase

04.5%

voltage-doubler SEPIC rectifier with the switched capacitor

THD

03.5%

(SC) concept. As a result, a set of hybrid rectifiers was

generated. These rectifiers improve the static gain of the

voltage-doubler SEPIC converter without increasing the

02.5%

voltage stress on the semiconductors, making them suitable for

01.5%

applications that require high output voltage levels (above

100 200 300 400 500 700 800 900 1000 800 V). The structures, a theoretical analysis and the

Output Power (W)

experimental validation of this integration are the main

Fig. 27. Measured THD of the rectifier 2S with n = 2.

contributions of the paper.

The efficiency, THD and PF curves for the 1 kW 2S The switched-capacitor cell integrated to the voltage-

prototype are shown in Fig. 25, Fig. 26 and Fig. 27. The doubler SEPIC rectifier has extra diodes, which contribute to

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QUANTITATIVE ANALYSIS

cell, which can be implemented in three forms. Of these, the

Bridgeless Bridgeless Bridgeless

Proposed SEPIC SEPIC SEPIC

bridgeless version with two active switches (Fig. 1 (c) - 2S)

Characteristics Rectifier Rectifier Rectifier Rectifier was chosen for the theoretical analysis and experimental

1

in DCM in DCM in DCM in DCM verification. The converter implemented was tested at rated

[21]1 [10]1 [20]1

power (1 kW) and it provided a current with a THD of 1.96%,

Input current 0 0 0 0

control PF of 0.999 and efficiency of 93.9%. These results are

Current sensor 0 0 0 0 significant because the rectifier does not use the soft

Output voltage 1 1 1 1 commutation technique and operates in DCM.

control

Voltage sensor 1 1 1 1

Number of 2 2 2 2 ACKNOWLEDGMENT

Switches1

Number of fast 10 3* 2 7* The authors would like to thank the Brazilian governmental

diodes agency CNPq (National Council for Scientific and

Number of slow 2 2 2 2 Technological Development) for its contribution to this work

diodes

Number of 3 2 3 2 in the form of a grant provided to Paulo Junior Silva Costa.

inductors

Number of 8 2 4 4 REFERENCES

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Reduced Switch Stress, IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. was born in Cricima, Santa Catarina

20252034, Sep./Oct. 2010. State, Brazil, in 1979. He received the

[27] M. S. B. Ranjana, N. SreeramulaReddy, R. K. P. Kumar, A novel B.Sc., M.Sc. and Ph.D. degrees in

SEPIC based dual output DC-DC converter for solar applications, in Electrical Engineering from the Federal

Proc. PESTSE, 2014, pp. 15.

University of Santa Catarina (UFSC),

Paulo Junior Silva Costa was born in Florianpolis, Brazil, in 2004, 2006 and

So Jos do Rio Claro, Brazil, in 1988. 2010, respectively.

He received the B.S. degree in industrial He is currently an Adjunct Professor at

automation technology, in 2011, and the the Department of Electrical and Electronic Engineering

M.S. degree in electrical engineering, in (EEL) from the UFSC, and he also works as a Researcher at

2015, both from the Federal University of the Power Electronics Institute (INEP), UFSC.

Technology Paran (UTFPR), Ponta His interests include switched-capacitor converters,

Grossa, Brazil. He received the Ph.D. inverters, rectifiers, parallel operation of converters, high-

degrees in electrical engineering from the voltage dc-dc converters and conversion systems for small

Federal University of Santa Catarina (UFSC) in 2017. wind turbines.

His interests include PWM rectifiers, switched-capacitors, Dr Lazzarin is a member of the Brazilian Power Electronic

and DC-DC converters. Society (SOBRAEP), IEEE Power Electronics Society (PELS)

and IEEE Industrial Electronics Society (IES).

0885-8993 (c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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