Circuit Design

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Circuit Design

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You are on page 1of 15

The ABC Saw Mill is the smallest Canadian producer of fire wood. They wish to

automate their log-cutting efforts and have decided to design the conveyor belt

system shown in Figure 1. You have been commissioned to develop the

synchronous sequential saw controller that can detect the length of wood logs

and cut only the logs that are long. For simplicity, you may assume that all logs

are of only two sizes, either LONG or SHORT. Using two sensors (S 1 and S2),

the SHORT logs will never pass under both sensors at the same time, however,

the LONG logs will. The sensor input will be set to logic high when a log is under

the sensor, otherwise the input it will remain at zero. After a LONG log is

detected (i.e. the end of the log passes sensor S 2), the SAW output must be

asserted, which will pause the conveyor belt and lower the saw to cut the log.

You may also assume that there will always be sufficient space between logs

such that two logs will never be under the sensors at the same time.

For all input sequences that are not physically possible, ensure that your system

returns to the initial state. Furthermore, all unused states should return your

system to the initial state.

1) Draw the State Transition Diagram for the sequential saw controller.

2) Derive the State Transition Table for the sequential saw controller.

3) Draw the sequential circuit diagram for the sequential saw controller using

only positive edge-triggered JK flip-flops. Minimize any combination logic

using K-maps.

SOLUTION to Question 1

STATE STATE

A B S1 S2 A+ B+ JA KA JB KB SAW

0 0 0 0 0 0 0 X 0 X 0

0 0 0 1 0 0 0 X 0 X 0

0 0 1 0 0 1 0 X 1 X 0

0 0 1 1 0 0 0 X 0 X 0

0 1 0 0 0 0 0 X X 1 0

0 1 0 1 0 0 0 X X 1 0

0 1 1 0 0 1 0 X X 0 0

0 1 1 1 1 0 1 X X 1 0

1 0 0 0 0 0 X 1 0 X 1

1 0 0 1 1 0 X 0 0 X 0

1 0 1 0 0 0 X 1 0 X 0

1 0 1 1 1 0 X 0 0 X 0

1 1 0 0 0 0 X 1 X 1 0

1 1 0 1 0 0 X 1 X 1 0

1 1 1 0 0 0 X 1 X 1 0

1 1 1 1 0 0 X 1 X 1 0

SOLUTION to Question 1

S1 S2

AB 00 01 11 10

00

01 1

11 X X X X

10 X X X X

JA = BS1S2

S1 S2

AB 00 01 11 10

00 X X X X

01 X X X X

11 1 1 1 1

10 1 1

KA = B + S2

S1 S2

AB 00 01 11 10

00 1

01 X X X X

11 X X X X

10

JB = AS1S2

S1 S2

AB 00 01 11 10

00 X X X X

01 1 1 1 0

11 1 1 1 1

10 X X X X

KB = A + B + S1 + S2

Question 2: Sequential Circuit Analysis

The sequential circuit in Figure 2 is a sequence detector that asserts its output Z

when a 4-bit serial input sequence is detected. The serial input is denoted X.

This circuit is synchronized with respect to the clock signal CLK. The 16x3 ROM

has the following programming table:

INPUTS OUTPUTS

A3 A2 A1 A0 Y2 Y1 Y0

0 0 0 0 0 0 0

0 0 0 1 0 1 0

0 0 1 0 1 1 0

0 0 1 1 1 0 0

0 1 0 0 0 1 0

0 1 0 1 1 1 0

0 1 1 0 0 1 0

0 1 1 1 0 1 1

1 0 0 0 0 0 0

1 0 0 1 1 0 1

1 0 1 0 1 1 0

1 0 1 1 0 1 1

1 1 0 0 1 0 0

1 1 0 1 1 1 1

1 1 1 0 1 0 0

1 1 1 1 1 0 1

b) Draw the state transition diagram.

c) What four bit sequence does this circuit detect? (Hint: State 00 is the initial

state.)

SOLUTION to Question 2

(a)

QA QB X DA TB QA(t+1) QB(t+1) Z

0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 0

0 1 0 0 1 0 0 0

0 1 1 1 1 1 0 0

1 0 0 1 1 1 1 0

1 0 1 1 0 1 0 0

1 1 0 0 1 0 0 0

1 1 1 0 1 0 0 1

(b)

(c) 1101

Question 1 (Arithmetic)

Let ADD4 be a 4-bit adder. We will use this adder as a building block to design other

arithmetic circuits.

1- Consider MUL3 circuit shown in Figure 1(a). This circuit has a 4-bit input A and a 6-

bit output P such that P = 3*A. Design this circuit using a single ADD4 component and

HA/FA cells.

2- Consider the 4-bit adder shown in Figure 1(b). We call this adder ADD4_MOD. The

behavior of the circuit depends on the values of inputs M1 and M0 as shown in Table 1 .

For instance, the circuit performs the addition of the two 4-bit numbers A and B modulo 8

when M1M0 = 01. The result of this addition appears at output S. Output Cout is the

carry-out of adding A and B when M1M0 = 00, in all other modes Cout = 0. Design

ADD4_MOD using the following components : ADD4, multiplexers and logic gates.

M1 M0 Operation

0 0 A+B

0 1 (A+B)mod8

1 0 (A+B)mod4

Table 1

3- Carry-select adders (CSA) are used to cope with the carry propagation delays

encountered in ripple-carry adders. A typical CSA is made of smaller adder -blocks.

Some blocks are replicated to consider the cases when the carry-in is 0 and when the

carry-in is 1. An incomplete 12-bit CSA is shown in Figure 2. Complete this figure by

adding the missing components and connections.

Solution

1-

2-

3- Straightforward.

Question 2 (PLDs)

The truth table of a binary to excess-3 encoder is shown in Table 2. We like to implement

this circuit using a PLA.

1- Derive, using K-maps, the simplified expressions for each output and its complement.

2- Deduce a programming table for the PLA. You should minimize the number of product

terms.

ABCD WXYZ

0000 0011

0001 0100

0010 0101

0011 0110

0100 0111

0101 1000

0110 1001

0111 1010

1000 1011

1001 1100

1010 0000

1011 0001

1100 0010

1101 1101

1110 1110

1111 1111

Table 2.

Solution

1- W = BD + BC + AB'C'

W' = B'C + BC'D' + A'B'C'

X' = B'C'D' + AC'D' + A'BD + A'BC + AB'C

Y'= C'D + A'CD' + AB'C

Z = A'D' + B'C'D' + ABD + ACD

Z' = A'D + B'C'D + ABD' + ACD'

2- Functions : W, X', Y' and Z will be implemented. Total number of product terms 13.

Outputs F1,F2,F3 and F4 produce W,X,Y and Z, respectively.

ABCD (T)(C)(C)(T)

F1F2F3F4

BC 1 11 1

BD 2 11 1

AB'C' 3 100 1

B'C'D' 4 000 11

AC'D' 5 100 1

A'BD 6 010 1

A'BC 7 011 1

AB'C 8 101 11

C'D 9 01 1

A'CD' 10 010 1

A'D' 11 00 1

ABD 12 "111" 1

ACD 13 111 1

Q1:

(A) Simplify the following expressions using Boolean Algebra;

V = X Y Z + X Y Z + X Y Z + X Y Z + ( X + Y + Z )

P = A B C + A B C +A B C + ( A + B ) C

R=((M(N+K))(M+(NK)))

2- Obtain the truth table.

3- Convert the expression to all NAND form.

4- Implement the all NAND circuit.

5- Simplify the original output expression (as in 1).

A 1 2 1

3

2

1

C 2

3

1

3

B 1 2 2

1

3

Z

2

1

A 2

13

12

C 1 2

1- how two inputs NOR gate can be constructed from 2 inputs NAND

gates.

2- how you construct Y= ABCD using only 2 inputs NAND gates.

3- how 7486 XOR chip (contains 4 XOR) can be used to make an

XNOR gate using only 7486 chip.

(B) Design a logic circuit that will detect various inputs conditions for 4 inputs

(DCBA). The circuit will generate the following outputs:

- Output GT will be HIGH if the input value is greater than 9.

- Output LT will be LOW if the input value is less than 4.

- Output RNG will be HIGH if the input is greater than 6 and less than 11.

- Output signal TEN will be LOW if the input is equal to 10.

The design should include; Truth Table, K-Maps, and Logic equations.

Solutions

Q1 (A) V = X Y Z + X Y Z + X Y Z + X Y Z + ( X + Y + Z )

= X Z (Y +Y ) + X Y (Z+Z) + X Y Z

= X Z + X(Y + Y Z )

= X Z + X(Y + Z)

= Z + X Y

P = A B C + A B C +A B C + ( A + B ) C

= (A+A ) BC +A B C + A B C

= B C + C B (A + A )

= B C + C B

=C

R=((M(N+K))(M+(NK)))

= (M (N + K) (M + (N k) ) )

= ((M N K ) ( M N K ))

=1

Q1 (B)

(1) Z = A C + C B + (A B C)

(2)

A B C Z

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

(3) Z = (( A C + C B + (A B C)) )

= ( (A C) . (C B ) . (A B C) )

(4)

A B C

U4B

U3B

5

4

5

4

2

1

U1A

74HC00N

74HC00N

3

U2B

3

4 6

5

74LS12N

U2A

U1D

1

12

11 2 12

13

13

Z

74HC00N

74LS12N

U1C

9

8

10

74HC00N

(5) Z= A C +B C + A + B + C

= A ( C + 1) + B (C + 1) + C

= A + B + C

Q2 (A)

(1)

U5D

12

A 13

11

U7D U8D

12 12

74HC00N 11 11

13 13

U6D

12 74HC00N 74HC00N

B 11

13

74HC00N

(2)

U13D

U9D

A 12

11 12

13 11

B 13 U11D U12D

74HC00N 12 12

74HC00N 11 11 Y

U14D 13 13

U10D

12

C 11 12 74HC00N 74HC00N

13 11

13

D 74HC00N

74HC00N

(3)

U15A

U15B

1

A 3 4

2 6

B 5

7486N

7486N

1(High)

0 0 0 0 0 0 0 0 1

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 0 1

3 0 0 1 1 0 0 0 1

4 0 1 0 0 0 1 0 1

5 0 1 0 1 0 1 0 1

6 0 1 1 0 0 1 0 1

7 0 1 1 1 0 1 1 1

8 1 0 0 0 0 1 1 1

9 1 0 0 1 0 1 1 1

10 1 0 1 0 1 1 1 0

11 1 0 1 1 1 1 0 1

12 1 1 0 0 1 1 0 1

13 1 1 0 1 1 1 0 1

14 1 1 1 0 1 1 0 1

15 1 1 1 1 1 1 0 1

K-Maps

BA

00 01 11 10

DC 00 0 0 0 0

01

11 1 1 1 1 GT = DC +DB

10 1 1 (LT) = D C

BA

00 01 11 10

DC 00

01 1

11

10 1 1 1 0

RNG = B D C + A D C + D C B A (TEN) = D C B A

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