DATE

NAME OF PROCESSOR

CAPABILITIES r Maximum clock speed was 740 kHz r Instruction cycle: 92.6 kHz [8] (740 kHz /8 = 92.6 kHz, 10.8 µs instruction period) r Data moving instructions. r Arithmetic - add, subtract, increment, decrement. r Logic - rotate. r Control transfer - conditional (limited to current ROM), unconditional, call subroutine and return from subroutine. r Input/Output instructions. r Other - carry flag operations, decimal adjust, etc. r Instruction length can be one or two bytes. r Ran at 200KHz r Data moving instructions. r Arithmetic - add, subtract, increment and decrement. r Logic - AND, OR, XOR, compare and rotate. r Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts. r Input/Output instructions. r Other - Halt instruction. r Instruction length can be from 1 to 3 bytes. r Maximum clock speed was 2Mhz r The total addressable memory size is 64 KB. r The interrupt can be enabled or disabled using EI and DI instructions. r Data moving instructions. r Arithmetic - add, subtract, increment and decrement. r Logic - AND, OR, XOR and rotate. r r r r r r r r r r r r
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ARCHITECTURE

1971

4004 (intel)

Number of transistors: 2,300 Memory: Program Memory, Data, Stack Interrupts: None I/O ports: 16 4-bit input ports & 16 4-bit output ports Registers: 12-bit Program Counter, Stack Registers, 4-bit Accumulator, Index Registers r Instruction set: 46 r Addressing modes: Register, Memory Direct, Register Indirect, Immediate r r r r r

July 1972

8008 (intel)

Number of transistors: 3,500 Memory: Program Memory, Data, Stack Interrupts: Suppport non-maskable interrupt I/O ports: 8 input ports & 24 output ports Registers: Accumulator, Data Registers, Program Counter, Stack Register r Instruction set: 48 r Addressing modes: Register, Register Indirect, Immediate

December 1974

8080

Number of transistors: 6,000 Memory: Program Memory, Data, Stack Interrupts: Suppport maskable interrupt I/O ports: 256 input ports & 256 output ports Registers: Accumulator, Flag, Stack Pointer, Program Counter r Addressing modes: Register, Register Direct, Immediate

r Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts. r Input/Output instructions. r Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

August 1976

8085 (intel)

r Maximum clock speed was 6MHz r Data moving instructions. r Arithmetic - add, subtract, increment and decrement. r Logic - AND, OR, XOR and rotate. r Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts. r Input/Output instructions. r Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Number of transistors: 6,500 Memory: Program Memory, Data, Stack Interrupts: 5 interrupts I/O ports: 256 input ports & 256 output ports Registers: Accumulator, Flag, Program Counter, Stack Pointer r Instruction set: 48 r Addressing modes: Register, Register Indirect, Direct, Immediate r r r r r

September 1978

8086 (intel)

r Maximum clock speed was 10MHz r Data moving instructions. r Arithmetic - add, subtract, increment, decrement, convert byte/word and compare. r Logic - AND, OR, exclusive OR, shift/rotate and test. r String manipulation - load, store, move, compare and scan for byte/word. r Control transfer - conditional, unconditional, call subroutine and return from subroutine. r Input/Output instructions. r Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Number of transistors: 29,000 Memory: Program Memory, Data, Stack Interrupts: INTR, NMI I/O ports: 65,536 8-bit I/O ports Registers: Code Segment, Stack Segment, Data Segment, Extra Segment, Accumulator, Base, Count, Data, Stack Pointer, Base Pointer, Source Index, Destination Index, Instruction Pointer, Flags r Addressing modes: Implied, Register, Register Indirect, Direct, Immediate, Based, Indexed, Based Indexed, Based Indexed w/ displacement r r r r

February 1982

80286 (intel)

r Maximum clock speed was 12MHz

October 1985

80386(intel)

r Maximum clock speed was 40MHz

r Number of transistors: 134,000 r 16-bit Internal Registers 16-bit External Data Bus 24-bit Address Bus r Number of transistors: 275,000 r 32-bit Internal Registers 32-bit External Data Bus 32-bit Address Bus r Number of transistors: 1,200,000 r 32-bit Internal Registers 32-bit External Data Bus 32-bit Address Bus 8 KB Cache r Number of transistors: 3.1 million r 32-bit Internal Registers 64-bit External Data Bus 32-bit Address Bus 8 + 8 KB Cache r Number of transistors: 3.3 million r Quad-pumped Front Side Bus. With the initial Banias core, Intel adopted the 400 MHz FSB first used in the Pentium 4. The Dothan core moved to the 533 MHz FSB, following the Pentium 4's evolution.

April 1989

80486 (intel)

r Maximum clock speed was 100MHz

March 1993

Pentium

r Clock speed: 60 MHz

November 1995

Pentium Pro

r Maximum clock speed was 200MHz

r Larger L2 cache. Initially 1 MB in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states. r SSE2 support. r A 12-14-stage instruction pipeline to achieve higher clock speeds than the Pentium III-M.

r Dedicated register stack management. r Addition of global history to branch prediction table. r Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations. r Number of transistors: 7.5 million r SDR32-bit Internal Registers 64-bit External Data Bus 36-bit Address Bus 16 +16 KB Cache r Number of transistors: 7.5 million r SDR32-bit Internal Registers 64-bit External Data Bus 36-bit Address Bus 0 Cache r Number of transistors: 9.5 million r SDRAM and RDRAM 256/512 Level 2 Cache r Number of transistors: 42 million r RDRAM, SDRAM, DDR SDRAM, DDR2 SDRAM 265/512 Level 2 Cache r Number of transistors: 42 million r 128 64-bit general purpose registers 2001 Itanium r Maximum clock speed is 1.73GHz r 128 82-bit floating-point registers r 64 1-bit predicate registers r Maximum clock speed is 1.73GHz r The Pentium M (Mobile) is a CPU for laptops.It uses throttling, or adjusting the

May 1997

Pentium II

r Clock speed: 300 MHz

April 1988

Celeron

r Clock speed: 400 MHz

Feb 1999

Pentium III

r Maximum clock speed is 1.4GHz

November 2000

Pentium 4

r Clock speed: 1.5 GHz

March 2003

Pentium M

r Number of transistors: 55 million

clock speed to the lowest rate necessary, to conserve power to the laptop. r Maximum clock speed is 3.73GHz r Number of transistors: 55 million r Based on Core microarchitecture July 2006 Core2Duo r Maximum clock speed is 3.33GHz r Number of transistors: 253 million r Level 2 cache 4 MB Nov 2006 Core 2 Extreme r Maximum clock speed is 3.33GHz r Number of transistors: 582 million r Level 2 cache 8 MB

May 2005

Pentium D

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