The Characteristics of ASICs

The remarks that follow further discuss some trade-offs of ASICs with respect to the following categories:
y y y y y y

Complexity Silicon Efficiency Design Risks Prototype Turnaround NRE CAD / CAE Support

y Performance
Complexity
Complexity here means the number of transistors (or the amount of logic and/or memory) per given amount of area, plus the associated interconnect capability Current Array-Based and Cell-Based chips accommodate as many as 20,000,000 usable logic gates on a single die. Array-Based designs -especially in a Channel-Free Array technology - are capable of realizing functions that represent actual system building blocks and incorporate system memory functions on the same die.

The Array-Based memories do tend to be about 5 times less dense than CellBased memories because they are constructed out of the gates on the master slice. And full custom memories would provide much higher densities than do Array-Based memories. But in fact many designers who are using the Array-Based technologies to get fast turn around tend to be using very small ³scratch pad´ or ³cache´ types of memories which fit very well into the ASIC concept .

Silicon Efficiency
Array-Based technologies focus on fast implementation of logic integration onto a single chip, rather than on absolute highest density. Cell-Based designs allow you to get more logic onto a chip in a given area. Cell-Based designs feature transistors and routing tracks whose gradations of size are finer than those in Array-Based products. Thus Cell- Based designs use silicon more efficiently than Array-Based designs .

NRE
NRE (³Non-Recurring Engineering´) charges are the costs associated with developing an ASIC . NRE is based on a number of factors like: y The complexity of the design, y The technology chosen (# of masks required). y The amount of work to be done by the customer and by the silico vendor. y The need for special cells or procedures. y The type of package required. y The schedule the number of layers of metal. The more work the silicon vendor does and the more special the requirements, the higher will be the NRE . The more work the customer does, the lower the NRE . Array-Based designs require the fewest number of design-specific masks and therefore offer the lowest NRE to prototypes.

Cell- Based designs require all masks to be generated for the chosen process and therefore the NRE charge will be higher for a Cell-Based design than for an Array-Based design.

Design Risks
The penalty for discovering a design error is higher for a Cell-Based ASIC than for an Array-Based ASIC . Mistakes after prototype fabrication in Array-Based designs usually only require that the metal mask layers be redone. On the other hand, design changes for a Cell- Based design may require that all masks be redone .

Prototype Turnaround Time (TAT)
Designs that require a complete mask set (Cell- Based) will always require more time to manufacture than designs which use a basic set of diffusion masks and only require customization at the metal layers (Array-Based). This difference in time could be anywhere from one week to 4 weeks depending on how fast the silicon vendor can get masks from the mask shop and depending on how long the FAB cycle is for a given process.

CAD / CAE Support
The use of EDA tools ensure: y y y y y y y Clean documentation. Reusable data . Functional verification. Easy modification. Automated rule check. Back-annotation (synchronization between schematic and layout). Bill of material.

Performance
The two most critical parameters that have been used to measure the worth of new technologies have been speed and power. High power circuits are normally fast, but the increased power requires larger power supplies and tends to heat up the junctions on silicon chips which slows the devices. In today's most dominant ASIC technology - CMOS - high power can cause accelerated junction temperatures which can slow down speed . One way to reduce the power and still maintain speed is to develop circuits such as differential pairs that do not switch from voltage rail to voltage rail .