A Thesis presented to the faculty of the Graduate School University of Missouri—Columbia

In Partial Fulfillment Of the Requirements for the Degree Master of Science

by SCOTT CASTAGNO Dr. Randy Curry, Thesis Supervisor MAY 2006

© Copyright by Scott Castagno 2006 All Rights Reserved

Keith Lechien. and Matt Aubuchon provided valuable collaboration and assistance throughout my graduate studies. guidance. Laura Heffernan.ACKNOWLEDGEMENTS I would like to thank Dr. Peter Norgard. All of his help and dedication is greatly appreciated. ii . Kenneth McDonald for his willingness to provide technical support for the work. Also. I would like to recognize Dr. Randy Curry for his assistance. Additionally. and support with the research and writing of this thesis. student colleagues Josh Leckbee.

...................................................................................................... ii TABLE OF CONTENTS........................1 VOLTAGE GAIN AND INDUCTOR DERIVATION...............0 THEORETICAL CASCADE BOOST DESIGN ........................................................0 INTRODUCTION .....................................2 THE BOOST CONVERTER............................................................................................................................. iii LIST OF TABLES...... 13 2...............................................2 FILTER CAPACITORS ...............................5 ASYMMETRICAL SWITCHING ... 1 REFERENCES FOR CHAPTER 1............... 22 2....... 9 CHAPTER 2.4........... 17 2.......... 27 2............................3 DISCONTINUOUS MODE ....................... vii LIST FIGURES ....4..................................1 SWITCH-MODE CONVERTERS.........................0 .................... 11 2.......................... 29 iii ......... 21 2........................................................4 CASCADE BOOST CONVERTER DESIGN ............................................................................................................................. x CHAPTER 1....................................................................................................................TABLE OF CONTENTS ACKNOWLEDGEMENTS............................ 11 2...........................................................

...............................................1 IGBT CAPACITANCE ....6 INITIAL DESIGN VALUES AND SIMULATION RESULTS OF AN IDEALIZED MODEL ................................................ 57 3....................................... 73 CHAPTER 4...... 41 3................4 SECOND STAGE SWITCH DESIGN OPTIMIZATION ............. 56 3............................................................................1 IGBT SWITCHING DESIGN THEORY............................................. 75 4........................................................................ 75 4................................3 IGBT SWITCHING THEORY CONCLUSION...2 CURRENT DIAGNOSTICS .......3 SECOND STAGE DETAIL ............................................ 31 REFERENCES FOR CHAPTER 2............................................0 DIAGNOSTICS OF THE CASCADE BOOST CONVERTER PROTOTYPE .........1 VOLTAGE DIAGNOSTICS ........... 68 REFERENCE FOR CHAPTER 3...................1.................................................................................................... 44 3................ 62 3....0............ 39 3................0 .........3 OSCILLOSCOPE ....0 CASCADE BOOST CONVERTER PROTOTYPE DESIGN...................1..................................................... 37 CHAPTER 3........................................2 FIRST STAGE DETAIL ... 77 4...................................................................... 78 iv .............. 38 3......2 THE TURN-OFF TRANSIENT OF IGBTS .......................................1........2..............................................................

................................ 101 CHAPTER 6.......CHAPTER 5.......... 128 v ....4 TOTAL COMPONENT LOSS CALCULATION .................1 NEAR-TERM TECHNOLOGY BASED SCALING .......................................................................................................................1 MEASUREMENT OF THE FIRST STAGE IGBT LOSS ............................0 CASCADE BOOST CONVERTER PROTOTYPE RESULTS ...............0 CASCADE BOOST CONVERTER SCALING TO HIGHER POWER LEVELS............................. 88 5.2 FIVE & TEN-YEAR FUTURE TECHNOLOGY SCALING ...........2.0 CONCLUSION......................................................2....................................... 99 REFERENCES FOR CHAPTER 5...... 102 6..............................0.. 103 6........................ 123 CHAPTER 7....................... 125 APPENDIX A........................................................ 94 5........1 CASCADE BOOST CONVERTER OUTPUT AND EFFICIENCY ....0 .........3 OPTIMIZATION OF THE PROTOTYPE CONVERTER................3 MEASUREMENT OF DIODE LOSSES .............. 80 5.......... 79 5.............. 112 REFERENCE FOR CHAPTER 6.....2 COMPONENT LOSS ANALYSIS ..2..2............................... 98 5.......... 88 5......................................................................................... 92 5..2 MEASUREMENT OF THE SECOND STAGE IGBT LOSS ................................

.................................................................................................................................................................... 132 APPENDIX D............................................................................................. 134 vi .....................APPENDIX B ........................ 131 APPENDIX C ......................................

... peak current.....1 Cascade boost converter prototype design goals.......... ........................... 68 3................ 79 5............ .......................... 77 4............. usable rise time..... max continuous current.......................7 Cascade boost converter parameter comparison of 3.....1 Cascade boost converter prototype design goals................................. 19 3.3 mH.....1 Comparison of voltage gain and inductor values over a range of duty ratios and voltage gain ratios. Incremental current is the minimum current at which the inductance will be decreased by 5% from the initial (zero-DC) value...................... ............ 72 4. 60 3....................................................................... ..... 67 3....................5 Total cascade boost converter prototype volume and mass............. 76 4......3 Volume and mass of first stage components using COTS components........................ DCM inductor held at 3......... 84 5..............2 Average value data of the system operated at 5 kV output...... 84 vii ............3 Efficiency and loss for the first and second stages operated at 5 kV output.... ..... ... 61 3.... 71 3..........1 Voltage probes for circuit diagnostics including attenuation factor and bandwidth.... 78 5......................................3 kV and 1200 V IGBTs. . ........... 39 3..............LIST OF TABLES Table 2..6 Turn-off loss comparison of the two IGBT designs..... CCM Lmin adjusted to keep boost converter in CCM...........................4 Volume and mass of the second stage components....3 Current monitors for circuit diagnostics including output voltage per amp.. ..............2 Caddell-Burns inductor specifications....2 Measurement and diagnostic equipment implemented..

............................6 First stage components volume and mass for the near-term 60 kV....... ... The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter......11 Summary of the key parameter estimates for SiC devices in 5 and 10 years. .. ................. corresponding to 90% efficiency.. .............................2 Ideal parameters calculated for a 60 kV......4 Number of IGBT modules in series and parallel for assembly of S1 and S2.............................9 Total near-term projected component volume and mass and complete system volume and mass of a 300 kW converter... 92 5......7 Summary of second stage IGBT data.................. ...... .......... .. 111 6.........3 Switching parameters adjusted............................ 113 6......... 300 kW module..................... 104 6.........12 Number of devices to be placed in series and parallel for the 5 and 10-year time frames for the 300 kW converter’s first and second stage switches......... 116 6.. 88 5.......4 First stage and second stage voltage data of the cascade boost converter prototype as input voltage is varied from 0 V to 100 V............................... 300 kW converter....................................... 110 6... 84 5.......................................................... .................................................................................... 300 kW converter...................... . 102 6..8 Breakdown of average component power loss..............8 Estimated volume and mass of components of the near-term 60 kV................................ 94 5.. 111 6....... ...... 119 viii ......5..............13 First stage component projected volume and mass for the 5 & 10-year trend in a 60 kV................. 116 6..5 Expected voltage and current per IGBT..............10 Properties of SiC that will enhance power semiconductor devices.......... 300 kW cascade boost converter..1 Cascade boost converter specifications for a 60 kV.................................. 110 6........................... 99 6.................... 106 6.. and total average turn-off loss........ .. 300 kW converter..6 Summary of the first stage IGBT data....7 Second stage components volume and mass for the near-term 60 kV................. .... ...... ...............5 Cascade boost converter operating conditions for the component loss analysis .................. 104 6............................. 106 6................................................................. 300 kW converter module....

...........6............16 5-year total projected component and complete system volume and mass for a 60 kV................... The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter... 119 6......15 Estimated total volume and mass of each component category in a 60 kV.................... ..... 300 kW converter module.........17 10-year total projected component and total system volume and mass for a 60 kV........ 119 6....................................... 300 kW converter module................ The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter................. 300 kW converter module......... 119 6............................ 120 ix . ............................. 300 kW converter module.............14 Second stage component projected volume and mass for the 5 & 10-year trend in a 60 kV.....

......5 Comparison of DCM to CCM (R=25 kΩ..... 33 2......................... which correlates to a voltage ripple of less than ± 0................... L=3.....3 Discontinuous Inductor Current.............................. the current remains greater than zero...................1 General diagram of a generic DC-DC switch-mode converter.. R3 were inserted into the model to avoid convergence problems....... 6 1............ and C1 (black)............................................ 12 2................. 23 2........5%............... ................ ............2 CPI gyrotron cross section................................ .... f=10 kHz.............................................. 7 2... 21 2................... 34 x ...7 V................................. and ∆1 and ∆2 are the duty ratios of the diodes and fall time of the inductor current............................. L2 (blue).. During the fall time of the inductor current....2 Single Stage Boost Converter . D is the switch duty ratio and ∆1 is the diode duty ratio or the fall time of the inductor current.................... 15 2........................ ......... 15 2...10 Idealized Pspice circuit model using derived component values.................. D is the switch duty ratio.............3 mH) ....... High dif/dt occurring at diode turn-off......1 Schematic of a simplified cascade boost converter..............3 CPI depressed collector configuration...................9 Example of the current waveforms of L1 (red)... 14 2................................... 19 2................................ 22 2......11 Simulated output voltage of the second stage/converter............. Resistors R1.....................................4 Continuous Inductor Current.................. ∆V = 47..................6 The CCM diode and inductor currents.................................LIST OF FIGURES Figure 1.. ................................ R2.............................. 21 2........................ 4 1...................8 Simplified Cascade boost converter schematic...........7 The DCM diode and inductor currents ......

............................. 70 5................ 81 5.... td(off): dealy time.................................................................2 Cascade boost DC converter output voltage...................... 67 3........12 Power loss waveform of the two 3... tf2: 2nd current fall-time................ 57 3............. extends primarily into the n....... and the depletion region width........ 62 3........... .............3 kV IGBTs in series.....12 Simulated voltage across C1 and current through L1.......... ... ...... 42 3......... tf1: 1st current fall-time.............. 64 3.....................8 Schematic of second stage components......... Rdrift...... internal MOSFET and BJT...... ......................drift region due to high doping concentration of the p+ body region...... 70 3. 42 3............... where the zero occurs at junction J2.. ..... Wd............... 39 3.............................. the average output voltage is displayed at 5010 V.......................... 35 2...... 47 3..............................6 Schematic of first stage components.............5 PNP transistor layers in the IGBT: Epeak occurs at the junction J2..................................................................... The integrated energy loss is 126...... 59 3... 35 3......................................................5 mJ per pulse............ 47 3.9 The IGBT stack with six IGBTs in series....1 First stage DC output voltage..7 Thermaflo E3045 heat sink profile............ for a voltage gain of approximately 10 from the 503 V first stage output. wire wound resistors for dissipation of the 1 kW output of the prototype.... .................1 Bench top cascade boost converter prototype.............10 The output Load with 10 series Ohmite.................................. operating as the second stage switch......2.................. 82 xi ......... The x axis is the distance along the pnp layers......4 Cross-section of the NPT IGBT............................ and drift region resistance..................... switch capacitance................................ tvr: voltage rise-time......2 The IGBT equivalent circuit including.......... for a voltage gain slightly of 5 from the 100 V input..3 The IGBT turn-off waveforms in a clamped inductive load.........13 Simulated current through L2 with the second stage output voltage across C2.................11 Voltage and current waveforms of two 3.................. which results in an average power loss of 1139 W..3 kV IGBTs in series as the second stage switch of the cascade boost converter with and output of 5 kV and 1 kW............ the average output voltage is displayed at 503 V.........

.......................13 Second stage diode voltage and current waveforms.....................................614 and .........11 First stage diode voltage and current waveforms...................2 and 2.................................................................4 Efficiency of the individual stages and the overall converter......... with constant switching duty ratios of ..........................10 Second stage IGBT stack turn-off power loss.......3 First stage and second stage output voltages as input voltage is varied from 0 to 100 V....................................7 Turn-off voltage and collector current waveforms of the first stage IGBTs in parallel.......................... 97 5........7 W average loss.............................................................. ...............1 300 kW converter volume scaling from estimated technology trends........ 85 5.. 122 A..............2 and 2................ 121 6.....................4 MW converter volume scaling using parallel 300 kW converter modules.129 xii .....................................................457 mJ per pulse and average power loss is 4......................................................................................... 121 6..................... ......... 95 5.14 Second stage diode power loss waveform..................................9 Turn-off voltage and current waveforms of the second stage IGBT stack.......................................... ..5 First stage experimental and simulated input currents when the converter is operated with a 100 V input and 5 kVoutput..................................................513 for the first and second stages respectively............. . 93 5............................1 IGBT trigger module...6 Second stage experimental and simulated input currents when the converter is operated with a 100 V input and 5 kV output.............67 W...................... 85 5... 122 6..........................2 300 kW converter mass scaling from estimated technology trends. Integrated energy loss is 0...12 First stage diode power loss waveform......................................83 mJ at 20 kHz for 98....................................................................................... 96 5.......................57 W average loss........................................ ...........82 mJ per pulse and average power loss is 1..... Integrated energy loss is 0.....................13 W... The integrated turn-off energy loss = 11............................. 93 5.4 MW converter mass scaling using parallel 300 kW converter modules..................3 1...............8 First stage turn-off power loss.................. 87 5..........6 mJ at 9 kHz for 104.. . 97 6.. ....................5.... The integrated turn-off loss = 4..... 91 5... 91 5..................................... ................... ...............4 1............. 87 5....... ..

.......... 129 A..................................... 130 C.................3 IGBT gate driver circuit............................ 133 xiii ......................2 Power oscillator.A................................IGBT................. Non-Punch Through (NPT).................. .....................1 Experimental on-state forward conduction voltage and trend line of the International Rectifier IRGP30B120KD-E 1200 V..... Vg = 12...............................................5 V........................................... 60 A rated.........................

The development of power conditioning technology has led to advancements in the area of switch-mode power converters [3-4]. For military applications.CHAPTER 1 . The power conditioning becomes a significant factor of the total size and weight of these systems.0 INTRODUCTION The demand for compact electrical systems has motivated size and weight reduction of power conditioning architecture sub-systems. in addition to technical risk mitigation and adhering to the stringent reliability requirements for operation in military environments. where new technologies and innovation must develop highly compact and lightweight conditioning architectures in order for such emerging military technologies to move forward. or boosts. Switch-mode power conversion topologies are highly common among electronic devices and power conditioning designs. or boost converter [5-7]. they face engineering challenges to meet the size and weight requirements for integration on mobile platforms. The boost converter is a DC to DC converter that simply steps-up. However. and electronic weapon systems [1-2]. the government has funded the development of compact high voltage electrical systems for combat vehicles that require large scale power conditioning. These systems include electromagnetic launchers. AC to DC boost converters are used as power factor correction (PFC) circuits for the front end of power conditioning systems requiring a unity power 1 . A switch-mode converter circuit topology familiar to the subject of power electronics is the step-up. electromagnetic armor. Utilizing the same circuit operation. These technologies have the potential for revolutionizing military engagement. the input voltage to a higher output voltage.

In converter designs for high voltage applications. Converter designs in this regime have the ability to exceed 90% efficiency [8-10]. commercial boost converter circuits are implemented in systems requiring power conditioning levels ranging from less than 10 W to multi-kilowatt. switch-mode converters and high voltage power conditioning systems benefit with higher switching frequencies. and have output DC voltages in the hundreds of volts range or less. The general operation principles of switch-mode converters and typical boost converter design equations are discussed in this thesis. over existing silicon (Si) devices. which impacts component size. and lower 2 . For example. thermal management.factor interface with AC power sources. for solidstate switch technology the capability of high voltage solid-state devices is advancing. For instance. lifetime. Solid-state components rated higher than 1 kV can limit switching frequency and efficiency due to typically higher switching loss. high voltage switching is a significant design challenge. with step-up ratios on the order of 10. and higher efficiencies from improved. wide band-gap semiconductor materials like silicon carbide (SiC) offer advantages. such as higher electric field breakdown strength. and provides the ability to create more compact system designs. faster switching. Generally. Similarly. greater power densities. The pulsed power industry also has taken advantage of this technology as solid-state switching provides advantages such as increased reliability. emerging solid-state switch technology. and total power density. and high voltage power modulator designs have taken advantage of the solid-state technology [11-14]. Fortunately. control. high voltage thyratrons and spark gaps have been replaced by solid-state switches. as a background to the design of the cascade boost converter.

capacitor. and a simplified schematic is shown below in Figure 1. which has a significant potential for reduction in size and weight through advances in the aforementioned SiC. This converter is composed of two series arranged boost converters and develops a high input to output DC-DC voltage step-up gain from the two stages. thus shrinking passive components. and nanocrystalline technologies. The topology will suitably be referred to as the cascade boost converter. developing high voltage capacitor dielectrics are enabling capacitive energy storage in smaller volumes. The circuit topology investigated in this research project is a high voltage transformerless DC-DC switching converter. expanded voltage capability will reduce the number of series devices in stacked assembly designs. Also. In addition to semiconductors. Already.switching loss. High voltage diodes with a voltage rating of 10 kV or higher are anticipated to emerge as the first generation of high voltage SiC devices with 5-10 kV rated transistors subsequently available. The anticipated SiC technology will allow the converter to operate at higher switching frequencies. and nanocrystalline magnetic core materials have already shown improvements in transformer and inductor core reduction. 3 . 1200 V SiC diodes exhibit lower loss and can allow converters to operate at higher frequencies. A semiconductor paradigm shift of mature wide band-gap devices for high voltage switching may occur within a 10-year time frame.1.

this converter is certainly not limited to highpower microwave systems. The cascade boost topology is a potential enabling technology for systems for mobile platforms by fulfilling power conditioning size requirements. Gyrotrons.L1 D1 L2 D2 Vs S1 C1 S2 C2 RL Figure 1. originally developed in the 1960’s. The Air Force has accelerated research and development of Directed Energy systems using high-power microwave and laser technology. The Department of Defense (DOD) has developed microwave architectures for integration onto airborne. These Directed Energy weapon systems can provide non-lethal tactical solutions for the military such as remote disruption or destruction of enemy electronic systems and even physically stunning enemy combatants with applied radiation on the subjects. and this effort is expected to continue well into the twenty-first century [15]. However. Since the inception of the 4 . A typical high power microwave source is the gyrotron microwave tube. and land vehicles. The output can be tailored to meet the needs of a wide variety of applications. A particular application for which the cascade boost converter is designed is the power conditioning for high power microwave tubes. sea.1 Schematic of a simplified cascade boost converter. Directed Energy weaponry provides the United States with means for tactical advantage over the country’s adversaries where casualty mitigation is an objective. were utilized for electron cyclotron resonance heating of plasmas in fusion experiments [15].

3. where the collector is grounded (depressed in voltage relative to the body) as shown in Figure 1. In a Gyrotron. The continuous electron beam. and United States have developed megawatt continuous power class tubes [15]. after passing through the first cavity. A cross section of a CPI gyrotron is shown in Figure 1. 40A power supply is utilized to power the megawatt output Gyrotron. mega-watt class gyrotron tubes require the electron gun cathode power supply to deliver 20 A or greater [18]. Japan. The typical efficiency of a single extraction cavity Gyrotron is 20%. while multiple extraction cavities exhibit efficiencies of 40-45%. has manufactured Gyrotrons up to 1 MW power levels at efficiencies of 20-45% [17]. imparting a helical motion to the electron beam [16]. The body of the tube is biased at +20 kV in the depressed collector mode of operation. The Gyrotron consists of a cathode.2. France. a ceramic metal housing. The 20 kV body 5 . A 60 kV. produces a periodically bunched beam [16]. Gyrotrons with an extraction efficiency of 40-45% and megawatt power levels are under development [17]. Communication and Power Industries (CPI). This helical motion allows the coupling of the electron beam to a fast wave structure for extraction of the microwave power [16]. superconducting magnets. a cathode at modest 40-85 kV voltage levels injects an electron beam into a 2-3 cavity structure [16]. Gyrotron tubes generate high power and high frequency microwave radiation that is applicable for Directed Energy systems. The predominant manufacturer of Gyrotrons in the United States.Gyrotron. a vacuum pump (VacIon) and a collector. In general. An external magnetic field is also applied. consortiums in Russia.

Figure 1. The efficiency of the Gyrotron is somewhat determined by the regulation of the power supply according to CPI.0.0.2 CPI gyrotron cross section.5%. 6 . the 60 kV supply must also have a minimum regulation of +/. highly regulated power supply.1%. The 20 kV power supply is typically regulated to +/. Thus.supply is a 50mA.

highly regulated supply (+/.3 CPI depressed collector configuration. moderately regulated supply (+/. stepped up from a 100 V input.5% regulation) Figure 1. Boost converter theory.0. The prototype converter has demonstrated an output of 5 kV at 1 kW.0.1% regulation) 2– High current. an experimental cascade boost converter prototype for design validation. This modular approach extends the flexibility for many applications and provides redundancy for increased reliability. which requires a 60 times step-up ratio for a 60 kV converter output. The load utilized in the tests is a resistive load. The cascade boost converter has been selected to operate at 60 kV and 300 kW at full power. where the 7 .0.(2) + 60 kV 40 A _ (1) 20 kV 50 mA + Collector Voltage Divider for Sensing Body Gyrotron 1– Low current.5%) is achieved with appropriate output filtering and a precise boost converter control system. with the ability to be modularized for higher power conditioning output by paralleling modules. and the converter was designed for analysis and circuit demonstration in the laboratory environment. Power regulation (+/. based on the high current gyrotron power supply requirements. and theoretical system scaling to mulitmegawatt output levels is presented in the following chapters. The input for the design of the converter has been selected at 1 kV. for a total step-up ratio of 50. an idealized converter design.

300 kW converter designed for near-term. 8 . the cascade boost converter prototype is used to estimate the volume and mass of a 60 kV. This analysis includes individual component power loss and performance in relation to the system performance. namely the switches. This research project also includes the review of high voltage solid-state switching theory and switching designs of the cascade boost converter. and 10-year projected technology trends. diodes. The scope of the prototype converter analysis is centered on the main boost circuit components. inductors. and capacitors of the converter. 5-year. and projects the potential for the compact power conditioning systems based on the topology of the cascade boost converter.converter was operated at a constant input and output voltage. Finally. The scaling trend of the cascade boost converter demonstrates the dramatic reduction possible for such a system.

Gaudet. 1995. Hart. of Power Modulator Conf. New York: Van Nostrand Reihold Company.A. McNab. of PESC. 591-596 vol. 2. 17.P. pp. pp. 7.G. “Research issues in developing compact pulsed power for high peak power applications on mobile platforms. “Comparison of experimental losses among six different topologies for a 1. Semiconductor Power Electronics.G. H.REFERENCES FOR CHAPTER 1. 12651271 vol. using IGBTs.” Proceeding of the IEEE.. 1986. 9-13. “A new. 1999. N. pp. 50 kV solid-state kicker pulser. of Particle Accelerator Conf. C. Undeland. Power Electronics. pp. July 2002. of APEC.J. 2. of Energy Conversion Engineering Conference. 1..” in Proc. Yungtaek. pp. 469-476. 9 . New York: John Wiley & Sons. W. July 2004. Gaudreau. of Pulsed Power Conf. L.M. 1. of INTELEC. “Design and testing of a fast. 2000.W. No. D. [11] E. 359-363 vol. pp.A. Upper Saddle River. 1180-1196.” in Proc. Hoft. Robbins. 106-109. 1997. Huber. G.” IEEE trans. I. 2003. 1.R. [2] [3] [4] [5] [6] [7] [8] [9] [10] J. soft-switched.6 kW boost converter. “Power electronics innovation with next generation advanced power devices. pp. 2003. NJ: Prentice Hall. Ohashi. vol. 92. 1995. W. 547-549 vol. vol. “Advanced power converters for More Electric Aircraft applications. [12] M. Introduction to Power Electronics. Canesin.” in Proc. “A design approach for server power supplies for networking applications. 2nd Edition. pp. “Developments in battlefield power technology. Mohan.” in Proc. Homeyer.0 [1] J. T. high-power-factor boost converter with IGBTs. 1997.P. 1163-1169 vol.” in Proc.” in Proc. “Solid-state pulsed power systems for the Next Linear Collider.. July 2002. pp. Cook. on Power Electronics.” in Proc. R.

April 1999. pp. July 2004. Kempkes.” IEEE Trans. 2004. 2001. pp. Ives. System consideration.[13] W.A.. 1180-1196. 7. 10 . [18] R. “Compact solid-State switched pulsed power and its applications. “Design of a multistage depressed collector system for 1 MW CW gyrotrons. ED-27. Plasma Science. pp. [14] M. No. New York: Institute of Electrical and Electronics Engineers. [17] CPI Private Communication with Mr. Jiang. II. 92. vol. vol. of IVEC. 503-511.” Proceeding of the IEEE.L. 271-272 [15] R. High-Power Microwave Sources and Technologies. “Crowbar replacement through solid-state opening switches [VED applications]. Inc. [16] CPI Gyrotron Primer and Specifications Sheets. Barker. Parent and Dr. Felch.J.” in Proc.

The general design concept of switch-mode converters is the delivery of controlled and regulated power from an unregulated source [1]. consumer and military electronics. A high-level diagram of a DC-DC switch-mode converter is shown in Figure 2. and other applications where controlled and regulated power is necessary [2].1 Switch-Mode Converters The subject of switch-mode converters is a significant portion of power conditioning electronics. the input and output diagnostics feed data to the controller. computers. electric transportation drives. Switch-mode converters are designed to sustain a constant output and compensate variation from an unregulated power source. which are designed for DC input and conditioning of the DC output voltage. The focus of the following will be on DC-DC switch-mode converters. motor control systems.0 THEORETICAL CASCADE BOOST DESIGN 2.1. The switch-mode converter’s diagnostics and control loop are designed to give the necessary switching parameter compensation to maintain the regulated DC output. heating and cooling. These circuits are used in power processing systems integrated into power supplies.CHAPTER 2. 11 . Here.

The output of switch-mode converters can be adjusted by altering the duty ratio of the switch.Unregulated DC Switching Converter Regulated DC Load Controller Diagnostics Figure 2. A controllable switching parameter is the switching duty ratio. For instance. which is the ratio of on-time of the switching device(s) to the total time duration of the switching period as seen in equation [2. hence the name switch-mode converter. the buck converter topology creates a 12 . At steady state.1 General diagram of a generic DC-DC switch-mode converter. and ton is the time the switch is conducting. Switching period Ts [2. the converter control system will maintain an average energy transfer to the output by adjusting switching characteristics to account for unregulated input variation.1] where f is the frequency in Hertz. Certain DC-DC switch-mode converter topologies are specifically designed to step-up or step-down DC voltage. This control is called pulse width modulation (PWM). or switches. which in turn adjusts the average energy transfer through the converter. Switch-mode converters operate by repetitively transferring energy from the input source to the output load by controlled switching devices.1] below: D ≡ ton ton = = tonf .

the controllability of the PWM allows switch-mode converters to have real-time adjustable voltage ratios. such as the buck-boost and the Ćuk converter. or load. Also. regulated output is necessary. Thus stepping-up or stepping-down the voltage is analogous to a transformer’s winding ratio in AC signal applications. The output capacitor provides low-pass filtering. a switch.less-than-unity voltage gain—it is designed to step-down a DC voltage to a lesser DC voltage. 13 .2 The Boost Converter The basic boost converter is comprised of an inductor. A schematic of the boost converter is shown in Figure 2. Also. However. some topologies. where the average diode current is delivered to the load. 2. The PWM controlled output compensates from variation in the input source. through the diode. while delivering a steady DC voltage. switch-mode converters are implemented in applications where constant. DC output filtering is implemented in most converters for mitigation of the voltage ripple transferred to the output from the active switching.2. and a capacitor for output DC filtering of the load. For this reason. The converter stores magnetic energy in the inductor and then switches it to the output load. with every switching period. a diode. are designed to do both—increase or decrease the DC output voltage depending on the switching duty ratio. The boost converter has a greater-than-unity voltage gain—it is designed to step-up DC voltage.

The inductor current for DCM and CCM is shown in Figure 2. the filter capacitance can be designed to meet this specification. the circuit is in CCM. If the output maximum voltage ripple is specified to be ± 0.The average diode current through the load provides the output DC voltage. If the boost circuit inductor current does go to zero. and the switching frequency of the converter. A boost converter can be operated in two modes: continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The current waveform of the inductor indicates which conduction mode the converter is operating. it is in DCM. 14 . Figure 2. The amplitude of the AC voltage ripple is affected by the output capacitor.4. respectively. where the average voltage across the inductor is zero during the steady state operation of the circuit.5%.3 and Figure 2. the impedance of the load.2 Single Stage Boost Converter Deriving the gain equation for the boost converter is conditional on the converter’s operational mode. The voltage gain in DCM and CCM is derived from the principle of balanced inductor volt-second product. but there is a certain amount of AC voltage ripple coupled to the output. If the current in the inductor does not reach zero during the time when the switch is open.

During the fall time of the inductor current.Vo)(1 . Vs. iL IL T DT toff Figure 2. When the switch opens. across the inductor is equal to zero. the current remains greater than zero. When the switch is closed.iL Imax T DT ∆1T Figure 2. Vo. as described in equation [2.4 Continuous Inductor Current. The inductor voltage is negative during this interval (toff) and the inductor current will be transferred to the load. For CCM. T [2. through the diode. or output voltage.3 Discontinuous Inductor Current. the voltage across the inductor is equal to the supply voltage.2] below: VL= 1 [ VsDT + (Vs . the derivation of the voltage gain is as follows.D)T ] = 0 . The average voltage. where current increases linearly through the inductor and switch.2] 15 . the voltage across the inductor is equal to the supply voltage minus the clamped voltage across the capacitor. D is the switch duty ratio and ∆1 is the diode duty ratio or the fall time of the inductor current. VL.

during each period is zero as shown in the following: VL= 1 ⎡ VsDT+ ( Vs-Vo ) ∆1T ⎤ =0 .3. ∆1T. Vs ∆1 [2.5] 16 . T is the period. is also the diode forward conduction time. The time. the same procedure is followed as in CCM.3] A similar equation for DCM operation will also be derived. Solving for the ratio of output to input voltage. will result in the following step-up voltage gain equation for CCM is shown below: Vo 1 = Vs (1-D) . DT equals the time the switch on-time. using equation [2. The average voltage across the inductor. ⎦ T⎣ [2.where D is the duty ratio.5]: Vo (D+∆1) = . [2. and (1D)T equals the time the switch off-time. where ∆1 is the diode duty ratio.4] The voltage gain from equation [2. VL .4] yields the following relationship in equation [2. The inductor current is shown in Figure 2. where ∆1T is the duration during which the inductor current falls from Imax to zero. To determine the voltage gain in DCM.2].

The value of the interval ∆1, however, is dependent on the boost converter’s inductor, switching frequency, switch duty ratio, and the output load as seen in equation [2.6]:

⎛ Vo ⎞ ⎛ 2L ⎞ ∆1 = ⎜ ⎟ ⎜ ⎟. ⎝ Vs ⎠ ⎝ RDT ⎠


Inserting equation [2.6] into equation [2.5] yields equation [2.7] for the gain of a boost converter in DCM:

Vo 1 ⎛ 2D 2 RT ⎞ = ⎜ 1+ 1+ ⎟. Vs 2 ⎜ L ⎟ ⎝ ⎠


2.3 Discontinuous Mode

The cascade boost converter has been designed using DCM due to the necessary high voltage boost ratio and operation into a high impedance load. An important

advantage of DCM is that the boost converter can operate with a high step-up gain and allow for reduced inductor size. Figure 2.5 displays a voltage step-up gain comparison of a boost converter in DCM and in CCM. This shows a favorable linear relationship of the gain with the switch duty ratio. Table 2.1 shows the CCM and DCM voltage gain ratios, in relation to the minimum inductor value for operation in the CCM. The gain value for both modes is independent of converter voltage input, output, or power specifications. This shows that the inductor for CCM must be several times larger than the inductor used 17

in DCM for an equivalent step-up voltage gain. The inductor can consume a large portion of the converter volume and mass, where power density of the converter can be increased if the inductor size is minimized. Unlike CCM, voltage gain for the discontinuous mode does not exclusively depend on the switch duty ratio, D. Operating in DCM may have advantages over CCM under the condition of a high impedance load, where the average output current is small. For instance, in CCM, the duty ratio must be 90% of the switching period to achieve a voltage gain of ten. In DCM, this gain can be accomplished with a duty ratio of 60%, where ∆1 is 6.67% of the switching period. Operating at high duty ratios has

disadvantages, such as limited range for the control system to increase the duty ratio further in order to maintain a regulated output. Thus, the converter’s ability to maintain a constant output voltage is relatively limited in the CCM.


20 18 16 14 Voltage Ratio 12 10 8 6 4 2 0 0 0.2 0.4 0.6 Duty Ratio 0.8 1


Figure 2.5 Comparison of DCM to CCM (R=25 kΩ, f=10 kHz, L=3.3 mH)

Table 2.1 Comparison of voltage gain and inductor values over a range of duty ratios and voltage gain ratios. DCM inductor held at 3.3 mH; CCM Lmin adjusted to keep boost converter in CCM.
Duty Ratio CCM Gain CCM Lmin (mH) DCM Gain 0.1 1.11 1098 2.43 0.2 1.25 976 4.27 0.3 1.43 854 6.12 0.4 1.67 732 7.98 0.5 2.00 610 9.85 0.6 2.50 488 11.71 0.7 3.33 366 13.58 0.8 5.00 244 15.44 0.9 10.00 122 17.31 0.95 20.00 61 18.24 0.98 50.00 24.4 18.80

Another important aspect of the DCM is a reduction of the reverse recovery loss associated with typical power diodes in the boost circuits. The reverse recovery loss occurs during the transient when the diode switches from conducting current in the 19

since the reverse recovery current will contribute to the switch turn-on current level in the CCM. Figure 2. The reverse recovery current is formed as residual junction charge is transferred out of the diode. have developed Silicon Carbide (SiC) Schottky diodes with 1200 V and 10 A ratings. where higher dIf/dt generally results in higher peak reverse recovery current. Also. 20 . the rate at which the current falls from conducting to blocking influences the peak reverse recovery current. The amount of reverse recovery loss depends on the design of the diode. The reverse recovery current. multiplied by the rising reverse voltage. The high diode dif/dt in the CCM occurs as the diode turns to the off state.7 of DCM diode and inductor currents shows the inductor-limited dIf/dt diode current. Manufacturers typically list reverse recovery characteristics from a given current level and rate of current fall. Recent manufacturers such as Cree Inc.6 shows the diode current in the CCM. as it is a majority carrier device. Additionally. the reverse recovery current increases switch loss at turn-on.forward biased state to the reverse bias or off state. will result in power loss. that reduce reverse recovery loss dramatically. and the reverse recovery can become significant. these diodes can have voltage ratings nearly ten times that of Si Schottky diodes. and with SiC. where power diodes and high voltage diodes tend to recover more slowly than lower voltage rated high-speed diodes. The DCM reduces the peak reverse recovery current since the dIf/dt of the diode is equal to the dIL/dt of the inductor. Reduction of the reverse recovery loss can be lessened further by use of new diode technology. which can be orders of magnitude lower. The diagram in Figure 2. Schottky diodes have no minority carrier stored charge.

4 Cascade Boost Converter Design The following section details the principles and the derivation of the system equations used to determine component values under specified switching parameters. L2.7 The DCM diode and inductor currents 2. and load. The analysis will determine L1. i(t) Diode current Inductor current dID/dt = IL/dt Figure 2. voltage ripple.8 below is an idealized schematic of the two stage cascade boost converter.i(t) Diode current Inductor current ID(t) IL(t) 0 High dif/dt Figure 2.6 The CCM diode and inductor currents. High dif/dt occurring at diode turn-off. and C2 in an algebraic form. Figure 2. 21 . C1.

1 Voltage Gain and Inductor Derivation The cascade boost converter transfers energy through two series boost converter stages where the output voltage of the second stage is maintained across the load. a linear-rate rise in current is drawn through L1 from the DC input source. This voltage multiplication is achieved without use of a transformer. When both switches are open (time 22 .L1 D1 L2 D2 Vs S1 C1 S2 C2 RL Figure 2. Each stage operates just as any boost converter. DT or ton. During time. rather the stages are coupled together by a controlled average current flow through the stages. and L2 similarly draws current out of C1. except the first stage does not operate into a resistive load. RL. The energy transfer process during steady state operation is as follows.9.8 Simplified Cascade boost converter schematic. Thus. The resultant converter voltage gain is the product of the first stage voltage gain and second stage voltage gain. The effective load impedance for the first stage will change if the average current through L2 increases or decreases from the PWM controlled second stage. An example of the inductor current waveforms is illustrated in Figure 2. of the switches.4. 2. The first stage average output current is equal to the average input current of the second stage. the first stage switching duty ratio must be controlled to compensate for any changes in the average current drawn from the second stage.

during DT. must equal the charge flowing into C1 during ∆2T. This shows that changes in the average second stage inductor current will affect accumulative charge storage in C1 and thus first stage DC output voltage. charge flows into the capacitors DT T 23 . and simultaneously. to maintain a constant capacitor voltage. current flows through diode D2 to the output load. the average current of the capacitors is zero.9 Example of the current waveforms of L1 (red). L2 (blue). filtered by C2.9 is the current through C1. As mentioned above. the average rate of charge input equals the average rate of discharge. and C1 (black). Also shown in Figure 2. where the charge flowing out of C1. i(t) T L1 Current L2 Current C1 Current iL1 iL2 iC1 DT ∆1T ∆2T Figure 2. current through diode D1 flows through C1. and ∆1 and ∆2 are the duty ratios of the diodes and fall time of the inductor current.duration T-DT). and the voltage across them equalizes to a constant DC voltage. D is the switch duty ratio. Therefore the DT integral of current over one period is zero: ∫ 0 ic dt= ∫ ic dt . The calculation of the inductance values for inductors L1 and L2 is found by assuming the circuit is in the steady state mode.

asynchronous switching may be desirable and will be discussed in section 2.8]: ∆vc = ∆Q = C ∫i c dt C . The linear increase of the current through L2.5. where the duty ratio and period in the following derivation applies to both switches. [2. Therefore. ic1 dt = (DT) ⎜ DT ⎟ = 2 2L2 ⎝ L2 ⎠ [2. However. If the net current per period is zero.9] The negative change in the C1 voltage while the switches are closed.from 0 to DT and out of the capacitors from DT to T. For simplicity. the net change in voltage per period is also zero: -∆vc = +∆vc.9]: DT ∫ 0 2 1 ⎛ VC1 ⎞ -VC1(DT) .8] The following analysis will find the relationship of L1 and L2 using steady state voltage equalization of C1. where -∆vc1 = +∆vc1 per period. The governing equation of the capacitors’ voltage is shown below in equation [2. the integral of current flowing out of capacitor C1 and through inductor L2 is shown below in equation [2.9. while the switches are closed. has a slope of VC1/L2 for time duration of DT. is given by: 24 . then. The illustration of the inductor currents that will be discussed is shown in Figure 2. the analysis also assumes switches S1 and S2 are switching synchronously.

-∆vC1 = 1 C1 DT ∫ 0 iC1 dt= VC1(DT) 2 . The first stage voltage gain and second voltage gain are shown below in equations [2.14]: VC1 ( D+∆1) = . when the switches are open. charge is also being removed from C1 by iL2 during the time ∆2T. This is more complicated because while charge is being added to C1 by iL1.13] and [2.11] Setting –∆vC1 = +∆vC1 and solving for the average capacitor voltage. 2L2C1 [2.12] below: VC1= L2 ⎛ ∆1 ⎞ ⎜ ⎟ Vs . Vs ∆1 [2.12] Since the design of the cascaded boost converter’s voltage gain or “boost” in the first and second stages is calculated in DCM.10] Using the same process when the switches are open results in a slightly more complicated solution for +∆iC1 and +∆vC1. L1 ⎝ D+∆2 ⎠ [2.2 ∆2 L2 DT ⎟ . C1 DT ⎝ ⎠ T [2.13] 25 . the voltage gain of both stages is in the form of equation [2.5]. results in the equation [2. VC1. Integrating the current through C1. yields the positive change in voltage: +∆vC1= 1 1 ⎛1 Vd 1 VC1 ⎞ ∫ iC1 dt= C1 ⎜ 2 ∆1T L1 DT.

VC2 is the cascade boost output voltage. and the voltage gain for both stages. duty ratio. as shown in the following equation [2. and switching period with synchronous switching.14] respectively.15] After solving for L2. D.16]: ⎛ ∆1 ⎞ Vs L1 = L 2 ⎜ . L1 is found using equation [2. voltage gain per stage. Vo. 26 .12].15]: ⎛ VC1 ⎞ ⎛ RDT ⎞ L2 = ⎜ ⎟⎜ ⎟ ∆2 . ⎟ ⎝ D + ∆ 2 ⎠ VC1 [2. The values of ∆1 and ∆2 can be solved from [2. The derivation assumes ideal circuit parameters. the value of L2 is found by using equation [2. Such losses are analyzed in the cascade boost converter prototype and are explained in the chapters to follow. ⎝ VC 2 ⎠ ⎝ 2 ⎠ [2. where realistic circuit losses absorb energy which lowers the gain and the output voltage.VC2 Vo (D + ∆2) = = . VC1 VC1 ∆2 [2. Once ∆1 and ∆2 are known. given the duty ratio value.6] and ∆2 as in equation [2.14] where the second stage output voltage.13] and [2.16] This concludes the derivation of L1 and L2 given the output load resistance.

2. the capacitance values should not greatly exceed the value necessary for the specified voltage ripple. The voltage ripple is the ratio of the varying AC component to the average DC value. the capacitor C1 and C2 values must also be derived. For the capacitor C1.17]: ∆vC1 (∆Q/C ) = . where extraneous capacitance will consume extra volume and mass of the system.17] where VC1 represents the DC voltage value and ∆vC1 is the peak-to-peak magnitude of the voltage ripple.4. The values of these capacitors must fulfill the system requirements for voltage ripple regulation. For system volume and mass minimization.2 Filter Capacitors As a design parameter. and is commonly expressed in percentage. VC1 VC1 [2. the ratio of peak-to-peak AC voltage to DC voltage is calculated with equation [2. or the current flowing out of the capacitor when the switches are closed. 2 ⎝ L2 ⎠ [2. The charge transfer ratio ∆Q. The charge transfer ∆Q is: ∆Q = ∫ ∆iC1 dt = 1 ⎛ VC1 ⎞ (DT) ⎜ − DT ⎟ .18] 27 . is used in the calculation. to simplify the integration.

20] below is the voltage ripple across C2 and RL: ∆vC2 L2Io ⎞ ⎛ VC1 −1 ⎡ ⎛ ⎞⎤ DT − Io ⎟ ⎥ . as given in equation [2.19]: ∆vC1 (DT) 2 = .20] where VC2 is the DC output voltage and ∆vC2 is the peak-to-peak AC voltage. C2. = ( 2C2VC2 ) ⎢⎜ ∆2T − ⎟⎜ VC2 Vo − VC1 ⎠ ⎝ L2 ⎠⎦ ⎣⎝ [2. The equations [2. is more complicated. Equation [2. with the voltage ripple solved in terms of design parameters.22] below derive the values of capacitors C1 and C2 in terms of the voltage ripple across C1 and C2.The results from equation [2. Therefore. Vo/RL. respectively: C1 = (DT) 2 .18] can be used to calculate the ripple in capacitor C1. the capacitance values can be found. flowing through the diode. VC1 2C1L2 [2. ∆vC1 2 L2 VC1 28 [2.21] and [2.19] The voltage ripple for the output capacitor. but the procedure is similar. where the average diode current is equal to the DC output current.21] . The change in the capacitor charge is found by integrating the amplitude of current above the average current. Io.

given that the capacitance of C1 will satisfy the specified voltage ripple regulation requirement. The primary concern is to control the steady state current and the subsequent DC voltage across C1 and C2. The average power loss in the switches is proportional to the switching frequency from the energy lost per transition.15] and [2. The inductance values are solved as they are solved in equations [2. while operating within the specified power loss.5 Asymmetrical Switching Switching loss is a crucial parameter for consideration in the design of the cascade boost converter.22] 2. For instance. and both stages can have independent switching frequencies.L2Io ⎞ ⎛ VC1 −1 ⎡ ⎛ ⎞⎤ C2 = ( 2∆vC2 ) ⎢⎜ ∆2T − DT − Io ⎟ ⎥ .16]. One method for independent switching design is to first approach the circuit as a symmetrically switching circuit. Because the inductor values are inversely proportional to the 29 . asymmetrical switching allows the first stage to be operated at a higher switching frequency independently of the second stage to take advantage of typically faster. can optimize the inductor and capacitor values for improved system power density. Asymmetrical switching of the first and second stages is not difficult to achieve. Capacitor C1 will then couple both stages with a steady DC voltage. Maximizing the switching frequency per stage. ⎟⎜ Vo − VC1 ⎠ ⎝ L2 ⎠⎦ ⎣⎝ [2. lower voltage rated switches of the first stage.

switching frequency.23] shows that if D1T1 is reduced by one tenth. 30 . The reduced inductor value creates a proportionally steeper inductor current slope. L1 must be reduced by the same factor as seen in equation [2. Therefore. maximum switching frequency for each stage can be accomplished. and the average current flowing into C1 from the first stage will remain as in the symmetrical switching case since the time interval. the average current flowing into C1.23] The preceding discussion and relation of the inductance to the switching frequency per stage allows for the asymmetrical switching between stages.23] below: Vs ⎛ 1 ⎞⎛ 1 ⎞ 1 Vs IC1 = ⎜ ⎟ ⎜ ∆1T1 D1T1 ⎟ = ∆1 D1T1 . IC1 . the inductance values can initially be solved using a symmetrical switching design with the first stage inductor L1 scaled to one tenth of the initial value. Maximized switching frequency results in minimized inductor values and reduced inductor volume and mass. L1 ⎝ T1 ⎠ ⎝ 2 ⎠ 2 L1 [2. the inductors are scaled proportionally with a change in the switching frequency in each stage. With the ability to operate the stages independently. if the first stage is to be operated with a ten times higher switching frequency than the second stage. For instance. when the switch is closed would change in proportion to the change in frequency. in equation [2. D1T1.

the second stage switching frequency is limited to half of the first stage switching frequency due to higher anticipated switch loss. the values of L1. These values are given below and were applied to equations [2. 31 . L2. A judgment was made for the step-up ratios and switching frequencies of the first and second stage. and constant output voltage.13] through [2. Also. The cascade boost efficiency must operate at 70% or higher. the capacitance value of C1 was determined empirically by sweeping the capacitance to attain the specified voltage ripple in the first stage output. Due to asymmetrical switching. based on the load impedances per stage and the limiting peak inductor currents to limit power loss and magnetic field radiation.10. since heat removal can become a significant issue for high power converters.6 Initial Design Values and Simulation Results of an Idealized Model The inductor and capacitor values in the cascade boost converter are determined from the equations in Chapter 2. certain values must be specified. In order to use the equations in Chapter 2. as discussed in section 2. The circuit model was created and simulated using Orcad Pspice. and C2 were determined on the basis of constant input voltage. it has been assumed that a converter operating at less than 70% efficiency will be unacceptable for the end user. The asymmetrical switching frequencies of the first and second stages were accounted for. The circuit simulation results verify the circuit equations which were used to derive the circuit component values. Also. C 1. These values were used to simulate an idealized circuit model of the cascade boost converter with an output of 5 kV and 1 kW.2. constant gain.5.5% voltage ripple. The circuit model and the associated circuit element values are shown in Figure 2. Also the output regulation has been simulated for a ±0.16].

The following values were used as an initial parameter space to begin circuit modeling of the converter. In the actual prototype cascade boost converter, the parameters were modified, which will be discussed in Chapter 5. 1st stage gain = 5 2nd stage gain = 10 1st stage switching frequency = 20 kHz 2nd stage switching frequency = 10 kHz (limited due to switch loss) Duty ratio of both stages = 0.5 Load resistance = 25 kΩ ± 0.5% or less Voltage ripple on C1 and C2 Efficiency = 70% or higher (specification for experimental circuit only) The circuit values derived from equations [2.13] through [2.16]: ∆1 = 0.125; ∆2 = .055 L2 = 3.4375 mH (rounded down to 3.4 mH) L1 = 76.6 µH C1 = 28 µF C2 = 0.383 µF(rounded up to 0.4 µF)


L1 76.6uH

R1 .0001


L2 3.4mH

R2 .0001


S1 Vs 100v V1 = 0 V2 = 1 TD = TR = 1n TF = 1n PW = 25us PER = 50us Vg1
+ +

C1 28u V1 = 0 V2 = 1 TD = 0 TR = 1n TF = 1n PW = 50us PER = 100us Vg2

+ +



C2 0.4u

RL 25000

S VOFF = 0.0V VON = 1.0V R3 .001

S VOFF = 0.0V VON = 1.0V


Figure 2.10 Idealized Pspice circuit model using derived component values. Resistors R1, R2, R3 were inserted into the model to avoid convergence problems.

The non-idealities existing in the model are negligibly small and do not affect the converter output. The switches in the model are ideal, but incorporate 1 mΩ impedances during the on-state. The resistance values of R1 and R2 were added as resistance for simulation convergence, and the diodes have an internal forward voltage of 0.7-1.0 V. The total power loss from the non-idealities is approximately 2 W, leading to a model efficiency of 99.8%. These low losses can be neglected in the model with the efficiency nearly ideal. The output voltage waveform generated by Pspice, in Figure 2.11, shows an average DC voltage of about 5.07 kV with a voltage ripple of less than ± 0.5%. The output is greater than 5 kV since L2 was rounded down to 3.4 mH from 3.4375 mH, which slightly increases the peak inductor current and average charge transfer into C1. The observed peak-to-peak magnitude of the ripple is 47.7 V, which correlates to a 0.94% peak-to-peak voltage ripple result. The ± 0.5% voltage ripple, specified above, is


fulfilled with a 0.4 µF capacitance for C2, which was rounded up from the calculated value of 0.38 µF. Figure 2.12 shows the voltage across capacitor C1 and the current through L1. The peak-to-peak voltage ripple across C1 is calculated to be about 0.94% with a capacitance of 28 µF. The voltage ripple meets the specification of ± 0.5% or less. Figure 2.13 shows the voltage across capacitor C2 and the current through L2. The current waveforms through L1 and L2 show the ∆1 and ∆2 duty ratio values of approximately 0.125 and .055 respectively, which are in agreement with the calculated values found with equations [2.13] and [2.14]. The current waveforms also indicate the current peak as 33 A in L1 and 7.5 A in L2. Since the peak inductor current corresponds to the current level which the switches must turn off, these current waveforms can be used to select the solid state switches, estimate the switch loss and heat sink size, and design the inductors for the experimental circuit.
Output Voltage 5.14 Output Voltage ( kV ) 5.12 5.1 5.08 5.06 5.04 5.02 5 0 100 200 300 400 500 Time ( µs )
Figure 2.11 Simulated output voltage of the second stage/converter. ∆V = 47.7 V, which correlates to a voltage ripple of less than ± 0.5%.

∆V = 47.7 V


08 5.04 0 25 50 75 100 125 8 7 6 5 4 3 2 1 0 -1 C2 Voltage ( kV ) Time ( µs ) Figure 2.06 5.12 Simulated voltage across C1 and current through L1.13 Simulated current through L2 with the second stage output voltage across C2. The simulation of the idealized circuit model verifies the derived equations of Chapter 2.07 5.1 5. 5.09 C2 Voltage and L2 Current 5.510 C1Voltage and L1Current 35 30 25 20 15 10 5 0 -5 C1 Votlage ( V ) 500 495 490 0 25 50 Time ( µs ) 75 100 125 Figure 2. Losses in a practical circuit model will affect the cascade boost converter 35 L2 Current ( A ) L1 Current ( A ) 505 .05 5.

Increasing the duty ratio. and show the interaction of the circuit component values. where increasing the duty ratio of both stages is necessary to overcome such losses. 36 . however. the idealized circuit model results demonstrate the circuit equations in Chapter 2. incurs higher peak inductor current.voltage gain. However. The losses to consider in the cascade boost converter appear to be a result of the switching loss and the inductor loss. Other losses include diode loss. and thus. higher current switch current and resistance loss. and series resistive loss in the capacitors and inductors.

Mohan. Undeland.REFERENCES FOR CHAPTER 2. Hart. 1997. T. 2nd Edition.M. 37 . New York: John Wiley & Sons.0 [1] [2] N. D. Power Electronics. Upper Saddle River. W. Introduction to Power Electronics. 1995.W. NJ: Prentice Hall.P. Robbins.


The cascade boost converter prototype has been designed and built to satisfy a DC output of 5 kV, into a 25 kΩ load, from a 100 V DC source using cascaded boost circuits, and maintain a +/- 0.5% output voltage ripple regulation. The design goals are

summarized in Table 3.1. This system has been designed with commercial off-the-shelf (COTS) components, and is a bench top system for the analysis of circuit parameters such as switch, diode, and inductor loss. A photograph of the bench top prototype converter is shown in Figure 3.1. Switch theory and design involved in the cascade boost converter is discussed in this chapter, where the voltage requirements for the second stage switch, diode, output capacitance, and inductor must be designed to the converter’s output voltage of 5 kV. This requires COTS switches, diodes, and capacitors to be arranged in series, and requires adequate high voltage insulation within the second stage inductor. The implementation of leading inductor core technology, and stacked series device designs for the second stage, also facilitates scaling to higher power levels for future designs. Fortunately, the first stage output of 500 V allows for conventional use of widely available commercial components in this voltage range. This chapter describes the cascade boost converter circuit design and experimental setup, and highlights the switching theory used in the design of the second stage switch.


Table 3.1 Cascade boost converter prototype design goals.

Voltage Input Voltage Output Power Output Output Voltage Regulation

100 V 5 kV 1 kW

+/- 0.5%

Figure 3.1 Bench top cascade boost converter prototype.

3.1 IGBT Switching Design Theory

The Insulated Gate Bipolar Transistor is a hybrid of a bipolar-junction transistor (BJT) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and has accrued success has a high power solid state switching device for its fast switching, low conduction loss, and high impedance control requirement. These qualities are favorable for the cascade boost converter and applications such as SMPS, power converters, and


motor control. The implementation of IGBTs in the cascade boost converter will be discussed in sections 3.2-4, where the first and second stage components will be covered. The equivalent circuit of an IGBT is shown in Figure 3.2. The terminology for the IGBT terminals is the following: the collector is the anode, the emitter is the cathode, and the gate is the control terminal. The IGBT can be modeled as a MOSFET controlled BJT, where the MOSFET front end forms the high-impedance gate input. Similar to the MOSFET, the applied voltage from gate to emitter above the threshold level turns the device on, and a voltage below this threshold voltage turns the device off. The low onstate collector to emitter resistance is inherent to the conducting properties of the BJT portion of the IGBT. The IGBT, in effect, has favorable qualities of both the MOSFET and BJT. However, IGBTs with ratings greater than 1 kV are commonly used in

applications of 100 kHz or less, since switching loss tends be too great at higher frequencies. The MOSFET, with a faster switching speed but higher on-state resistance, are ideal for low power switching at frequencies in the kilohertz to megahertz range. As a compromise between the MOSFET and the BJT, the IGBT was selected as the switch of choice. The frequency limitation of the IGBT switches can be linked to input and output mechanisms of switching losses due to the MOSFET and BJT, respectively. In the cascade boost converter application, the turn-off operation is of primary concern as the switches turn-on with zero current conduction and turn-off current at the peak inductor current. Two significant factors that affect the turn-off switching time and turn-off energy loss of IGBTs will be the focus in the following theoretical IGBT switching 40

Cres (Coes= Cce+ Cres). tf1 [1]. The capacitances of the equivalent circuit are shown in Figure 3. Cce. 3. along with the drift region resistance. Rdrift.2.1 IGBT Capacitance The switch capacitances commonly noted on IGBT data sheets include the input capacitance.3.1. which will be discussed in section 3. The MOSFET portion governs the first three time intervals of the turn off transient: the turn-off delay time. and thus contributes to the loss in the IGBT [1]. and capacitance versus Vce curves also are typically provided on data sheets. These capacitance values vary with Vce. These factors included the internal IGBT capacitance of the MOSFET structure and the slowly decaying current “tail” during turn off due to the BJT portion. tvr. the reverse transfer capacitance (Miller capacitance). and the first interval of current during turn-off.discussion. Cies. td(off). The output capacitance may affect the output circuit and is equal to the collector to emitter capacitance. which is made up of Cres plus the gate to emitter capacitance. the voltage rise time. Coes. 41 .1. The input capacitance may affect the gate drive requirement. and the output capacitance. The charge stored in the input capacitance is the only charge that is to be transferred during switching of the MOSFET. Cge (Cies= Cres+ Cge). plus the Miller capacitance. The turn-off transition waveforms are illustrated in Figure 3. Cres.2.

where RG is the total resistance of the drive circuit. which is stored in the Cies.Collector Rdrift pnp BJT Ccg Gate Cge Emitter MOSFET Cce Cies= Cres+ Cge Coes= Cce+ Cres Cres=Ccg Figure 3. The gate drive circuit has a significant effect on the switching behavior of IGBTs [2-4]. For example. In general. ic(t) MOSFET tf2 vce(t) 0 BJT t td(off) vge(t) 0 tvr tf1 vth t Figure 3. and Cies is the IGBT input capacitance. and drift region resistance. This is because the gate drive circuit is similar to a capacitor charging/discharging circuit.2 The IGBT equivalent circuit including. switch capacitance. internal MOSFET and BJT.3 The IGBT turn-off waveforms in a clamped inductive load. will shorten the MOSFET switching time and lower switching energy loss [5]. td(off): dealy time. Rdrift. tf2: 2nd current fall-time. tf1: 1st current fall-time. increasing the rate at which charge is extracted from the gate. The total input 42 . tvr: voltage risetime. the gate driver voltage charges or discharges the IGBT input capacitance with a time constant ofτ RC = RGCies .

which may result in overshoot of Vce during turn-off from high -dic/dt and lead to increased power loss or even device failure. Latch-up occurs when the pnpn regenerative action results from the parasitic thyristor within the IGBT doping structure. Furthermore. as the rate at which the capacitance is charged and discharged is increased. the gate resistor must be made large enough to prevent IGBT latchup from high collector to emitter voltage time-rate of change (dvce/dt). Consequently.capacitance is fixed internal to the IGBT. can cause damage to the IGBT. Also. resulting in spontaneous turn-on. Using small external gate resistance reduces the time constant and increases the peaks of the gate current pulses. controlling the switch rate with the gate impedance reduces the effects of stray circuit inductance in series with the IGBT collector. The magnitude of current and voltage. due of the faster switching of the MOSFET portion. However. along with high dvce/dt and dic/dt rates. With paralleled devices that have varying lengths of gate connection. the gate resistance lowers the effect of asymmetrical gate lead inductances that may cause triggering delay and asymmetrical current sharing among the devices [6]. For instance. the external resistor will dampen the ringing from the inductance in the gate circuit that may cause the gate voltage to ring above the threshold voltage. faster turn-on and turnoff of the IGBT will result. a minimum gate impedance must be considered in relation to the IGBT application. Switching stress on the device affects reliability and lifetime. and to provide noise immunity in the gate circuit [1]. The main consideration is that the minimum gate resistance must be designed based on the trade-off of mitigating switching energy loss 43 . and the gate can no longer control the device to turn-off. and the external gate resistor is used to control the gate charging and discharge rate.

device reliability and lifetime during switching may be trade-off factors to fast switching. The IGBT modules with current ratings of approximately 100A or greater use several IGBT chips in parallel to share current. Utilizing the device datasheet information for input capacitance information. the gate driver must be designed for the IGBT input capacitance to meet the design specifications for switching speed and power loss. Such a gate driver must have low resistance output drivers and low stray inductance in order to compensate for high capacitance. When chips are paralleled.1. where fast turn-off is important to limit turn-off loss. The input capacitance is an important parameter to consider for high current.and the factors of insidious transient effects that can reduce the IGBT reliability and lifetime.3. capacitance along with the corresponding stray inductance from gate wire bonds limits the IGBTs gate drive bandwidth [6]. is the decay of 44 . or the fourth and final time interval in Figure 3. switching applications. The gate drive requirements for a specific device’s input capacitance must be met. This creates a large equivalent input The input capacitance of the module to charge and discharge during switching. 3. the input capacitance increases proportional to number of dies in parallel. However under certain applications. and the charging/discharging rate of the capacitance must be considered for mitigation of switching loss.2 The Turn-off Transient of IGBTs The portion of the turn-off switching transition following the charge extraction of the input capacitance.

increasing the voltage ratings of NPT type IGBTs can increase the turn-off transition time [7]. where the p+ body and p+ collector are highly concentrated ptyped doped regions. The depletion region of the NPT IGBT. Epeak. Therefore synchronously switching multiple low voltage rated IGBTs in series can lead to faster switching compared to a single high voltage rated IGBT.4 shows the cross-section of a Non-Punch Through (NPT) type IGBT. n-type drift region. However. A reverse biased junction of J2 is shown in Figure 3.drift region. does not extend past or “punch through” the n. Figure 3. Conversely.5. developed by a reverse voltage in the off-state. The BJT portion is a pnp type transistor made of the p-type collector. occurs at this junction. can be modeled as an abrupt p+n. and has been commonly termed the current “tail”. and the drift region is a lower concentrated n-type doped region. with the design of the second stage switch. This time interval exhibits an exponential-like current decay. as will be shown in this section. The NPT is a common type of IGBT for high voltage ratings due to excellent thermal properties such as negative temperature coefficient of resistivity and high thermal reliability [6]. and the 45 . The current tail is a result of the Bipolar Junction Transistor (BJT) portion of the IGBT’s turnoff process. n-type buffer layer adjacent to the p+ collector and allows the depletion region to extend through the n.drift region and stop in the n-type buffer layer. which is exemplified later in section 3. the Punch Through (PT) type IGBT implements a thin. J2. and the p-type body. the p-n junction.the collector current before the IGBT completely turns off. highly concentrated.4. The peak electric field.junction of a reverse biased NPT PiN diode [1]. When the NPT IGBT is reversed biased.

1] where NB is the background doping concentration of a semiconductor device.1]: dE ( x) NB =q . by definition. ND. ldrift. due to a relatively low donor doping concentration. at breakdown (depletion width is maximum). The electric field slope is much steeper in the higher doping concentration region. In the IGBT. is equal to the depletion region width. ε 0ε s dx [3.field is zero at the depletion width edges. and εs is the relative permittivity of the semiconductor. ε0 is the electric permittivity of free space. based on equation [3. the NPT type IGBT depletion region width never exceeds the drift region without device breakdown. and will therefore not penetrate as far into the p+ body. the minimum drift region size. Wd. Also. The electric field slope depends upon the background semiconductor doping concentration as shown in equation [3.1]. Therefore. electric field expands over the drift region primarily. 46 . compared to the p+ body acceptor doping concentration. NA.

dE(x)/dx xn Therefore. when the IGBT is fully on. The x axis is the distance along the pnp layers. the drift region thickness ldrift and NB are designed to hold off a specified reverse voltage.Gate Contact Emitter Contact n+ p + body n+ J2 J n drift region 1 p + collector - Gate Oxide Collector Contact Figure 3.5 PNP transistor layers in the IGBT: Epeak occurs at the junction J2. However. J2 Wd J1 p+ body n. the resistance of the drift 47 .4 Cross-section of the NPT IGBT.drift region due to high doping concentration of the p+ body region. and the depletion region width. extends primarily into the n.drift region ldrift p+ collector x xp E(0)=Epea E(x) Figure 3. where the zero occurs at junction J2. Wd.

the drift region thickness and doping concentration must be designed to handle the depletion region width at the device’s specified maximum voltage 48 . As discussed earlier. and must recombine for the IGBT to fully turn off. a condition of high level injection exists. the presence of free electrons is equally high.region becomes a component of the total on-state power loss. When excess charge carrier concentration exceeds the background doping concentration of a region by several orders of magnitude. and the minority carrier injection of holes into the drift region halts.2. Due to the space-charge neutrality condition. which decays at a rate that depends on the carrier lifetime [6]. is shown in the equivalent IGBT circuit in Figure 3. and the voltage rating of the IGBT. creating a plasma-like region of free charge effectively distributed evenly within the drift region. on the current tail can be shown using general equations found in semiconductor device theory. which allows for low forward on-state voltage at high current density levels. The resistance of the drift region is mitigated as minority carriers are injected from the p+ collector due to the forward biased junction J1. After the BJT base current is cutoff and J1 is no longer forward biased. This minority carrier conductivity modulation mechanism is used in devices such as BJTs and thyristors. The diffusion current density of injected free electrons and holes significantly affect the drift region conductivity. When the MOSFET portion turns off. the base current into the pnp BJT is stopped. where Rdrift. The recombination of the carriers within the drift region drives the current tail at turn-off. The effect of the drift region thickness. the excess carriers that have been injected from the p+ collector remain stored in the drift region.

Epeak. By space-charge neutrality. qNAxp = −qNDxn . the depletion width Wd in the drift region can be expressed solely in terms of the donor concentration.4] below: Wd ≈ xn = ε 0ε sEpeak qND . the peak electric field is given by Epeak = qNAxp ε 0ε s =− qNDxn ε 0ε s . Using the peak electric field.2] where xp is the distance of the depletion region in the p-body. at J2 the depletion region penetration into the p-body and the drift region can be found.3] Since the doping concentration of the acceptor doped p-body side is much greater than the n-type drift region in the IGBT.1] and [3. Using Guass’s law and integrating the charge within the electric field. as shown in Figure 3. ND. Wd. from equation [3. by equations [3. [3. is the sum of xp and xn. and again the electric field ramps linearly from the edge of the depletion region to the peak field.4] 49 . xn is the distance into the drift region. the distribution of the depletion region can again be simplified as only reaching into the drift region.3]. Therefore. Epeak. and εs is the relative permittivity of silicon. The depletion region width.application. [3.5. [3.2]. as shown in equation [3. the charge from both sides of a p-n junction must be equal where.

and the breakdown process occurs when the field becomes high enough to start impact ionization in the depletion region from high kinetic energy carriers accelerated in the field. and the depletion region will be at the boundary of the drift region and the p+ collector. In silicon. When the applied voltage is at the breakdown voltage. the depletion width equal to the width. [3. The 50 . The current flowing through the device. Vbr.6] below: Φ0 = kT ⎛ NAND ⎞ ln ⎜ ⎟. The voltage. results in high power dissipation and device failure.When the maximum voltage is applied across the reverse-biased junction. Wd br . it has been assumed that the applied voltage at breakdown is much greater than the contact potential.6] where ni is the intrinsic carrier density of the semiconductor. Vbr. when the breakdown will occur is found by integrating the electric field distribution over the depletion region width: 1 ε 0ε sEbr 2 Vbr = WdEbr = 2 2qND . Ebr. Ebr = 3x105 V/cm. Epeak will be equal to the breakdown electric field. as expressed in equation [3. of the semiconductor material. q ⎝ ni 2 ⎠ [3. Φ0. which establishes the process of avalanche breakdown [8]. after the avalanche process has been initiated.5] Also.

7]. During the fully on-state. and where n and p are the free charge carrier levels of electrons and holes. The high level injection case requires the concentration profile length of injected holes.thickness of the drift region. ρdrift. This relation is shown in equation [3. called the hole diffusion 51 . The resistivity of the drift region. At the high level injection condition. [3.8] where µn and µp are the electron and hole mobilities. respectively.5] and [3. ldrift. It is evident that high voltage rated. and at high level injection. the drift region charge carrier profile and junction J1 can be modeled as a forward biased PiN diode [9].8]: ρ drift = 1 . must be equal to or greater than the depletion region width at breakdown ( Wd br ): ldrift ≥ Wd br = ε 0ε sEbr qND . q ( nµ n + p µ p ) [3. NPT IGBTs require thick drift regions and/or increased n-type doping concentration. Wd br is directly proportional to the reverse breakdown voltage of the device. the resistivity is reduced greatly when a high level of excess hole charge carriers are injected from the p+ collector into the drift region.7] By equations [3. is inversely proportional to the quantity of free charge carriers.

the excess carrier concentration must fall to zero since it is reversed biased. the distribution of holes in the preceding discussion deviates from the PiN diode model with the p-n. [3.9] as LHL = Daτ HL > ldrift . the distribution in the IGBT drift region does 52 . In other words.9] where Da is the ambipolar diffusion coefficient and τHL is the hole lifetime during high level injection. to be longer than the thickness of the drift region [1].length. is given in equation [3. which shortens the lifetime compared to the low level injection lifetime [1]. The hole diffusion length is stated as the average distance a hole will diffuse from the junction before it is recombined [8]. accounting for carrier-carrier scattering. which lowers the mobility compared to the low level injection mobility [1]. and µHL is the hole mobility at high level injection. at the p+ body is involved.junction. The value of LHL is the average length of time a hole will diffuse before recombining with the Auger recombination effects. However. J2. where it begins to fall towards the junction [10]. LHL. The diffusion length for holes during high level injection.10]: Da = µ HLVT . The carrier profile is similar to the PiN diode profile until about midway through the drift region. At this junction. Lp. [3. The ambipolar diffusion coefficient is defined in equation [3.10] where VT is the thermal voltage. which changes the boundary conditions and the distribution.

The boundary conditions of the hole distribution.12]: pn( x) = ∆pn sinh{(ldrift − x) / LHL} . pn(x).12] where ∆pn is found by applying boundary conditions for the current densities for electrons and holes: Jn(x=0) = 0. At steady state. where the J1 and J2 are shown in Figure 3. The solution of ∆pn . 2 ∂x LHL2 [3. derived with these boundary conditions. sinh(ldrift / LHL ) [3.11] and solving the second-order differential equation.4 [10]. the continuity equation for holes is shown below in terms of the hole diffusion length and hole concentration is the following: ∂ 2 pn pn − = 0 [6].not have a high level charge injection across the entire width as the PiN diode does. However. down to the excess concentration at junction of J2. the derived final solution for pn(x). are the following: pn(x=0) = ∆pn and pn(x=d) = 0.11] Applying the aforementioned boundary conditions to equation [3. is shown in equation [3. is expressed in equation [3. where x is zero at J1 and d is the distance to J1 from J2.13]: 53 . the distribution of excess hole concentration can be solved by applying the continuity equation for holes with recombination effects. and Jp(x=0) = J [6]. A simplified distribution of holes without recombination effects appears linear from the excess concentration at junction J1.

resulting in more stored charge existing in the drift region to maintain a low resistance drift region. When the IGBT begins to turn off. recombine at the rate depending on the carrier lifetime during high level injection. iCtail (t ) . The spreading depletion region from J2 will extend into the drift region and sweep out some carriers. the current density. the excess carriers near J1 will only be removed by the process of recombination. and τHL is the high level 54 . It is clear that if the drift region is made to be larger. and also the thickness of the drift region. is exponential as shown in the following: iCtail (t ) = QB (0) τ HL e ( −t βτ ) . β is the pnp transistor current gain. the collector decay current.∆pn = JLHL ⎛ d ⎞ tanh ⎜ ⎟ [6]. the injection of holes must be made deeper. The effect of sweep out does not exist from J1. If the beginning of the current tail initiates at t = 0. or pnp transistor base. 2qDp ⎝ LHL ⎠ [3. where the growing depletion region removes charge carriers in the electric field—the depletion region spreads from J2.13] The principle result reveals that the distribution of the injected holes into the drift region is related to the diffusion length. but the remaining charge carriers that are not swept out.14] where QB (0) is the stored charge in the drift region. HL [3. at the beginning of the tail.

which increases on-state loss. Reducing the lifetime can expedite the collector current during the tail time according to equation [3. These technologies are employed in recent 6. The carrier lifetime is sensitive to temperature where increased thermal energy in the IGBT can cause current tail elongation [10].14]. such as the Fast Stop or Soft/Light Punch Through technologies. electron irradiation. IGBT modules. These designs use advanced doping profiles. designed for rugged industrial and commercial applications. and have shown reduced losses compared to similar rated NPT designs [11]. especially concerning the current tail loss [12]. and localized proton implantation are used to speed up the recombination process [10]. new trench-gate IGBT designs have been shown to lower on-state voltage compared to planar DMOS gate structures by reducing the on-state resistance in the MOSFET portion [13]. which add a thin n-type doped buffer layer adjacent to the heavily doped p+ collector terminal (next to J1).5 kV rated and high speed COTS.injection lifetime [6]. However. reducing the carrier lifetime has trade-offs such as lower charge carrier injection levels and possibly increased resistivity in the drift region. Also. Lifetime reduction techniques such as gold doping. This buffer layer provides a desired low forward on-state voltage during conduction and allows for a thinner drift region and faster recombination of carriers to mitigate switching loss. The latest generation of high voltage IGBTs. 55 .

The gate drive circuit must be designed for fast discharge of the IGBT’s input capacitance for mitigated switching time.3. and parallel. Additionally. Since the total turn-off time will generally increase as the voltage rating increases.1. the external gate drive resistor can be adjusted to customize the IGBT switching rate if necessary. complexity. high voltage switching can be accomplished with a stack of multiple lower voltage rated IGBTs in series [14]. is determined by the break-even point where reliability. is typically designed with a certain thickness and doping concentration for the IGBT’s off-state voltage rating. The maximum number of switches in series. the turn-off transition of high voltage IGBTs is relatively slow due to prolonged carrier recombination in the drift region. Furthermore. where the gate drive impedance can limit the response of the MOSFET turn-off. Consideration of the device voltage rating must be taken into account concerning turn-off loss.3 IGBT Switching Theory Conclusion The IGBT switching frequency is partially limited by input capacitance. The drift region. and cost meet the benefit of lowering switching loss relative to using singledevice IGBTs. especially in harsh environments [14]. also the base of the pnp transistor. IGBTs with high voltage ratings can affect system performance such as efficiency and switching frequency in switch-mode converters. Isolated gate drivers for each IGBT are required in such an assembly. As an alternative to high voltage IGBTs. by adjustment of the gate drive circuit’s capacitive time constant. 56 . and synchronized switching and equal voltage sharing must be ensured for reliable IGBT stack operation.

24 Ω International Rectifier IGBTs 0.24 Ω 400V TVS 400V TVS 237 µF Power Ten P83C-30033 Power Supply Powerex gate driver & DC-DC converter 18V TVS HP 8012B Pulse Generator 12. 60 A rated.3. and two series capacitors for the DC filtering capacitors between stages. The gate drive delivers a bipolar signal of +15.8 V and 8. The DC-DC converter draws power from a 12-18 V input. Non-Punch Through (NPT). IGBTs. each in a TO-247AD package.6 Schematic of first stage components The IGBTs used for the first stage are International Rectifier IRGP30B120KD-E 1200 V.4 µH Cree SiC diodes 237 µF Rg ~21 Ω 0.2 V. two diodes in parallel. four inductors in series. These IGBTs. switched in parallel.2 First Stage Detail The first stage of the cascade boost converter experimental setup consists of two Insulated Gate Bipolar Transistors (IGBTs) switched in parallel. which is provided by 57 .5 V Power Supply Nippon Chemi-con (2 series capacitors) Figure 3. Caddell-Burns Inductors (4 series inductors) 85. are driven by a single Powerex M57962L gate driver which is powered by a single Powerex M57145L-01 DC-DC converter designed specifically for the M57962L.

7. in length to give a total surface area of 113 in2 per heat sink. The IGBT loss was determined to be approximately 40-50 W when implemented in the final cascade boost converter prototype. 8012B pulse generator.5 ºC/W. The heat sink air flow is provided by a 24 V fan that provides about 200 CFM. The combined volume is 40 in3 for the heat sinks. including separation between heat sinks and brackets for mounting. shown in Figure 3. The power supply delivering the input power is a Power Ten.an 18 W. The resistive load was used to simulate the average current draw of the second stage.5 V power supply plugged into the 120V AC laboratory power. P83C-30033 power supply that is rated at 10 kW with a 300 V maximum output voltage. The first stage switching loss was determined based upon initial IGBT testing using the circuit shown in Figure 3.3.6. In order to limit the operating temperature below the rated 125º C junction temperature. The thermal resistance for each heat sink is estimated to be less than 0. 12. is given in Table 3. The gate drive input signal source is controlled by a Hewlett Packard. The gate resistance for both IGBTs is controlled by a single potentiometer set nominally at 21Ω. The test converter produced 550 VDC and the turn-off current level of each IGBT was 25 A. The development of the first stage involved determination of switching loss for the IGBT cooling requirements. The total volume consumed by both heat sinks in the prototype setup. 58 . The heat sinks are E3045 profiles by Thermaflo. where each heat sink was cut to 5 in. Inc. but operating as a single stage converter into a 249 Ω resistive load. each IGBT was clamped to a forced air cooled aluminum heat sink.

The power loss of Schottky diodes is almost exclusively due to the onstate conduction loss. Two of these inductors are rated at 15 µH and two are rated at 22 µH. These diodes represent an emerging power semiconductor technology using SiC. higher operating temperatures. The SiC higher electric field strength enables the production of Schottky type diodes with a 1200 V rating. The diodes shown in the schematic in Figure 3. The measured inductance showed that the actual inductance of the four inductors in series is 59 . where Si Schottky diodes are rarely rated above 200 V. which includes a number of advantages over silicon. is a series arrangement of four inductors by CaddellBurns. The first stage inductor. CSD10120 silicon carbide (SiC) Schottky diodes with a 1200 V. and higher thermal conductivity.7 Thermaflo E3045 heat sink profile. where both diodes are mounted on a single heatsink (Wakefield 63720ABP) that has a rated temperature rise of 55º C with 6 W dissipated from both devices. Schottky diodes are advantageous due to their inherent fast switching speed and low reverse recovery loss compared to Si.6 are two Cree Inc. The low power loss and low device temperature rise allows the use of a small heatsink. 10A rating each in a TO-247-3 package. L1. 1200 V. p-n junction diodes.Figure 3. Such advantages are the following: approximately 10 times higher voltage blocking ability..

The tested capacitance of each capacitor is 237 µF with 0. which prevents the first stage output from exceeding approximately 800 V.005 .6 with a value of 76. to prevent damage to the IGBT gate 60 . The manufacturer’s product data of the inductors is given in Table 3. TVS diode. Ohms . which represents the current level at which the inductance decreases by 5% from the initial (zero-DC) value at steady state conditions.85. transient-voltage suppressor (TVS) diodes in series.523 as specified in section 2. DC resistance. The inductors were selected with an expected peak current of 50A or less. Auto-Z impedance meter. and was measured with a Sencore LC102.24 Ω series resistance.2.4 µH at 1 kHz.2. P6KE400A. 450 V rated capacitors in series.6 µH for L1. Table 3. actual prototype inductor currents are analyze in Chapter 5. Inductance 15 µH 22 µH Model # 7000-03 7000-05 Max. The actual inductance of 85. The “incremental current” in Table 3.5 to 0. Auto-Z impedance meter. The gate-to-emitter voltage of the IGBT is also limited to approximately 18 V with a P6KE18CA. The capacitors are placed in parallel with two. Amps 24 21 Incremental Current. Amps 52 41 The capacitors used for C1 are two Nippon Chemi-con 220 µF.4 µH changes the duty ratio from 0. which was measured with a Sencore LC102. Incremental current is the minimum current at which the inductance will be decreased by 5% from the initial (zero-DC) value. was used to define the peak current rating of the inductors.2 Caddell-Burns inductor specifications.007 Rated IDC.

886) 61 .3. IGBTs + heat sinks Gate drive Diodes +heat sink Inductors Capacitors Total Volume: in3(cc) 90 (1.085 (492) 0. VLSI circuits.from spurious voltage spikes. Table 3. technology such as the recent developments in micro-channel heat sinks with flowing.5 (221.25(1. but the volume and mass of the cooling system may be reduced by a factor of two with a more efficient COTS heat sink extrusion profile.125 (16. This experimental system has the potential for further volume and mass optimization with redesign of the first stage IGBT cooling. two-phase liquids for server CPUs.5) 13.3.82 (372) 4. The volume and mass of individual components of the second stage are shown in Table 3.68) 1.25 (102.3 Volume and mass of first stage components using COTS components. as is discussed in Chapter 6.2) 10.158 (1. which gives a baseline understanding and allows for projection of the system volume scaled to higher power levels.375 (22. may be efficient enough to extract over 500 W/cm2 in the near-term [15-16].987) Mass: lbs(g) 2.4) 121. Also. Notwithstanding. Such technology has the potential to reduce the cooling system volume and mass to a fraction of the volume and mass shown in Table 3. The heat sinks in the first stage were utilized primarily due to availability and cost. the gate to emitter voltage must not exceed ± 20 V according to the manufacturer’s recommendations.475) 6.13 (966) 0. the volume and mass of the prototype cascade boost converter’s first stage provides adequate cooling for operation of the experimental circuit.077 (34. and power electronics.046 (21) 0.4) 1.

was custom built by Loree 62 . Figure 3. a single inductor. which includes isolated gate drive circuitry and switch over-voltage protection.3 Second Stage Detail The second stage of the cascade boost converter prototype consists of a stack of six IGBTs in series.9. 5 µF CSI Capacitors) Figure 3. This IGBT stack assembly. and is designed for optimization of switching efficiency using COTS IGBTs in a customized stack assembly.5 mH Diodes: (6 series 10ETF12FP) + First stage DC output voltage Gate Driver IGBT stack: (6 series IRGP30B120KD-E) 5 µF 25 kΩ load (10 series Ohmite 2K5L225J) Optically isolated gate signals & isolation transformer 5 µF Gate Driver 12. six diodes in series. This section presents the second stage components and includes the design of the output load.5 V power supply DC filter capacitors (2 series 3.8 shows the schematic of the second stage with the components utilized for the prototype converter.8 Schematic of second stage components The IGBT stack was built with six IGBTs in series. The stack is shown in Figure 3. and two output filter capacitors in series.3. Inductor (Stangenes nanocrystalline core) 3.5 kV.

63 . The gate driver boards provide +15 V for turn-on. The design of the stack uses International Rectifier.7 Ω gate resistor in series with the gate. and gate drive boards are given in Appendix A. with 0. isolated power oscillator. The circuit schematics with details of the stack’s isolated trigger board. the trigger signal. IRGP30B120KD-E 1200 V. Each IGBT gate signal is transmitted through fiber-optics to the individual isolated gate driver boards on which the IGBT is connected. These IGBTs are the same devices as the first stage IGBTs.5” radius rounded corners and 3/32” rounded edges. The stack requires a 12 V DC power input. and 0 V for turn-off through a 4.15” x 3” x 0. 60 A rated Non-Punch Through (NPT) IGBT devices. and was forced-air cooled at full power operation.1875”).Engineering to UMC specification for the cascade boost converter. The heat sink for each IGBT is a flat milled aluminum plate (measuring 5.

Figure 3. each rated at 1200 V and 10 A average. The second stage inductor. L2. and is built with 64 .5 mH at 1 kHz with a Sencore LC102. as is common on TO-220 packages. Six diodes in series form the second stage 5 kV boost diode. operating as the second stage switch.4 mH. These diodes come in a TO-220 “FullPack” package.9 The IGBT stack with six IGBTs in series. No heat sinks are utilized for the diodes since the expected power dissipation is nearly negligible. was built by Stangenes Industries to the given inductor specifications of the cascade boost converter of 3. where the collector terminal is not exposed on the backside of the diode. The diode stack consists of International Rectifier 10ETF12FP diodes. Auto-Z impedance meter. The tested inductance was 3.

the nanocrystalline core material represents modern technology for inductor and transformer magnetic cores in power electronics [17-18]. to increase from the ideal value of 0. D2.5 calculated using the equations in Chapter 2 to the actual value of 0. which is used as a basis to scale the cascade boost converter to higher power levels in Chapter 6.502. and combines the high maximum flux density of iron-based cores. The inductance of 3. The design expertise of Stangenes provided a high quality nanocrystalline-core inductor for the design. Analogous to SiC in the semiconductor industry. The nanocrystalline core material provides the low core loss of ferrite cores. 65 .5 mH for L2 results in the duty ratio.four nanocrystalline “C” cores with a 3 mm gap spacing.

ten 2. wire wound.5 kΩ. The resistors are Ohmite.4. The load was measured and found to be 25 kΩ. These resistors are rated for 3 kV dielectric voltage hold off. vitreous enamel power resistors (2k5L225J). To achieve operation at a full output voltage of 5 kV and 1 kW. both before and immediately after a dissipation power level of 1 kW output.The load for the cascade boost converter has an impedance of 25 kΩ. 66 . these volume and mass values for the cascade boost converter prototype will be used for scaling to higher power levels. The load is not included in the volume and mass measurements.10. 225 W rated resistors were arranged in series. The volume and mass of the individual second stage components is shown in Table 3. where each resistor was de-rated to handle 500 V and dissipate only 100 W. and the laboratory temperature was also maintained below 25ºC. A fan provided a constant air flow across all ten resistors. As with the first stage. The load is shown in Figure 3.

125(1. but reduction in weight is possible with research specifically aimed at engineering an advanced cooling system and utilizing next generation light67 .027(12) 4. wire wound resistors for dissipation of the 1 kW output of the prototype.518) 0.35(1.10 The output Load with 10 series Ohmite. This figure is not lightweight.008) The total bench top cascade boost converter volume and mass is shown in Table 3.Figure 3.362) 77.540.04(5.75) 83.1 (5.158) 2.76(2.9(1. The total mass of the system is 15.656(10. which represents about 15 lbs/kW.5. Table 3. IGBT stack Diodes Inductor Capacitors Total Volume in3(cc) 177(2.3(1267) 338.5) Mass lbs(g) 3.4 Volume and mass of the second stage components.2 lbs.330) 11.900) 0.

5) 459. Table 3. NPT (Non-Punch Through) IGBTs from Dynex Semiconductor. the six-series stack of 1200 V IGBTs was designed to replace the two 3.3 kV IGBT modules in series. This high switching loss limited the total cascade boost circuit efficiency to approximately 37%. which resulted in high average switching loss of over 1. high density capacitors.1.008) 15. This experimental evidence validates the preceding IGBT switching theory in section 3.886) 11. The weight and volume of the prototype is dominated by commercial off the shelf components.3.04 (5.3 kV IGBT modules is presented in the following. Circuit measurement waveforms and improvement of the switching efficiency performance of the six-series IGBT stack in contrast to the two 3.1 kW. and switches.540.3 kV IGBTs and provide lower switching loss. Using the IGBT theory discussed in section 3. 3.35 in3 or 0.35 (7. The 3.weight.5 Total cascade boost converter prototype volume and mass. inductors.4 Second Stage Switch Design Optimization The original design of the second stage switch utilized two high current. Two of these IGBTs are packaged in a single module unit 68 .25 (1.4) Mass lbs(g) 4. and can be substantially reduced in an aerospace rated system.1 (5.894) 3.008 m3. which does not include a packaging factor. The total volume of the system is 459.2 (6.527.3 kV IGBTs are 200 A rated. First Stage Second Stage Total Volume in3(cc) 121.158 (1.987) 338.

and the integration of this power loss results in a total of 126. and synchronized by simultaneous gate signals.5 mJ of energy loss per pulse.3 kV IGBTs in series replaced the six 1200 V IGBTs. the heat sink thermal resistance is rated as 0. The second stage schematic is similar to the circuit shown in Figure 3.11 shows the turn-off voltage and current waveforms of the two 3.6 kW. except that two 3. At this flow rate. 69 .3 kV IGBTs in series. Figure 3. The IGBTs devices in the module package were connected in series. with the maximum IGBT junction temperature at 125 ºC. and the combined IGBT maximum power dissipation handling results in approximately 2.3 kV IGBTs in series as the second stage switch in the cascade boost converter operating with an output of 5 kV and 1 kW. At a switching frequency of 9 kHz. this turn-off energy loss per pulse equals an average power loss of 1139 W for the two 3. The performance of the two 3. Both gate signals operated with 4.7 gpm water flow rate.8. The heat sink used for thermal management is a liquid cooled heat sink from Aavid Thermalloy (part number: 416101U00000) and was applied with approximately 0.3 kV and the six 1200 V IGBTs in series demonstrates a significant difference in switching loss. The module has a 6 kV isolated base plate for mounting to a grounded heat sink. Figure 3.4 Ω external gate resistors. The total thermal resistance for each IGBT becomes 0.077 ºC/W.013 ºC/W.designed for half-bridge circuits for application in motor control or the traction industry.12 displays the power loss during turn-off.

08 0.3 kV Dynex IGBT Turn-0ff Los s 60 50 40 30 Second s tage s witch turn-off los s Energy Los s 0.5 mJ 0. 2 Series 3.24 0. The integrated energy loss is 126.16 0.5 mJ per pulse. A comparison of the two IGBT turn-off loss figures is shown in Table 3.2 0.12 Power loss waveform of the two 3.3 kV IGBTs in series.7 shows the necessary switching duty ratio increase to compensate the switching loss in 70 .12 Eof f = 126.3 kV IGBTs in series as the second stage switch of the cascade boost converter with and output of 5 kV and 1 kW.6.2 Series 3.04 0 8 9 10 11 12 13 14 15 16 17 18 Tim e ( µ s ) Power ( kW ) 20 10 0 Figure 3. which results in an average power loss of 1139 W.3 kV Dynex IGBT Turn-0ff Waveform 6000 Collector-Emitter Voltage (V) 5000 4000 3000 2000 Second stage switch voltage Second stage switch current 6 4 12 10 8 Switch Current ( A ) Energy (J) Current tail 1000 0 8 9 10 11 12 13 Time ( µs ) 14 15 16 17 18 2 0 Figure 3. Table 3.11 Voltage and current waveforms of two 3.

The first stage IGBT loss also increases with the 3. 200 A IGBTs 6 series 1200 V.6 Turn-off loss comparison of the two IGBT designs.55 W 71 . The duty ratio for the second stage was limited to 0.7 with two series 3.6 mJ Average turn-off power loss 1139 W 93.3 kV IGBTs implemented in the second stage since the first stage peak switch current must increase proportionally to regulate the voltage across C1.the 5 kV output converter. Again.3 kV. the switching duty ratios of both stages were maximized in order to optimize the converter’s step-up ratio. The optimized cascade boost converter’s maximum voltage gain was only 46. 60 A IGBTs Turn-off energy loss 130 mJ 11.7. 2 series 3.66 as the current limit and near-saturation effects of L2 were reached at marginally higher duty ratios. using an input voltage of 107 V as shown below in Table 3.3 kV devices resulted in a cascade boost converter efficiency of approximately 37%.3 kV IGBTs for S2. The 5 kV and 1 kW output was achieved. The increased duty ratio increased the peak inductor charging current and the average input current to the converter from the source power supply. Table 3. Due to the maximum first stage IGBT power loss limitations and the second stage inductor current limit. the loss of the 3.

8 .1 A 503 V . where the high voltage rated IGBTs exhibit a long and substantial current tail. 60 A IGBTs 76.12 demonstrate the theoretical relation between voltage ratings and current tail magnitudes in IGBTs. The redesign of S2 with six series 1200 V rated IGBTs experimentally demonstrates a lower current tail loss and faster switching speed.513 34.66 50 A 11.11 and Figure 3. 200 A IGBTs 37 % 107 V 24.614 0.6 % 100 V 13. The waveforms of Figure 3.3 kV and 1200 V IGBTs.6% from 37%. Analysis of the IGBT stack turnoff switching loss and further experimental results of the prototype cascade boost converter are detailed in Chapter 5. Efficiency Input voltage Average input current First stage output D1 D2 iL1 max iL2 max 2 series 3.3 kV.5 A 8. which results in nearly 92% lower loss in S2 and increases the efficiency to 76.3 A 6 series 1200 V. 72 .8 A 589 V 0.7 Cascade boost converter parameter comparison of 3.Table 3.3 kV rated IGBTs motivated the redesign of S2 to achieve a lower switching loss.1 A The low system efficiency using 3.

NJ: Prentice-Hall Inc.” in 1997 Proc.” in 2002 Proc. “Low Turn-off Switching Energy 1200V IGBT Module. and T. 73 . Kang. pp. 105-108. “Control of the switching transients of IGBT series strings by highperformance drive units. pp. Y. 1.” in 2003 Proc. Power Electronics.-W. R. Kim.. pp. vol. 12-15. on Industrial Electronics. pp. Mohan.0 [1] [2] N. 1991. “Switching behaviour of high voltage IGBTs and its dependence on gate-drive. [11] H. ISPSD. 46. Petterteig. Holonyak. Dynex Semiconductor application note. Record of Industry Applications Society Annual Meeting. pp. AN4504 (http://www. A.M. pp.C . “FieldStop IGBT with MOS-like (tailless) turn-off. 1042-1049. Lode. 2165-2169. Chokhawala.” 1992 Conf. Englewood Cliffs. B. May 1999. vol.” IEEE Trans. IGBT Theory and Design. Miserey.com) V. pp. 1995. Khanna. “Analysis of CIC NPT IGBT's turn-off operations for high switching current level. Streetman. 2003. [12] X. 2nd Edition. Industry Applications Conf.1042-1049. [3] [4] [5] [6] [7] [8] [9] [10] H.. 1186-1195. 338-340. 2nd ed. record on Industry Applications Society Annual Meeting. N.” 2002 Conf. “Gate drive considerations for IGBT modules. G.REFERENCE FOR CHAPTER 3. vol. Piscataway. Jr. pp.. 21752181. New York: John Wiley & Sons. on Electronic Devices. 1. Husken. Solid State Electronic Devices.dynexsemi. NJ: IEEE Press. J. S. June 2001. Raciti. 482490. pp. 48. “Excess carrier density and forward voltage drop in trench insulated gate bipolar transistor (TIGBT). 1980.” in 2002 Proc. MIEL Conf. “IGBT turn-off losses for hard switching and with capacitive snubbers. vol. Yamada. ISPSD. 3. Lefebvre and F.. Ed. vol. [13] J. K. “Characterization and modeling of high-voltage field-stop IGBTs. record on Industry Applications Society Annual Meeting. Undeland.” IEEE Trans. A.” Conf. Gerstenmaier..

IEEE Industrial Electronics Society. 2003. 1998.” in Proc. “Design technology of high-voltage multi-megawatt polyphase resonant converter modulators” in Proc. 236241.[14] P.R. “Practical design of a 1000 W/cm2 cooling system. Conf.” in Proc. [16] G.A.4. [18] W. Ferch. Rease. 2003. pp. pp. 411-415. “Light transformers for kilowatt SMPS based on nanocrystalline soft magnetic cores. 223 – 230. of Seventh Int. Palmer. pp.4 [17] M. 2003. [15] D. IEEE Semiconductor Thermal Measurement and Management Symposium. 32. Faulkner. Upadhya.1 . Conf. of 29th Annu. “Closed-loop cooling technologies for microprocessors. on Power Electronics and Variable Speed Drives. Electron Devices Meeting.” in Tech Digest IEEE Int. “A comparison of IGBT technologies for use in the series connection. Power Electronics and Variable Speed Drives Int. pp. Conf.” in 1996 Proc. 74 . 19th Annu. 96-101. pp..4.32.

The output DC voltage of the cascade boost converter was measured with a Fluke 80k-40. 1000X high voltage probe.1 Voltage Diagnostics The voltage diagnostics include DC voltage measurements and time varying voltage measurements. digital multi-meter.0 DIAGNOSTICS OF THE CASCADE BOOST CONVERTER PROTOTYPE Evaluation of the cascade boost converter operation requires utilization of the current and voltage waveforms in the system. The Fluke 80k-40 probe is connected to a Fluke 23 III. Also. the second stage of the cascade boost converter requires voltage diagnostics designed to measure the high voltage DC and time-varying voltage transients. The waveform diagnostics are paramount for gauging component loss and verification of system performance. The attenuation and frequency bandwidth response of the voltage probes used for the cascade boost diagnostics are shown in Table 4. The Fluke 80k-40 probe has a maximum voltage rating of 40 kV DC.CHAPTER 4. 4. The voltage measurements in the first and second stage require accurate voltage diagnostics for measuring fast-changing switch voltage. For 75 . the current measurements require diagnostics capable of accurately measuring the current magnitudes in the system. and is designed to interface with digital multi-meters with 10 MΩ ( ± 1%) input impedance or greater. This chapter describes the diagnostic equipment used in the measurements of the experimental cascade boost converter. Additionally.1.

input power supply. a Fluke 77 II. was also used to measure the first stage output voltage for measurement of first stage voltage ripple. which monitored the switch duty ratio and the switching frequency for each stage of the cascade boost converter. The P6015A has a 20 kV maximum DC voltage rating. digital multi-meter was connected directly across capacitor C1. and includes a compensation box for probe frequency response characteristics. The cascade boost converter’s voltage waveforms of the first and second stage IGBTs and the output voltage ripple were measured with a Tektronix P6015A.3%. The input DC voltage was monitored using the voltage monitor on the front panel of the PowerTen P83C-30033. 75 MHz bandwidth. Voltage Probe Fluke 80k-40 Tektronix P6015A Tektronix P5100 Hewlett Packard 10071A Attenuation 1000X 1000X 100X 10X Bandwidth DC-60 Hz 75 MHz 250 MHz 150 MHz 76 . The Fluke 23 III and 77 II DC voltage measurement accuracy is ± 0.the first stage output DC voltage measurement. 100X voltage probe.1 Voltage probes for circuit diagnostics including attenuation factor and bandwidth. 1000X high voltage probe. and output DC voltages. 10X voltage probe. A summary of the voltage diagnostics is displayed in Table 4. A Tektronix P5100.5 kV maximum rating.2 below. These DC voltage diagnostics provide a convenient method to observe the cascade boost converter’s input. The measurement of the IGBT gate drive circuitry was accomplished with a Hewlett Packard 10071A. and the accuracy has been verified with a Fluke digital multi-meter. first stage. which has a 2. Table 4.

model SI 17385. The probe has a 4 inch outer diameter and a 2. It has a rating of 10 kA. One of the current monitors is a Pearson Electronics current monitor model 110A. 0. 77 .3 below. and maximum RMS current of 30 A. These specifications will also satisfy the diagnostic requirements for accurate current measurement. These specifications allow the 110A current monitor to accurately measure the system current. The Stangenes current monitor gives an output of 0. a usable rise time of 20 ns.8% droop/ms. This current monitor gives an output of 0.0 % droop/ms.25 inch outer diameter and 1 inch inner diameter. has a rating of 5 kA.1 inner diameter.1 V/A of current flowing through the conductor being measured. Measurement Input Voltage First Stage Output DC Voltage Second Stage Output DC Voltage First Stage Output Waveform Second Stage Output Waveform First Stage IGBT Waveform Second Stage IGBT Waveform Diagnostic Equipment Power supply (PowerTen P83C-30033) voltage monitor display Direct connection to a Fluke 23III DMM Fluke 80k-40 1000X HV probe to a Fluke 77II DMM Tektronix P5100 100X probe Tektronix P6015A 1000X HV probe Tektronix P6015A 1000X HV probe Tektronix P6015A 1000X HV probe 4. This probe is smaller in size.1 V/A. usable rise time of 20 ns. and maximum RMS current of 65 A.2 Current Diagnostics All of the current measurements were made using two current monitors. 1.Table 4. The second current monitor is made by Stangenes Industries. A summary of the current diagnostics are displayed in Table 4.2 Measurement and diagnostic equipment implemented. consuming 4.

where data analysis was completed using Microsoft Excel and MATLAB.8 %/ms 1.3 Current monitors for circuit diagnostics Current Monitor Pearson 110A Stangenes SI 17385 Output 0.1 V/A Peak Current 10 kA 5 kA Maximum Continuous Current 65 A RMS 30 A RMS Usable rise time 20 ns 20 ns Droop 0. The waveforms and 78 . four channel color digital phosphor oscilloscope. component loss analysis are also presented in Chapter 5. The TDS3034 oscilloscope bandwidth is 300 MHz and has a sample rate of up to 5 GS/s. The waveform data was collected and saved on to a computer disk. Specific measurement setups for the voltage and current diagnostics and data analysis processes are discussed further in Chapter 5.Table 4.0%/ms 4.1 V/A 0.3 Oscilloscope The voltage and current measurements utilized a Tektronix TDS3034.

and are summarized in Table 5. and a regulation of better than +/.6%.0 CASCADE BOOST CONVERTER PROTOTYPE RESULTS The output. where the prototype converter has satisfied the goals given in Chapter 3. an output of 5 kV DC at 1 kW.0. It is believed that the efficiency improvement is possible with additional optimization of the circuit. Table 5.CHAPTER 5. The gains for the first and second stages were 5 and 10. respectively. The experimental converter has demonstrated a step-up voltage gain of 50. The detailed analysis of the component loss is used for extrapolation of the loss per stage. such as lowering the inductor losses and the IGBT switching loss with faster switches and possibly parallel stages.5%. Voltage Input Voltage Output Power Output Output Voltage Regulation 100 V 5 kV 1 kW +/.1.1 Cascade boost converter prototype design goals. efficiency. and loss analysis of the cascade boost converter prototype. With the switching frequencies operating at 20 kHz for the first stage and 9 kHz for the second stage. Thus a 100 V DC input was stepped up to 5 kV DC into the 25 kΩ resistive load.0. which produces an output power of 1 kW. the converter efficiency resulted in 76. and also enables a realistic loss estimation of the cascade boost converter scaled to higher output power and voltage levels. are described in the following sections.5% 79 .

1 and Figure 5. The second stage output was measured with the Fluke 80k-40. The converter output ripple is measured to be 49. The switch duty ratios were adjusted manually to tune the step-up voltage gain to 5 for the first stage and 10 for the second stage.2.614 and . and the converter output voltage. respectively. According to these results. The first stage output voltage waveform. with an average output of 5 kV. which resulted in . is shown in Figure 5.5.513 for the first and second stage duty ratios. As discussed in Chapter 4.2. as can be seen in Figure 5. which coupled to the first and second stage outputs.5 µF filter capacitance used for the converter appears to be the minimum capacitance to achieve a +/-0. oscilloscope.3 V. the input voltage to the cascade boost converter was measured using the voltage monitor on the front panel of the input power supply (PowerTen P83C-30033). the first stage DC output voltage was measured with the Fluke 77 II digital multi-meter. In order to provide 80 .1. and the Tektronix TDS3034. The output voltage of the first and second stage was also measured with the Tektronix P6015A. respectively. is displayed in Figure 5. the 2.5% regulation goal. digital multi-meter. with an average of 503 V.5% regulation when stray switch inductance of the actual circuit is present. 1000X high voltage DC probe and Fluke 23 III. which corresponds to a regulation of +/-0.49% and meets the +/-0. high voltage probe.1 Cascade Boost Converter Output and Efficiency The circuit performance of the converter is evaluated in this section while operating with a DC output voltage of 5 kV from a 100 V DC input. The stray switch inductance in both stages resulted in a voltage overshoot across the switches during turn-off.

for a voltage gain of 5 from the 100 V input. ∆1T 450 400 Tim e ( µ s ) Figure 5. the switch overshoot was attenuated by the output capacitors. the average output voltage is displayed at 503 V.regulation within the specified value. Firs t Stage Output Voltage 600 550 1 st Stage Output ( V ) Averge voltage = 503 V 500 Stray switch inductance voltage spike. Thus the capacitor volume and mass will be reduced and result in a more compact converter design. mitigation of stray inductance from a low-inductance circuit design can lead to an optimal output regulation with reduced filter capacitance.1 First stage DC output voltage. 81 . In a future design.

the first stage output voltage.2]. the time-average power delivered to each stage was calculated as the following: [5.6. the average output voltage is displayed at 5010 V. and the second stage inductor current waveform is shown in Figure 5.3] 82 .1]. [5. for a voltage gain of approximately 10 from the 503 V first stage output. The time-average value of each current waveform equals the average input current per stage.Second Stage Output Voltage 5200 2 nd Stage Output ( V ) 5100 Averge voltage = 5010 V 5000 ∆2T 4900 4800 Time ( µs ) Figure 5. The efficiency values were calculated by using the input voltage.2 Cascade boost DC converter output voltage. The Pearson 110A and the Stangenes current monitors were utilized to measure these inductors currents. [5. and the converter output voltage.5. Thus. The average current values were determined using the current waveforms measured from the first and second stage inductor currents. These values were then multiplied by the average current flow at each stage. The first stage inductor current waveform is shown in Figure 5.

83 . and I 0 − I 2 are the average current values from the respective stage.P 0 = (VDC 0 ) I 0 . respectively. VDC2 is the converter output voltage.4. show a highly linear relationship with the input. and the voltages per stage. are shown in Table 5. first stage efficiency. VDC1 is the first stage output voltage. The converter’s first stage output voltage. the input voltage to the cascade boost converter was gradually increased from 0 V to 100 V.3] where P0 is the average input power. Table 5.2] [5.2 summarizes the average values measured in the cascaded boost converter. and second stage efficiency with respect to the output voltage is shown in Figure 5. Also. P1 is the average first stage output power. P2 is the average second stage output (converter output) power. VDC0 is the input voltage.3 summarizes the calculated efficiency and loss of the system per stage.3. The total system efficiency.1] [5. Table 5.513 for S1 and S2. )(I ) . 2 [5.4. shown in Figure 5. rising from an increasing input voltage. P1 = (VDC1 1 P 2 = (VDC 2 ( ) )(I ) .614 and . where the average current values listed are the time average values of the stage input currents as discussed above. with constant switch duty ratios of .

77% 76.98 W Table 5.470 3.4 First stage and second stage voltage data of the cascade boost converter prototype as input voltage is varied from 0 V to 100 V.3 A 200.3 Efficiency and loss for the first and second stages operated at 5 kV output.2 Average value data of the system operated at 5 kV output.33% 86.2 200.310 W 1.990 4.1 A 2.984 3. First stage Second stage Total system Efficiency 88.9 W 153.157 W 1.4 mA Average Power 1.485 2.64% Power Loss 152.1 93.530 5.9 351 401 454 503 Second Stage Output (V) 0 428 931 1.7 300.3 252. Input Voltage (V) 0 10 20 40 50 60 70 80 90 100 First Stage Output (V) 0 48.Table 5. DC Voltage 100 V 503 V 5.010 V Average Current 13.010 84 .964 2.08 W 305.004 W Converter Input First Stage Output Converter Output Table 5.

3 First stage and second stage output voltages as input voltage is varied from 0 to 100 V. with constant switching duty ratios of .513 for the first and second stages respectively. 85 .614 and .First & Second Stage Output Voltage 6000 Firs t Stage Output 5000 Second Stage Output 4000 Output Voltage 3000 2000 1000 0 0 20 40 60 Input Voltage 80 100 120 Figure 5. Cascade Boost Efficiency 100% 90% 80% 70% Efficiency 60% 50% 40% 30% 20% 10% 0% 0 1000 2000 3000 Output ( V ) 4000 Total Efficiency 2nd Stage Efficiency 1st Stage Efficiency 5000 6000 Figure 5.4 Efficiency of the individual stages and the overall converter.

6.1. As the converter losses accrue.5 mH and the ideal converter inductor is 3. where the ideal converter operated at a duty ratio 0. the larger duty ratios of the prototype converter are a result of larger inductor values. One of the obvious differences is the larger duty ratio of the prototype converter. These differences are to be expected due to the non-ideal properties and losses of the prototype converter. The rising current slope of the first stage inductor. the duty ratio must be increased to store more energy in the inductor that provides compensation for the losses. In addition to the losses. as compared to the simulation. or di/dt. of the rising first stage inductor current. which is larger than the 76.6 µH ideal inductance value.513 in the prototype converter. The same effect is seen in the second stage.5.The inductor charging currents of the cascade boost converter prototype shown below in Figure 5. accounts for about 30. The actual inductance utilized in the first stage is 85. 86 .3 mH. indicating a closed position of the first stage switch. and 0.4 µH as described in section 3.6 display subtle differences with the inductor currents produced by the ideal converter simulated and discussed in section 2.5 and Figure 5. where the actual inductor is 3.1 µs of the total 49 µs switching period. The duty ratio of the second stage is 0. The larger inductance is evident by the lower time-rate of change.5 in the ideal converter simulation.614 duty ratio. This corresponds to a 0.

Second Stage Input Current 10 8 Input Current ( A ) Experimental Current Simulated Current 6 4 2 0 -2 0 20 40 60 Tim e ( µ s ) 80 100 120 Figure 5.Firs t Stage Input Current 40 35 30 25 20 15 10 5 0 -5 0 5 10 15 20 25 30 Tim e ( µ s ) Experimental Current Simulated Current Input Current ( A ) 35 40 45 50 55 60 Figure 5.5 First stage experimental and simulated input currents when the converter is operated with a 100 V input and 5 kVoutput.6 Second stage experimental and simulated input currents when the converter is operated with a 100 V input and 5 kV output. 87 .

2.2 Component Loss Analysis The loss analysis of the cascade boost converter prototype operating at 5 kV output indicates that the IGBT switching loss and inductor loss are the two most significant components of the total power loss.513 5.5.5. The loss analysis also provides a baseline for the loss of a cascade boost converter scaled to higher power levels. the cascade boost converter operating conditions are shown below in Table 5. and the Pearson CT was setup to measure the inductor 88 .5 Cascade boost converter operating conditions for the component loss analysis Input Voltage First Stage Output First Stage IGBT Frequency First Stage Duty Ratio Second Stage Output Second Stage IGBT Frequency Second Stage Duty Ratio Circuit Conditions 100 V 503 V 20 kHz 0. diode. The following discussion estimates the switching. the loss in the inductor was derived.1 Measurement of the First Stage IGBT Loss The loss of the first stage IGBTs is determined from the measured voltage and current waveforms during operation of the cascade boost converter at the full 5 kV output. The Stangenes CT was utilized to measure the combined current of the parallel diodes comprising diode D1. and capacitor loss of both stages from analysis. Table 5. and from these. For all of the following component loss analysis.614 5010 V 9 kHz 0.

for calculation of energy loss per period. D1. Utilizing functions in Excel. Average power loss is calculated by multiplying the energy loss per period by the switching frequency as in equation [5. was saved and analyzed as a spreadsheet in Microsoft Excel. This method allows for the measurement of L1. The data recorded by the Tektronix TDS3035 oscilloscope. the 89 .4] below: Ploss = fs ∗ Eloss / period = fs ∗ ∫ v(t )i (t )dt . The power loss waveforms were integrated. The turn-off loss and conduction loss. the voltage and current waveforms were multiplied together to produce the waveforms for power loss. were processed separately and the respective average powers were added together to derive the total switch loss. The voltage probe setup includes the P5100 probe measuring the voltage across C1.4] where v(t) and i(t) are the instantaneous voltage and current values. The IGBT turn-on loss was neglected due to the zero turn-on current inherent in discontinuous conduction mode of the cascade boost converter. The derivation for the average conduction loss of the IGBTs is discussed in Appendix C. during the on-state. Also.current of L1. and S1 current with two current monitors. The MATLAB routine that was used for integration is given in Appendix B. and the P6015A probe across the collector and emitter of one IGBT. using a custom routine in MATLAB. The combined current of the parallel IGBTs is found by subtracting the diode current from the inductor current. 0 T [5.

where the current is sum of both collector currents.8 shows the IGBT turn-off power loss waveform for the two first stage IGBTs. commonly termed the “current tail”.slow time-rate of change of switch current.7 shows the turn-off voltage and current waveforms of the two first stage IGBTs in parallel.3 W per IGBT or 98.6 displays a summary of the IGBT waveforms and average power loss. Table 5. 90 .57 W total. the current tail loss significance reduces as the turn-off current is increased [1].4. The first stage IGBT turn-off demonstrates decaying current after the initial fast drop in current. Average power loss calculated from these waveforms is 49.5. Figure 5. after turn-on. According to IGBT theory. as seen in Figure 5. is limited by the inductance of L1. The current tail increases the turn-off loss significantly and is an inherent characteristic which results from the minority carrier recombination and the bipolar junction transistor component of the IGBT. Figure 5. the current tail does not scale linearly with the IGBT current at turn-off. where the cascade boost is operating at the conditions shown in Table 5. This explains the increasing system efficiency as the input voltage is increased.

83 mJ Figure 5. 91 .5 1 1.5 3 Eof f = 4.0 12.8 First stage turn-off power loss.First Stage Switch Turn-0ff Waveform 700 Collector-Emitter Voltage (V) 600 500 400 300 200 First stage switch voltage First stage switch current 40 35 Switch Current ( A ) 30 25 20 15 Current tail 100 0 0.83 mJ at 20 kHz for 98.0 4.0 6.0 10.0 2.5 3 10 5 0 Figure 5.0 0. First Stage Turn-0ff Loss 20.0 Power ( kW ) 14.5 Time ( µs ) 2 2. The integrated turn-off loss = 4.0 8.5 1 1.7 Turn-off voltage and collector current waveforms of the first stage IGBTs in parallel.57 W average loss.5 Time ( µs ) 2 2.0 0.0 18.0 16.

57 W 5.55 W 36.4 kHz) 0. The Pearson probe measured the total emitter current of the IGBT stack.614 34.2 Measurement of the Second Stage IGBT Loss The second stage IGBT loss was determined by the same process as the first stage IGBT loss.10 below. and two Tektronix P6015A 1000X probes.6 Summary of the first stage IGBT data.Table 5.2. 92 . and the other was used to measure the converter output voltage. The turn-off voltage and current waveforms and turn-off loss are shown in Figure 5.9 and Figure 5.5 A 503 V 94 ns 240 ns 12. The diagnostic equipment used to monitor the voltage and current includes the Pearson and the Stangenes current transformers.75 W 98. Switching period (frequency) Duty ratio Ic Vce Voltage rise time (10-90%) Current fall time (90-10%) Conduction loss per IGBT Turn-off loss per IGBT Total IGBT loss 49 µs (20. One of the P6015A probes measured the collector voltage.

7 W average loss.10 Second stage IGBT stack turn-off power loss.5 4 Eof f = 11.Second Stage Turn-0ff Waveform 6000 5000 7 4000 Second stage switch voltage 3000 2000 1000 1 0 0 1 2 Time ( µs ) 3 4 5 0 Second stage switch current 6 5 4 3 2 Emitter Current ( A ) 9 8 Collector-Emitter Voltage (V) Figure 5.6 mJ at 9 kHz for 104. The integrated turn-off energy loss = 11. 93 .9 Turn-off voltage and current waveforms of the second stage IGBT stack.5 2 2.6 mJ Figure 5. Second Stage Turn-0ff Loss 40 35 30 Power ( kW ) 25 20 15 10 5 0 1 1.5 Time ( µs ) 3 3.

The analysis of determining average power loss is also the same as the IGBT average power loss. The first stage diode average power loss has been determined to be 1.2. The parallel SiC Schottky diodes exhibit very low reverse recovery current loss.1 A 5010 V 2W 15. but considered to be a result of stray capacitance and inductance in the diagnostic equipment and circuit. a differential voltage measurement was taken by subtracting the output voltage from the IGBT collector voltage to obtain the voltage across the diode. High frequency oscillations and noise occurring in the following waveforms are significant.22 W 104.67 W from an integrated 94 .Table 5.7 W 5. where the diagnostic setup for measuring the diode current and voltage waveforms is identical to the measurements of the first stage IGBT waveforms.7 Summary of second stage IGBT data. However. Switching period (frequency) Duty ratio Voltage rise time (10-90%) Current fall time (90-10%) Current at turn-off Off-state voltage Conduction loss per IGBT Turn-off loss per IGBT Total IGBT stack loss 110.6 µs (9. The small negative current aberration following the 8 µs mark may be due to junction and stray capacitance as a result of the time rate of change in the diode voltage [1-3].11 and Figure 5.3 Measurement of Diode Losses The diode loss in the first stage was measured.12 display the diode current and voltage waveforms.513 586 ns 438 ns 8. Figure 5. Such oscillations produce zero net energy loss after integration as they are purely reactive.04 kHz) 0.

7% of the IGBT loss. the diode loss represents only 1.87 mJ per pulse. This loss generally agrees with the very small temperature rise of the heat sink on which the diodes are mounted.11 First stage diode voltage and current waveforms. As a comparison. 95 .energy loss of 0. First Stage Diode Waveforms 100 80 60 25 Diode Voltage ( V ) 20 0 -20 -40 -60 -80 -100 0 1 2 3 4 5 Time ( µs ) 6 7 8 9 First stage diode voltage First stage diode current 0 -5 20 15 10 5 Diode Current ( V ) 40 35 30 Figure 5.

13 W was determined from 0. Since six diodes are connected in series.12 First stage diode power loss waveform. along with the power loss waveform for the second stage diode. Integrated energy loss is 0. 96 . The average power loss of 4.82 mJ Power ( W ) 1000 500 0 -500 0 1 2 3 4 5 Tim e ( µ s ) 6 7 8 9 Figure 5.67 W. and the loss was determined using the same procedure as the first stage diode loss above.14 displays the voltage and current waveforms. The second stage diode was also measured with the same diagnostic setup as the first stage diode loss measurements. Figure 5.82 mJ per pulse and average power loss is 1.Firs t Stage Diode Power Waveform 2000 1500 E loss =0. 690 mW per diode is dissipated as heat.457 mJ integrated energy loss per pulse. The temperature rise of these diodes is practically imperceptible.13 and Figure 5.

457 mJ 400 Power ( W ) 200 0 -200 -400 -600 10 11 12 13 14 Time ( µs ) 15 16 17 Figure 5.Second Stage Diode Waveforms 200 150 Diode Voltage ( V ) 100 50 0 -50 -100 -150 -200 10 11 12 13 14 Time ( µs ) 15 16 17 18 Second stage diode voltage Second stage diode current 0 -1 7 6 Diode Current ( V ) 5 4 3 2 1 Figure 5.13 Second stage diode voltage and current waveforms.14 Second stage diode power loss waveform.13 W. Integrated energy loss is 0. 97 .457 mJ per pulse and average power loss is 4. Second Stage Diode Power Waveform 800 600 Eloss =0.

5] 98 .8. The capacitor loss is estimated by using the equivalent series resistance. capacitor RMS current. The RMS values are calculated in a simple MATLAB routine from the measured current waveforms.2. where ID1 is the RMS current into C1 and IL2 is the current out of C1.55 A rms. [5.204 A rms using a similar procedure as with the C1 current. can be found by addition of the RMS current flowing into C1 through D1. The MATLAB routine for the RMS calculation is shown in Appendix D. The RMS value of the first stage filter capacitor. the capacitor and inductor loss must be determined. along with a summary of the component losses presented in the previous sections.4 Total Component Loss Calculation In order to complete the total component loss calculation. and current flowing out of C1 through L2. and calculation of the I2R loss. The total capacitor power loss is given in Table 5. The resultant C1 current equals 3.5 Ω series resistance.5.064 A rms and IL2 = 3. Both capacitors have approximately 0. The current values calculated are ID1 = 7. The following accounts for the total power loss of the inductor of each stage.514 A rms. The inductor loss was determined by neglecting stray system resistance loss. and assuming the inductors consume the remaining loss. which includes core and I2R winding loss: Pinductor = Ptotal − Pswitch − Pdiode − Pcapacitor . The current through C2 is 1. C1.

a thorough semiconductor trade study can reveal alternative 99 .6 W 104.3 Optimization of the Prototype Converter The component loss analysis provides the insight as to where further design can achieve a higher efficiency of the converter. it is believed that a loss mitigating design of the switches and inductors can significantly improve the efficiency.8 W 90. can be re-designed as a single more efficient inductor.7 W 203.9 W 153. Table 5. According to Table 5. For instance.1 W 5. the switches and inductors are the leading component losses of the prototype converter. In particular.3 W 5.5 W 43. Pswitch is the IGBT loss. For the switches.8 W Capacitor Loss 6.1 W 306.8 below. made up of four inductors in series in the prototype.7 W Inductor Loss 46. and Pcapacitor is the capacitor loss as shown in Table 5.2 W 0.8 Average component power loss. minimizing the stray inductance in the first and second stage IGBT connections will reduce voltage overshoot during turn-off and the subsequent power loss. which can utilize nanocrystalline core material similar to the second stage inductor design and likely have reduced winding loss [4-5]. Total Loss per Stage First Stage Second Stage Total Average power ( W ) 152. a significant improvement to the switching loss can be made through dedicated research towards optimizing the turnoff time. Pdiode is the diode loss.0 W Switch Loss 98.8.7 W 4. As such. the first stage inductor.where Ptotal is the total power loss per stage. However.5 W 6.3 W Diode Loss 1.

100 . the total loss of a 1 kW output converter must be reduced to 111 W. For this efficiency. For example. respectively.IGBTs with faster turn-off times for the first stage and second stage switch. such as ultra-low impedance gate circuit can expedite gate charge removal during the turn-off process. such as increasing the number of parallel IGBTs in the first stage or possibly even utilizing a series and parallel matrix of high speed MOSFET devices. faster switching speed may be possible with experimentation with device configurations. The switching loss must be reduced by approximately 75% and the inductor loss must be reduced by approximately 50% of the presented prototype converter’s switching and inductor loss. Additionally. Also. the latest generation of fast-stop and light punch through IGBTs show evidence of faster turn-off time than the non-punch through IGBTs in the prototype [6-7]. development of the gate drive circuitry. These efforts of lowering the switching loss and optimizing the inductors have the potential for a future prototype converter design with an efficiency as high as 90%.

Yamada. of Seventh Int. on Power Electronics and Variable Speed Drives. Cree Inc. ISPSD. Conf.com) G. 1249-1253. Piscataway. Rease. CPWR-AN03 (www. Spiazzi. ISPSD. 1998.REFERENCES FOR CHAPTER 5. NJ: IEEE Press. J. H.0 [1] [2] [3] V.” IEEE Trans. “Performance evaluation of a Schottky SiC power diode in a boost PFC application. W.” in 2003 Proc. 96-101.cree.” in Proc. vol. 2003. Khanna. pp.” in 2003 Proc.. IEEE Industrial Electronics Society. 2003. 338-340. Husken. of 29th Annu. “Light transformers for kilowatt SMPS based on nanocrystalline soft magnetic cores. issue 6. “FieldStop IGBT with MOS-like (tailless) turn-off. Nov. pp. Industry Applications Conf. Ferch. 411-415. pp. [4] [5] [6] [7] 101 . “Design technology of high-voltage multi-megawatt polyphase resonant converter modulators” in Proc. “Low Turn-off Switching Energy 1200V IGBT Module. Power Electronics. IGBT Theory and Design. 338-340. 2165-2169. 18. K.” in 2002 Proc.A.IGBT with MOS-like (tailless) turn-off. Conf. pp. M. application note. pp. 2003. pp.

5-year.4 MW of power. 300 kW module. Voltage Input Voltage Output Power Output 1000 V 60 kV 300 kW 102 . which indicate a potential for a very compact and lightweight converter design. The DC input has also been selected as 1 kV for the converter design. which requires a total converter step-up gain of 60 instead of 50. the cascade boost circuit equations of Chapter 2. at 60 kV. and performance of the prototype converter have been integrated.CHAPTER 6. as listed in Table 6. and a 10-year volume and mass estimate of the cascade boost converter module. The following sections provide a near-term.0 CASCADE BOOST CONVERTER SCALING TO HIGHER POWER LEVELS The prototype cascade boost converter has provided a basis for a cascade boost converter scaled to the higher voltage and power output levels of 60 kV and 300 kW.1 Cascade boost converter specifications for a 60 kV. To achieve this power conditioning output. Table 6. Thus. for power conditioning applications such as gyrotron microwave tubes. As discussed in Chapter 1. and are used to derive the higher power design. Multiple converters must be paralleled to achieve the constant current.4 MW provided by CPI in Chapter 1.1. megawatt gyrotron tube power requirements of 2. gyrotron tubes require a high voltage source for support of the high current electron gun in the depressed collector configuration. eight 300 kW converters modules must be paralleled to deliver 40 A. to produce 2. as in the prototype converter.

3 A for an average second stage 103 .1 Near-Term Technology Based Scaling The design equations of Chapter 2 have been integrated into the design of the 60 kV. The parameters calculated for an ideal 300 kW cascade boost converter are shown in Table 6. If the estimated efficiency of a 300 kW converter is established to be 90%. the second stage average input current has been adjusted to be 63.2. 300 kW cascade boost converter. The parameters of this system differ from the 5 kV prototype system in correlation to the higher voltage step-up ratio of 60 and lower impedance load to deliver a 5A output. each stage of the 300 kW converter must have an efficiency of approximately 95%. The load has been simplified as a constant resistive load for a constant current electron beam.3. which is believed to be a realistically achievable value based primarily on mitigated switching losses as discussed in section 5. These parameters are also ideal parameters for a lossless converter. Thus. and have been calculated using synchronous switching waveforms for both stages. For total system efficiency of 90%. From the ideal converter design. the parameters have been calculated to provide an average input current of 333.3 kW.3 kW.6. It has been assumed that each stage contributes half of the power loss.3 A for an average input power of 333. the total power loss will be 33. The parameters corresponding to a system with a 90% efficiency are shown in Table 6.3. similar to the results of the 5 kV prototype cascade boost converter. Therefore. although in practice the load can be modeled as a complex and time-varying impedance. the switching parameters must be modified for the losses in an actual system.

input power of 316. corresponding to 90% efficiency.6 (both stages) 12 kΩ 5A 74. The primary switching device is based on the Powerex CM300DY-24NF IGBT module.3 Switching parameters adjusted. 104 . due to the increasing duty ratio. the adjusted capacitance values have been determined to reflect the realistic capacitance values of a non-ideal converter. Also.617 844 A 188 A 125 µF 1 µF The following presents the methodology for the converter volume and mass estimation using the values found in Table 6. the capacitances C1 and C2 increase slightly.632 0. Switching frequency Ideal duty ratio Load impedance Average output current L1 L2 C1 C2 10 kHz (both stages) 0. The current waveforms through L1 and L2 indicate the peak switch turn-off current of each stage. which is utilized for scaling the parallel diode and switch assemblies and inductor core sizes. Table 6. 300 kW cascade boost converter.2 Ideal parameters calculated for a 60 kV. The active switching components of the first and second stages were designed as assemblies of series and parallel IGBTs similar to the assemblies implemented in the 5 kV cascade boost converter prototype.5 kW.64 mH 110 µF 788 nF Table 6.3. Efficiency Average input power Duty ratio D1 Duty ratio D2 L1 peak current L2 peak current C1 C2 90 % 333.3 kW 0.9 µH 1.

2) for fast charge carrier recombination at turn-off. Utilizing the reported energy loss relation of 0. The switching frequency for the calculation of the turn-off loss is 10 kHz.028 mJ/A turn-off loss) with a bus voltage 600 V and switching 300 A [2].3 A (shown in Table 6. The necessary number of devices in series and parallel for S1 and S2 is shown in Table 6.1.4. which gives approximately 110 W per IGBT. Series and parallel arrangement of these modules for S1 and S2 have low loss. scales it up by 38% to 11 mJ per pulse. and is optimized for high switching frequency and low turn-off loss. This IGBT uses trench-gate technology for reduced on-state voltage and the Light Punch Through doping structure (discussed at the end of section 3. 105 . where the turn-off energy loss is considered the primary loss.which has a rating of 1200 V and 300 A with two IGBTs integrated into a single IGBT module package. is shown in Table 6.9 mJ per pulse. However. high performance switching devices produced with silicon. The voltage and current per device during turn-off and the average expected assembly turn-off loss.028 mJ/A and switching 281. scaling the loss in relation to the higher voltage of 833. The reported turn-off energy per pulse is 8.3 V (instead of 600 V).5.4 mJ (0. This IGBT module is the latest generation of IGBT devices and represents modern. the energy loss is approximately 7. based on reported turnoff energy loss per device. The device was selected based on published low turn-off energy loss figures and high switching frequency ability [1].5).

6”x7”x24” model (part #: 416301U). and Tl is the liquid coolant temperature [3]. and total average turn-off loss.8 V Current per IGBT 281. On-board cooling systems of mobile platforms.3 V 810. such as aircraft oil cooling.Table 6. Rth is the total thermal resistance from IGBT chip junction to the liquid coolant. Voltage per IGBT 833.1] where Pd is the average power loss. The volume and mass of switches S1 and S2 (including heat sinks and IGBT assemblies) is included in 106 . The junction temperature is found as [6. The heat sink design is based on a flowed water component from Aavid Thermalloy with 0.5 Expected voltage and current per IGBT. [6.002 ºC/W thermal resistance rating for a 0. of parallel IGBTs 3 1 Total modules (2 IGBTs per module) 9 37 S1 S2 Table 6. The thermal resistance ratings of IGBT module cases and heat sinks were used to maintain IGBT junction temperature below 125 ºC with the expected power loss and liquid coolant temperature of 25 ºC.4 Number of IGBT modules in series and parallel for assembly of S1 and S2. integrated with these liquid heat sinks will minimize the size and eliminate a dedicated heat exchanger.3 A 188 A Average turn-off loss 1980 W 5402 W S1 S2 The cooling of the assemblies for the near-term is estimated based on COTS liquid cooled heat sinks. of series IGBTs 6 73 No. No.1] Tj = Pd ( Rth) + Tl .

Bm. The peak flux density must be conserved since the inductor core must operate below the magnetic saturation level of the nanocrystalline core material. the peak flux density. If the inductor parameters are constant. which is shown in Table 6. Ac [6. This method provides an approximate estimate for the projected inductor volume and mass.7.2] where.2]: Bm = Φm . respectively. the relation becomes [6.4π N ⎜ IDC + ⎟ ×10 Φm 2 ⎠ ⎝ = Bm = lg Ac [6. First.3]: ∆I ⎞ ⎛ −4 0. by the following equation [6. respectively. Ac is the core cross section area and Φm is the maximum flux that occurs at peak inductor current. then Bm is proportional to the projected increased inductor current. 300 kW converter design. Since Bm is inversely proportional to the core area and directly proportional to the magnetic flux.the component data for the first and second stage. of the inductor cores is assumed to be conserved from the prototype as the inductor currents are scaled up to 844 A and 188 A from the lesser prototype current levels for L1 and L2. The inductor scaling method uses the second stage inductor dimensions of the 5 kV converter prototype and scales them up for the first and second stage inductors in the 60 kV.3] 107 .6 and Table 6.

The total volume and weight of the inductor can then be scaled as the cube of the change in the length of one side of the core’s cross-section area. is scaled by a factor limited to approximately one-half of the scaling factor for peak inductor current value.5]: SL = ( S). and SI is the scaling factor for the peak inductor currents from the prototype converter. by manipulating N and lg from equation [6.where lg is the air gap length. If the inductor core area. then the approximated scaling relation can be shown in equation [6. SL. Thus. and ∆I is the peak current level [4]. then the length of one side of the core’s cross section is approximately proportional to the squareroot of SA. 2 [6. based upon general inductor and transformer scaling trends [4]. 3 A [6. Bm can remain constant. If the core cross section area has an area scaling factor of SA as shown above.4]: SA = SI . despite increases in the current level. is equal to the following equation [6.3] and the core area Ac from equation [6.5] 108 . which requires a new winding density and longer air gap distance for increased core reluctance.2]. the inductor volume and mass scaling factor.4] where SA is the inductor core area scaling factor. IDC is the DC current level. Ac. N is the number of inductor winding turns. However.

where SA is the scaling factor of one of the sides of the core’s cross-section. and the six series diodes of D2 in the prototype likewise form a 5000 V. The capacitor data was taken from General Atomics capacitor datasheets. The scaled inductor volume and mass of L1 and L2 is shown in Table 6. create the diodes for the 60 kV converter. The volume and mass of D1 and D2 in the 60 kV converter are displayed in Table 6. The two parallel diodes of D1 in the prototype effectively form a single diode module that is used as a model for a 500 V.7. respectively.7. The capacitors used in the 5 kV converter prototype did not provide the baseline for modern technology. arranged in parallel and series. and by using the second stage inductor in the 5 kV prototype as the baseline. The diodes of the 60 kV converter have been scaled based on the diodes of the 5 kV converter prototype.2 g/cc. The dimension scaling factor SL allows for the inductor volume and mass scaling based on the increase of inductor current in the 300 kW converter scaled up from the inductor current of the 5 kV prototype converter. Bm in the first and second stage inductor cores. instead the energy density value of 0. the capacitors for near-term cascade boost converter were estimated based upon the existing energy densities (J/cc) for high voltage capacitors. These diode modules.6 and Table 6. of modern COTS capacitors were utilized for determining the mass and volume of the capacitors in the converter. Finally.47 J/cc and mass density value of 1. This method creates a scaling factor by conserving the magnetic flux density.6 and Table 6. respectively. 10 A diode module. The overall volume and mass was estimated based on these 109 . 50 A rated diode module.

S1 L1 D1 C1 Total in3 421. 300 kW converter.9 1.0 46. the energy stored in C1 (125 µF) is 1.3. The volume and mass of C1 and C2 is shown in Table 6.2 233.422. S2 L2 D2 C2 Total in3 1. The energy stored in the capacitors is found by [6.8 202.0 3.7 5.3 The component volume and mass data are displayed by the component category in Table 6.562. Table 6. 2 [6.9 Table 6. 300 kW converter.volumes along with the amount of energy stored in C1 and C2.0 565.6 233.0 149.2 lbs 150.277.2 10.8 108.8 lbs 41.6 and Table 6.6] 1 Estored = CV 2 (Joules).5 J and the energy stored in C2 (1 µF) is 1.348.800 J.0 13.7 Second stage components volume and mass for the near-term 60 kV.6] where V is the voltage across the capacitors.538.1 8.0 6. The estimated mass of the near-term cascade boost converter shows that the 110 .8.0 96. respectively.6 First stage components volume and mass for the near-term 60 kV. Using the capacitance value shown in Table 6.1 262.7.

3 436. Table 6. 300 kW converter.9 371.0 19.1 lbs 191.switches in the system consume about 50% of the mass.3 18.5 lbs/kW. shielding.2 The total component volume and mass values in Table 6. 300 kW converter using existing technology is approximately 1.2 383. insulation.913.2 445. and the inductors consumes about 38% of the converter mass. and possibly shock and vibration damping.0 3.692.692.9 shows the estimated power density of the near-term 60 kV. accounting for the additional volume and mass of the converter enclosure. Total Component Complete System (20% factor) in3 6. support structure. Table 6.4 lbs/kW 1.9 do not describe a completely packaged and operational 300 kW cascade boost converter.5 lbs 371.1 8.9 Total near-term projected component volume and mass and complete system volume and mass of a 300 kW converter.5 111 .6 6.8 Estimated volume and mass of components of the near-term 60 kV.959.030.0 142. Table 6. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter. The total component volume and mass values have been adjusted by a factor of 20% to estimate a complete converter. control system electronics. Switches Inductors Diodes Capacitors Total in3 1.

Table 6. Research has demonstrated SiC devices will have a substantial impact on switch-mode converters and high voltage power conditioning applications [7-9].10 lists the specific qualities of SiC in comparison to Si. include higher electric field breakdown. higher thermal conductivity. compared to Si. Properties of SiC that make the material so attractive for high voltage semiconductor devices. The SiC devices are known as wide band gap semiconductor devices—the band gap energy of SiC is more than twice as large as Si.2 Five & Ten-year Future Technology Scaling Future technologies such as Silicon Carbide (SiC) semiconductor devices offer the potential for great power density improvement of power conditioning systems. Increased switching frequency and higher voltage handing per device are the leading factors for the following projected reduction in volume and mass of the 300 kW cascade boost converter module. already has shown advantages such as fast switching speed and zero reverse recovery current [5-6]. The 4H-SiC 112 . and higher operating temperature. implemented in the 5 kV cascade boost converter prototype. The band gap energy level affects the semiconductor material operating temperature range and electric field breakdown strength.7 times higher switching frequency than a comparable converter with Si devices [10]. Two polytypes of SiC that are used as semiconductor material: hexagonal 4H-SiC and 6H-SiC. larger saturation velocity. A switch-mode converter using 200 V SiC devices (JFETs and diodes) has demonstrated reduced passive component size and higher power density.6. The 1200 V SiC Schottky diode. which is largely due to approximately 6.

These challenges result in SiC gate structures which have reliability issues and high on-state resistance in the inversion layer.2-2. Devices that do not use MOS control. which includes a higher band gap and higher electron mobility. The ten-fold reduction in thickness of the voltage blocking layers allows for a proportional reduction in the diffusion length of injected minority carriers. The SiC devices also offers thinner 113 . Si 1. BJTs and other minority carrier devices can theoretically exhibit approximately 100 times faster switching speed than equivalent Si devices [16]. to be nearly eliminated. such as the BJT. Apparently. such reduction in carrier lifetime impacts the effect of the current tail at turn-off.12 ev 300 kV/cm ~ 1. SiC BJT devices have recently been demonstrated [15]. High voltage.9 ev 4000 kV/cm ~ 5 W/cm-˚C ~ 2x107 cm/s 300˚C The first generation of high voltage SiC devices used may not be IGBTs or MOSFETs.however is more commonly employed than 6H-SiC. Band Gap Energy Electric Field Breakdown Thermal Conductivity Saturation Velocity Max Junction Temp. gate oxide issues and low channel mobility coupled with material science issues are the major challenges for high power SiC MOS controlled devices. This is due to SiC’s 10 times higher electric field strength. instead SiC BJT power switching devices may enter the market first [11-14]. eliminate such problems.5 W/cm-˚C ~ 1x107 cm/s 150˚C 4H-SiC 2. and the shorter diffusion length reduces the carrier lifetime to 100 times less. As discussed in Chapter 3.10 Properties of SiC that will enhance power semiconductor devices.1 times as thick. which allows voltage blocking layers to be made 0. Also. Table 6.

114 . implemented in the cascade boost converter. voltage controlled MOS SiC devices will be the next standard for solid state power devices. will achieve voltage blocking ratings of 5 kV. becomes a strong candidate for the first generation of commercial high voltage and high power SiC switching. provides a technological basis for an estimated size and weight reduction of the 300 kW cascade boost converter. Reevaluation of the cascade boost converter using future SiC technology. Therefore these estimates are based on demonstrations. projected for the time range of 5 and 10 years. estimating the trend of SiC devices is highly unpredictable. The voltage ratings and switching frequencies for these devices in 5 and 10 years have been estimated. However. and avoidance of problematic MOS control issues. The 10-year trend estimate is that 8 kV ratings will exist per SiC device. with fast switching. as SiC represents a new paradigm in semiconductors that is currently very young.11. the SiC BJT may also share the same trend as the Si BJT ancestor. and projections found in published literature of SiC research and development efforts [7] [10] [17-19]. high beta. and the switching speed will be increased to 70 kHz. However. and can only represent a hypothesized technology projection. simulations. The following 5-year trend estimate is that SiC devices. The future SiC BJT. and the switching frequency will be increased to 100 kHz. Ultimately. with technical solutions of the aforementioned SiC material science challenges with SiC. which allows SiC BJTs to operate with higher current gain (beta) for reduced base drive current to control the device. A summary of the projected key parameter estimates are shown in Table 6.base regions than Si.

which scale inversely proportional to the switching frequency. Subsequently. or 14. which has been assumed to be equal to the near-term average switching loss displayed in Table 6. The ideal inductor derivation in Chapter 2 indicates the linear relationship with the switching frequency. This increase in switching frequency will reduce the volume and mass of the inductors. the first stage inductor volume and mass has been scaled for the 5-year trend to be one-seventh. This advance in capacitor technology and the increase in switching 115 . Likewise. the energy storage requirement reduces linearly with the capacitance in the 5 and 10-year time frames according to equation [6. and 1% of the near term.3%. for the 5-year trend. based upon reports in published literature [20-21].7% of the near term. the average power loss in the semiconductor devices for all three time frames will be assumed constant. However.5. Also. respectively. energy densities of 1 J/cc and 5 J/cc are anticipated to be available in the 5 and 10-year terms. of the first stage inductor in the near-term because of the seven times switching frequency increase. The reduced energy storage requirement. result in dramatic size reduction of the capacitors. the switching frequencies for the two time frames are assumed to be limited by average switching power loss.The faster switching ability of the SiC devices allows the converter to be operated at the higher switching frequencies. The first and second stage output capacitors of the cascaded boost converter reduce to the resultant volume and mass of approximately 6. Thus. the capacitance value required for the first and second stage filter capacitors will reduce linearly with the increase in frequency according the derivations in Chapter 2. for the 10-year trend. For instance.6]. compounded with future high energy density dielectric technology.

based on the literature available on advanced cooling methods. the average power loss. The first and second stage switch volume and mass are linearly scaled based on the number of devices.12. The number of devices to be used in series and parallel for the first and second stage switch assemblies. on an individual device basis.frequency reduce the first and second capacitors down to the size of circuit board mountable components. 5-year (5 kV rated devices) Series Parallel 2 3 20 1 26 devices 10-year (8 kV rated devices) Series Parallel 1 3 10 1 13 devices S1 S2 As discussed above.12 Number of devices to be placed in series and parallel for the 5 and 10-year time frames for the 300 kW converter’s first and second stage switches. However. the average switching loss in the 5 and 10-year estimates will remain equal to the near-term switching loss although fewer devices will be implemented. is shown in Table 6. an estimation of future advanced cooling technology will allow for a favorable scaling of the thermal management hardware. relative to the number of devices in the near-term switch assemblies. Voltage rating per device Converter switching freq. The higher voltage capability of SiC devices will reduce the necessary number of devices in series for each switch stack assembly. The near-term switching assemblies have been designed with 116 . 5-year 5 kV 70 kHz 10-year 8 kV 100 kHz Table 6. in the 5 and 10-year assemblies.11 Summary of the key parameter estimates for SiC devices in 5 and 10 years. Thus. for the two time frames. will increase. Table 6.

on-chip cooling has been pursued for densely packed. with lower heat flux than advanced technologies. of the 300 kW converter’s cooling system volume and mass. which reduces the required thermal resistance of the cooling system by a factor of 2. For instance. the near-term estimate uses IGBT modules with standardized industrial packaging. bulk-aluminum heat sinks. Therefore. is assumed to be linear in relation to the number of switches in the 5 and 10-year time frames. the total switch assembly volume and mass will be directly related to the reduction of the number of switches and diodes. which have been primarily motivated by the thermal management needs of high performance server CPUs. Integrated. high performance IC’s for highly efficient heat extraction [22]. Furthermore. 117 . VLSI devices. since there will be one-third the number of devices in the assembly as in the near-term. or one-third of the mass of the same assembly in the near-term. Finally.conventional water cooled. High heat flux removal from micro-channel systems for local heat extraction has shown the ability to remove to up to 500 W/cm2 in local hotspots [22].7 lbs. and high-density power electronics. The approximated scaling. the typical maximum junction temperature of SiC is approximately double the maximum junction temperature of Si. Future heat flux may reach 1000 W/cm2 with the optimization of multi-phase fluid flow within micro-channels for a number of future systems [23]. the first stage switch design in the 5-year trend will have a total mass of 13. Customized packaging with integration of the cooling system within the device package can eliminate the contact resistance between the IGBT base plate and the heat sink.

118 . and possibly shock and vibration damping.Table 6. the 20 % accounts for the additional hardware that may include the converter enclosure. support structure.17 give the estimates for the final system for the 5 and 10-year trends including a 20% factor for additional volume and mass for a fully packaged and operational converter. Table 6. control system electronics.15 shows a breakdown per component of the cascade boost converter in the 5 and 10-year trends.16 and Table 6. shielding. insulation.13 and Table 6.14 show the first and second stage component volume and mass for the 5-year and 10-year technology trend estimates. As with the near-term converter estimate. Table 6.

119 .15 Estimated total volume and mass of each component category in a 60 kV.6 281.14 Second stage component projected volume and mass for the 5 & 10-year trend in a 60 kV.0 99.8 in 209.3 0.2 0.1 Table 6.7 57. 300 kW converter module.7 559.8 20.249.3 1.3 5-year lbs 54.8 Table 6.2 56.7 725.6 23.3 80.7 46.4 14.2 29.5 15. 3 5-year lbs 41.8 13.7 6.6 1. 300 kW converter module.7 S2 L2 D2 C2 Total in 421.9 391.4 in3 70.1 in3 280.16 5-year total projected component and complete system volume and mass for a 60 kV.6 1.9 3 10-year lbs 20.9 152.6 0.3 4. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter.13 First stage component projected volume and mass for the 5 & 10-year trend in a 60 kV. 300 kW converter module.3 52.5 23.0 10-year lbs 6. S1 L1 D1 C1 Total in3 140.1 0.1 31. 300 kW converter module.2 2.2 2.Table 6.4 5-year lbs 13.9 10-year lbs 27.3 49.4 1. Switches Inductors Diodes Capacitors Total in3 561.6 2.1 13.1 12.4 478.8 4.4 9.2 573.7 334.3 81.4 1.8 26.8 1.7 967.9 44.1 Table 6.6 43.7 2.

4 MW power output.0 Lbs/kW 0.9 871. where four 300 kW converters are paralleled for the 1.4 MW system.2 MW output and eight are paralleled for the 2.1 97. 10-year scaled Total Component Packaged System (20% factor) in3 725.32 Table 6.1 53.1 and Figure 6.17 10-year total projected component and total system volume and mass for a 60 kV.2 respectively. The compact and lightweight potential of the cascade boost converter design enables mega-watt class power support for applications such as gyrotrons aboard mobile platforms.18 The volume and mass trends for a 300 kW converter in the near-term and for the 5 and 10-year projections are displayed in Figure 6.5-year scaled Total Component Packaged System (20% factor) in3 1. The scaling indicates the potential of multi-megawatt class conversion under 500 lbs. where the projected technology advancements in high voltage semiconductor devices can greatly increase the power density of high power conditioning systems.499.3 and Figure 6. 300 kW converter module.2 MW and 2. The mega-watt class power converter shows an attractive scaling profile. 120 .4 display the significant mass reduction trend for a 1.3 1.1 lbs 44.1 lbs 81.249.3 Lbs/kW 0. Figure 6. The 20% scaling factor estimates additional volume and mass for a completely packaged and operational converter.

2 300 kW converter mass scaling from estimated technology trends.031 1.000 1.000 2.000 Volume ( In 3 ) 6.000 4.000 3. 121 .000 5.499 871 10-year Figure 6.000 8.000 7.Volume Scaling of a 300 kW Converter 9.1 300 kW converter volume scaling from estimated technology trends.000 0 Near-term 5-year 8. Mass Scaling of a 300 kW Converter 500 445 400 Mass ( Lbs ) 300 200 97 100 53 0 Near-term 5-year 10-year Figure 6.

400 2.Volume Scaling of a 1. Volume ( In 3 ) Mass Scaling of a 1.244 1.2 & 2.2 MW Mass 2. 122 .484 10-year 11.2 and 2.2 MW Vol Figure 6.563 1.4 MW Converter 4.4 1.122 20.000 2.4 MW Mass Figure 6.997 5-year 6.000 80.2 and 2.000 32.4 MW converter volume scaling using parallel 300 kW converter modules.000 1.781 3.2 & 2.969 3.3 1.000 0 Near-term 5.000 40.4 MW Vol 100.000 60.000 3.200 800 400 0 Near-term 5-year 389 779 424 212 10-year 1.993 64.800 Mass ( Lbs ) 2.600 1.4 MW Converter 120.4 MW converter mass scaling using parallel 300 kW converter modules.200 2.600 3.

“1 MHz hard-switched silicon carbide DC/DC converter.P. New York: John Wiley & Sons. 969986. 1964. [11] A. Power Semiconductor Devices and ICs. 589-597. Wang and B. on Power Electronics. Elasser and T. A. A. “Low Turn-off Switching Energy 1200V IGBT Module.” IEEE Electronic Device Letters. vol.R. 2165-2169.” IEEE Trans. June 2002. 2004. on Industry Applications. Cooper “SiC Power-Switching Devices—the Second Electronics Revolution?. 132-138. 956–968.” IEEE Trans. 2003. Williams. [12] Yanbin Lou. Nov.” in Proc. ED-90. “Evaluation of high-voltage 4H-SiC switching devices. “Silicon carbide benefits and advantages for power electronics circuits and systems. vol. pp. Power Electronics. J. 1249-1253. “High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base. “A comparative evaluation of new silicon carbide diodes and state-ofthe-art silicon diodes for power electronic applications. 2004. Agarwa. pp. 2003. pp. Industry Applications Conf. vol. pp. July-Aug.” IEEE Trans. Chow. [2] [3] [4] [5] [6] [7] [8] [9] [10] Abou-Alfotouch.REFERENCE FOR CHAPTER 6. Wm. Inc. T. McLyman. “Performance evaluation of a Schottky SiC power diode in a boost PFC application. New York and Basel: Marcel Dekker.” Proceedings of the IEEE. “The latest advances in industrial IGBT module technology. pp. Yamada. 2002.0 [1] E.” in Proc. pp. Motto and J.. ED123 . N. 235-240. G.” Proceedings of the IEEE. Applied Power Electronics Conference and Exposition.” in Proc. ED-18. 2003. ”Recent progress in SiC bipolar junction transistors. Donlon. J.K. 1995. J. 2nd Edition.” in Proc. vol. 915-921. ED-39. June 2002. vol. A. vol. pp. 361-364.. pp.W.F. ED-46. March 1999. Mohan. on Electronic Devices. Magnetic Core Selection for Transformers and Inductors. Applied Power Electronics Conference and Exposition. Elasser. ED-90. pp. Spiazzi.

vol ED-40. May 2004. 2003. pp. vol ED-19. pp. pp. 32. vol. [21] M.” IEEE Trans. on Power Electronics. 2211-2216. pp.W. 2004.V.4. “1800 V NPN bipolar junction transistors in 4H-SiC. 2004. 223-230. 1. Nov. Electron Devices Meeting. [14] R. McDougal. “Ultracompact Pulsed Power. [16] T. pp. 2535-2543. Dec. [19] P. 1065-1076. Johnson.” in Tech Digest IEEE Int. Huang. [20] F. 1381-1382. 1197-1204. 92. 695-697. pp. Lou.a role for wide bandgap semiconductors?. [17] A. [22] G. “Comparison of silicon and silicon carbide semiconductors for a 10 kV switching application.24.Q. “Demonstration of first 9. Oct. “High-temperature electronics .G. vol ED-48. 2003. vol.R. Neudeck. 2004. Sei-Hyung. March 2001. 124 . ”Silicon carbide PiN and merged PiN Schottky power diode models implemented in the Saber circuit simulator.M. pp.” IEEE Trans.” in Proc. McNutt. “Fabrication and characterization of high current gain (Beta =430) and high power (23a-500V) 4H-SiC Darlington bipolar transistors. [23] D. ED-51. Upadhya. 2003. [13] Y. vol. 2003.2 kV 4H-SiC bipolar junction transistor. vol.” in Digest of Technical Papers of Pulsed Power Conf. Power Electronics Specialists Conf. [15] J. IEEE Semiconductor Thermal Measurement and Management Symposium. 572-578. [18] C. on Electronic Devices. 2001.” in Proc. “Closed-loop cooling technologies for microprocessors. 513-517. 573-581. July 2004. on Electronic Devices.” IEEE Electronic Device Letter. June 2003.” IEEE Electronic Device Letters. June 2002.4. pp.. 124-126. Fazio. Faulkner. ED-90.1 .” Proceedings of the IEEE. pp. “Practical design of a 1000 W/cm2 cooling system. pp. vol.32.” IEEE Trans.” Proceedings of the IEEE. pp. Nov. pp. “High energy density pulsed power capacitors. 19th Annu.4. Zhang. ED-22.. “The future of bipolar power transistors.

with optimization of series and parallel arrangement. Chapter 3 presented a discussion on IGBT switching considerations. which resulted in a lower prototype efficiency of 37%. with respect to the voltage rating of the IGBTs. DC-DC conversion through a prototype cascade boost converter. Six series. further research on semiconductor devices. where the application of IGBTs must take into consideration switching loss. 1 kW output from a constant 100 V input at an efficiency of 76. The equations derived.6%.0 CONCLUSION This work has provided the design of the cascade boost converter topology. and testing of the prototype cascade boost converter by producing a 5 kV DC. enabled a 76. as the second stage switch. which has been experimentally demonstrated as a viable converter for high step up ratio. The cascade boost converter topology has been shown to have very attractive scaling trends in response to these technological advances for the 5 and 10-year projections.6% total prototype efficiency. the switches and inductors appear to be the leading sources of power loss in the converter. successfully enabled the design. The cascade boost converter prototype was designed based on the theoretical converter work as described in Chapter 2. As discussed in Chapter 5. After the circuit analysis of the prototype. Furthermore. will likely extend high voltage 125 .3 kV rated IGBTs. 1200 V rated IGBTs implemented for the second stage switch. high voltage.CHAPTER 7. the power density of high voltage power conditioning systems will drastically increase. fabrication. with the fruition of anticipated high voltage silicon carbide power devices and high energy density capacitor dielectrics. and was compared to two series 3.

2 MW system. 5-year. 300 A device that exhibits low turn-off loss. For instance. dedicated inductor optimization may reduce copper winding and magnetic core hysteresis loss of the first and second stage inductors. which has been based on testing of the cascade boost prototype converter. The diodes have been estimated by scaling the necessary number of diodes in series and parallel to accomplish the diode parameters for the higher voltage and power level. in the 60 kV converter design. scaled up from the prototype converter. An efficiency reaching 90% may likely be realized with dedicated component optimization and circuit fabrication. Chapter 6 discusses estimated volume and mass of a converter scaled to 60 kV and 300 kW in the near-term. Also.capability and mitigate switching losses in future designs of the cascade boost converter. The 10-year converter estimation shows a potential for a 300 kW system volume under 1. is a 1200 V.000 in3 and approximately 53 lbs. Using the assumption that 90% efficiency is possible. The inductors were scaled based on the core cross sectional area required to prevent magnetic flux saturation in the cores due to the peak inductor current. scales to approximately 126 . four converter modules assembled in parallel for a 1. and 10-year time frames have been estimated. and 10-year time frames. Parallel 300 kW modules can be utilized to fabricate multi-megawatt class converters. 5-year. system scaling in Chapter 6 for a 60 kV and 300 kW converter for the near-term. The scaling uses the basic series and parallel switching concepts implemented by the prototype cascade boost converter. and has been optimized to mitigate the current tail by using Light Punch Through technology. The COTS IGBT module used for the first and second stage switch assemblies.

Such power density advances will allow power conditioning systems to satisfy volume and mass requirements for such military applications. weapon systems.000 in3 and a mass of 424 lbs.500 in3 and 212 lbs. remarkable by any system standards. and pulsed power systems for the military can be operated on land vehicles. 127 . and a 2. aircrafts. such as mobile platforms. which allows for high power conditioning systems to be integrated onto platforms that are impractical today.4 MW system will proportionally have a volume of 7. and possibly man-portable systems given this technology trend. The cascade boost converter shows that reduction by 88% in weight may be achievable in a 10-year time frame. High energy lasers.3.

power oscillator. displays the six fiber optic transmitters (HFBR1521).1 through Figure A. The gate driver boards are powered by the power oscillator shown in Figure A. the fiber optic receiver (HFBR2521) is coupled to the main gate driver IC (MIC4451) that provides +15 V for turn-on and 0 V for turn-off with the capability of 12 A peak drive current. synchronized with the 50 Ω trigger TTL input signal. and each IGBT is overvoltage protected by a series of six transient voltage suppressor diodes (D10-D15) that provide a clamping voltage of 1200 V for the IGBT collector to the emitter voltage. 1200V rated. 128 .3. IGBTs that is used in the second stage of the cascade boost converter prototype. respectively show circuit schematics of the trigger module. Figure A. shown in Figure A. where the secondary winding of T1 couples to a magnetic core (CST206-1A) on each IGBT driver board. and gate drive circuit in the IGBT stack of six individual.APPENDIX A Drive Circuit Schematics of the Second Stage IGBT Stack Below. a 4.7 Ω external gate resistor is in series with the IGBT (IRGP30B120KD-E) gate input. using a single loop of high voltage insulated wire that is strung through each driver board. On each gate driver board. in Figure A. The IGBT trigger module.3. Also.1.2. that send optical signals to each IGBT gate driver board.

2 Power oscillator. Figure A.Figure A. 129 .1 IGBT trigger module.

3 IGBT gate driver circuit.Figure A. 130 .

m. Integratecsv. Column “B” is numerically integrated with respect to column “A”. x = M(:. the result will be the integral of the data. When implemented in MATLAB. M = csvread(csvfile).x). Intgrl = Y(end). 131 .1). Y = trapz(t.csv') %integratecsv numerically integrates a csv file (comma sep var) where %column B is integrated with respect to column A.2).APPENDIX B MATLAB function integratcsv.csv) file. This routine integrates waveform data saved as an array in a comma separated variable (. The routine is specifically designed to open a file with two columns of data. t = M(:. where column A may represent time values and column B represent waveform data.m is shown below: function Intgrl = integratecsv(csvfile) %integratecsv('directory path\filename.

068 ⎜ ⎟ ⎜ ( DT ) ⎟ . vf. L is the inductance. The conduction current is given by [C.1.1] and [C. The solution for the power is integrated to give the energy loss during the on-state per period and multiplied by the switching frequency. The on-state voltage. L ⎝2 ⎠ ⎝ L ⎠ ⎝3 ⎠ 2 [C. L [C. which provides the average conduction power loss.3] Pcond (t ) = 0.068 ⎜ t ⎟ .068 VL t.1] Icond (t ) = VL t + Iinitial .2] results in the power equation: [C. L [C.4] 132 .4] DT Eon = ∫ 0 VL ⎛ 1 2⎞ 3⎞ ⎛ VL ⎞ ⎛ 1 Pcond (t ) =0.3] Integration of Pcond.APPENDIX C Derivation of the IGBT conduction power loss The conduction power loss of the IGBTs is found by multiplication of the on-state current and voltage for a single period during stead state operation.2] vf = 0. results in the conduction energy loss per period: [C.7 ⎜ ( DT ) ⎟ + 0.7 VL ⎛ VL ⎞ t + 0. of the IGBT is approximated as [C. Multiplication of [C.7 + 0.2] which was determined from on-state forward conduction test shown in Figure C. L ⎝L ⎠ 2 [C.1] where VL is the voltage across the inductor. and Iinitial is zero if the boost converter is in discontinuous mode conduction.

Non-Punch Through (NPT).5 V 40 Amps 30 Vf data 20 10 0 0 1 2 3 Vf 4 5 6 Poly.1 Experimental on-state forward conduction voltage and trend line of the International Rectifier IRGP30B120KD-E 1200 V.5] On-State Forw ard Voltage Data & Trendline 60 50 Vg = 12. The average of Pcond(t) equals the Eon multiplied be the switching frequency: [C.5 V. (Vf data) Figure C. 133 .5] Pcond = fswEon = 1 Eon . IGBT. T [C.where the integration limits are from the beginning of the period to end of the switch ontime. 60 A rated. DT. Vg = 12.

The result of the routine is the calculated RMS value of the data. The routine is specifically designed to open a file with two columns of data. This routine calculates the RMS value of data saved as an array in a comma separated variable (. The time duration of the data must be equal to one period of a periodic waveform.csv) file. x = M(:.x. Y = cumtrapz(t.m. t = M(:.APPENDIX D MATLAB function RMSCalc. Irms = sqrt(Y(end)/T).^2). where column A may represent time values and column B represent waveform data.1). 134 .m is shown below: function Irms = rmscalc(csvfile) %rmscalc('directory path\filename. M = csvread(csvfile). %First and last data point in the CSV file define the period of a repetitive waveform. particularly from a Tektronics oscilloscope. T = max(t)-t(1). RMSCalc.csv') %rmscalc calculates the RMS value of a waveform in a CSV file.2).

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