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Optimized approach
Graph-theoretical algorithm
Euler Path for Optimal Layout
Developed by Gregory, 2004
Modified by Li Chen, 2013

©Gregory Holder 1 ©Gregory Holder 2

Optimized approach (Euler Path) Two Versions of C • (A + B)1
(Observe the input order)
• The Euler path technique has
been used in what is called the
“standard cell technique”,
which results in a dense layout
for CMOS gates and one
polysilicon strip that can serve
as the input to both NMOS
and PMOS devices.
• Our main aim is to have a
single strip of diffusion in both
NMOS and PMOS devices.
This depends on the
“ordering” of the inputs. How
do we determine the best

©Gregory Holder 3 ©Gregory Holder 4


i PDN • Euler paths must be consistent (same ordering in both A B A B C GND PUN (pull up network) and PDN (pull down network). edges in Euler path. any circuit will have a single contribute to separation area. edges on the Euler path. 5) Delete “Pesudo” edges in parallel and contacting “pseudo” edges in series with other edges for final circuit. If more than 2 edges are such that the sequence of according to the vertical order of edges on an Euler path inputs on logic diagram. minimum number of Euler logic structure we achieve the 1) The following example and 2) The “pseudo” input does not paths that cover the graph. B C ©Gregory Holder 5 ©Gregory Holder 6 The General Algorithm Heuristic Algorithm (of course life not being so easy) The Heuristic Algorithm 1. Inaddition. ©Gregory Holder 7 ©Gregory Holder 8 2 . Enumerate all possible • Therefore for the previous Theorem: 1) To every gate with an even consistent Euler path for the number of inputs add a “pseudo” decompositions to find the input. This is defined as the path through all B nodes or vertices (source and drain signals) such that X i VDD g ( transistor g each edge( gate inputs) p ) is onlyy visited exactly y X = C • (A + B) once. then provide a means of diffusion areas as separation area between each order of the inputs on a planar representation of the indicated by the sequence of pair of chains. “pseudo” and real inputs. necessary to cover the graph corresponding to the vertical 4) Chain together the gates by model. A • Can Run in linear time3. 10/1/2013 Graph the theoretical approach Consistent Euler Path1 X • To reduce the size of an array and an uninterrupted PUN diffusion strip we need to find this “Euler path” talked A C j C about previously. (vertices maybe visited more than once). optimal layout below. Chain by means of diffusion inputs to every AND/OR a minimal combination between area according to the order of element is odd. A logic diagram. But Euler path if the number of this input is added so that there is 2. path 2) Th There exist i t a graph h model d l 3) Construct the graph model 3. C B j A • Euler paths are not unique. “pseudo" input gives a separation between diffusions.

For our (p1. ©Gregory Holder 9 ©Gregory Holder 10 Analysis Analysis (continued) 1. It must be noted that the Here in (b) we see the final heuristic algorithm may not always give the optimal Euler Path interpretation layout but if the resulting sequence. 2.2. This is Illustrated in the four-bit carry look-ahead adder3 circuit shown in this slide. The heuristic gives excellent results for circuits which do not have a Euler path. if no the corresponding circuit separation areas are diagram (c) and the a final obtained then this is the optimal solution. the derived example and we obtain the Euler Path (c) and the following sequence corresponding Layout. and the remove the “pseudo” pseudo inputs PDN -----.1.4. 10/1/2013 Example Heuristic Works We apply our Heuristic We consider the following logic approach to the previous Circuit (a and b).5. ©Gregory Holder 11 ©Gregory Holder 12 3 . However. (Note we choose the combination with the minimum interlaced with real inputs) hence circuit (b). to get the same layout previously shown in slide 11.p2) where we Euler path the PUN.3. layout.

and Vancleemput. “Hewlett-Packard Journal. 10/1/2013 Conclusion References • This Presentation has given a brief incite into 1. algorithm. “Silicon-on Sapphire Technology of power and performance of a particular Produces High-Speed Single. Forbes. E.pp 2-8. The results show that by use of this 3. Uehara. in our layout. B. Digital integrated circuits 2nd edition optimizing the layout of complex CMOS gates. April 1977. 2.Chip Processor. M “optimal Using the Euler path approach and a heuristic layout of CMOS Functional Arrays”. W. ©Gregory Holder 13 ©Gregory Holder 14 4 . Further work can be done to simulate the “real” gain of this method in terms 4. Robert Sedgewick “Algorithms Algorithms in C third approach h we can optimize considerably d bl on area edition”. T. design.