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Unit-1

Computer System

1. CPU: controls operations, reads and executes instruction, stores the results, has Arithmetic
logic unit (ALU). CPU generates consecutive address to fetch information from memory, the
program counter. Can also hold the data temporarily in registers.
2. Memory - For data storage. Semiconductor memories store data as long as power is
available; magnetic memories can hold the data even in the absence of power.
Semiconductor memories can be ROM, the read only memory or RAM Random access
(read/write) memory.
3. I/O: Is the interface for the outside world. They are slow compared to CPU and memory,
and work asynchronously. IO devices typically use hand-shake signals for communications
Computer System
Address Bus: Used to access a unique location in memory (or I/O). CPU
sends out address of location from where it needs to access the data.
With n lines in the address bus CPU can access 2n address locations
Data Bus: These lines are used to carry data between CPU and devices
(memory and/or I/O). To ensure only one device responds to a specific
address, devices connected to data lines should have tri-state outputs.
With m data lines, we say it is m-bit CPU
Control Bus: CPU informs devices what to do (Ex. read or write) on these
lines. All the synchronization and hand-shake operations (signals) are
carried out by the control bus.
Typically, address and data bus are similar in all the CPUs. Variations
occur in the control bus.
Hardware is the physical device; software consists of programs, typically
resides in RAM; Firmware brings up the board and resides in ROM

Execution steps

1. CPU sends out the address of the instruction


2. CPU asserts READ signal
3. CPU Reads the instruction
4. CPU decodes instruction
5. CPU estimates address of operand
6. CPU sends out the address of operand
7. CPU Reads the operand
8. CPU operates on the operand
Depending on the type of instruction execution
sequence and steps might vary
Types of task execution
Batch processing: Jobs are partitioned; each part is completed
one after the other. Typically punched cards
Multiprogramming: Execute next task while CPU is waiting for
the some data
Timeshare: Multi-tasking - Divide available time among
processes. Allocate a time slice for each process
Distributed processing: Distribute the task among multiple
computers.
+ Fault tolerant +More tasks (quicker) + Efficient usage of resources.
-Synchronization -Load balancing
UC and uP

Microprocessor Microcontroller
Only CPU CPU + Memory + IO
General purpose Specific application
Higher clock speed Lower clock speed
Multi-tasking Single (of few) task
Higher power consumption Lower power consumption
Used in PCs Used in embedded systems
8086 Internal architecture

Look at the internal diagram here :


https://3.bp.blogspot.com/-n8scsmId8Z4/TWEYxhvWRcI/AAAAAAAAAGg/_WcfFnb6sGs/w1200-h630-p-k-no-nu/8086+-block+diagra
m.JPG

1. BIU (Bus Interface Unit) - Sends out address, fetches data(or instructions) and
writes back the result to the memory. The BIU can work asynchronously with
respect to the EU.
a. The Queue - CPU can pre-fetch (upto) 6 instructions (bytes) from memory and
store them in the BIU. This can be done in parallel with instruction execution in
the EU. Whenever EU wants an instruction, it can fetch the instruction from the
queue. This will be faster compared to fetching the same from a memory
location. Queue will be flushed out during a branch operation.
b. Segment registers: They hold the base address of four (independent)
segments. Segments helps to isolate different types of information (code,
data, stack) in the memory. We can configure the segment to be distributed
anywhere in the memory range. Segments can overlap or share a location too
c. Instruction pointer - Holds the 16 bit offset of next instruction, within a code
segment

8086 Internal architecture


1.Execution Unit: Fetched instructions are fetched and executed in this block. It
has general purpose registers, flags, control unit and ALU
2. Control system generates appropriate signals to carry out specific tasks.
3. General Purpose registers: Register L and H can hold 8-bit values
independently, whereas X can hold 16-bit value. Though all the registers are
general purpose, specific they can be used for specific task
1.A:Accumulator. Good number of Arithmetic and logic operations are performed using this
register. AX for 16 bit operation and AL for 8 bit operation
2. C:Count - CX is used to hold count value, a down counter will count down from n to 0
3.D:Data - It has dual role. During I/O operations, it holds the I/O address. During
multiplication(16bit16bit) and division(32bit/16bit), it is used to hold higher 32 bits (lower
16 bits will be in AX)
4.B:Base - Used to hold the base address during look-up table operation
5.SI: Source Index - Used to hold address of source array
6.DI:Destination Index - Used to hold the address of destination array
7.SP: Stack pointer
8.BP:Base pointer - used to access the data within stack
Flags
Flags - 8086 has 16 bit flag register. It can be
divided into conditional and control flags.
Conditional flags are set/reset depending on
arithmetic or logic operations; they (typically) do not
alter the program execution sequence. Control
flags (shown in italics in the figure below) can be
set by the user to alter flow of program execution.
The lower 8-bits are the same as that of 8085 flags.
Flags:
U U U U OF DF IF TF SF ZF UF AF U PF U CF
Flags
i. CF : Carry Flag - set whenever we get carry out of MSB (bit 7 for 8 bit
operation and bit 1t for 16 bit operation)
ii. PF : Parity flag indicates the (odd) parity after arithmetic or logic operation
iii. ZF : Zero flag - If the result is zero, after arithmetic or logic operation, this
flag is set, else reset
iv. SF : Sign flag - is the same as MSB after arithmetic/logic operation
v. AF : Auxiliary carry flag- used fo 8-bit BCD operation. After addition, if
lower nibble of AL is >9 or if AF=1, 06 is added to AL; if higher nibble is >9
or if CF=1, 0x60 is added to AL
vi. TF : Trap flag - Used for single stepping operation.
vii. IF : interrupt flag - used to enable(=1)/disable(=0) interrupt (INTR)
viii. OF : Overflow flag - If there is overflow from an operation (bit 7 for 8 bit
and bit 14 for 16 bit operation) , this flag is set
ix. DF : Direction flag - Used to control SI and/or DI during string operations.
If DF = 0, SI and/or DI will automatically be incremented and if DF = 1, SI
and/or DI will automatically decremented
Programming 8086
Machine language: Binary form of program. CPU
can read and execute it. Very difficult to code
Assembly language: Uses simple short forms(Called
mnemonics) for instruction. An assembler converts
them to binary code. Standard assembly language
has fields Label,opcde,operand,comments
Generates optimal code
Not portable CPU specific
High level language More english like. Compiler
will convert it to binary code.
Easy, flexible, portable -machine (CPU) independent
Non-optimal code
Addressing modes
It is the way data is accessed from source (location).
1 Register Data is in one of the registers MOV AX,BX
2 Immidiate Data follows instruction MOV al,0x12
3 Implied Does not require data or source is assumed.
Ex. CMC (complement carry) and DAA
4 Memory addressing When the data is in memory,
accessing it requires differnt addressing modes.
We shall use MOV instruction to illustrate memory
addressing.
5 Direct Address of the operand(Data) is specified
directly along with instruction
MOV AX,[1234] ; Load contents of memory location 1234 to AX
Memory addressing modes
1.Register indirect/Base: Base register (BX) holds address of
operand MOV AL,[BX]
2.Indexed: Index register (SI or DI) will hold the address of
operand MOV AL,[SI]
3.Base Relative: An offset is added to Base register (BX or BP)
to generate the address of operand. Ex. MOV AL,[BP+6]
4.Index relative: Similar to 3, but uses Index registers (SI/DI)
5.Base-Index: Address of operand is calculated as sum of
Base (BX/BP) and Index(SI/DI) register.
Ex. MOV AL,BX+DI]
6.Base-Index with offset: Address of operand is calculated as
a sum of Base + Index + offset. Ex. MOV Al,[BX+DI+0x0a]
Unit-2
Instruction set and assembly language
programming
Ref. Douglass Hall (2nd Edn.) Chapters 3 and 6
2. Instruction Set
8086 can operate on either 8 bit or 16 bit values.
However, both source and destination registers
should be of the same size. Moreover either sorce or
destination should be register. We can not have both
source and desination as memory (Exception exists)
2.1 Data Transfer group
These instruction move (or transfer) data from source to
destination . Flags are not affected after this instruction
1. Mov dst,src ; movecopy data from source to destination
2. PUSH src ;Store content of SRC on to stack (decrement stack by
2 and copy contents of SRC on stack)
3. POP dst ; reverse of PUSH. Copy the contents from stack on to
the desination (Copies top-of-stack on to desination and
increment stack by 2)
4. XCHG d,s ; contents of source and destination are exchanged
5. XLAT ; Translate. Used for lookup table. AL <-- [BX+AL].
Contents of BL are not altered
6. LEA; Load effective address. Loads the (effective) address of the
operand
7. PUSHF/POPF; Push and Pop Flags
2.2 Arithmetic Group
Typically uses accumulator as one of the operand.
Most of the flags are affected
1. ADD d,s ; d<- d+s
2. ADC d,s; Add with carry d<- d+s+CF
3. SUB d,s; d<- d-s
4. SBB d,s; sub with borrow d<- d-(s+CF)
5. INC src; src<- src++ CF not affected
6.DEC src ; src <- src-- CF not affected
7.NEG src; negate 2's complement src<-src* + 1
2.2 Arithmetic Group
8. CMP d1,d2 compare (d1-d2) affect the flags; if d1=d2,
ZF=1, if d1<d2 CF=1 if d1 > d2, ZF=CF=0
9. DAA: Decimal adjust accumultator. Used for decimal
addition. Works with AL only. If lower nibble of AL (bits 0-3)
are greater than 9 or of AF=1, AL<-AL+06. After that if higher
nibble of AL (bits 4-7) are >9 or if CF=1, AL<- AL+0x60
10. DAS: Decimal adjust for subtraction. Similar to DAA, CF
acts as borrow
11. AAA: ASCII adjust after addition. Converts ASCII No. to
unpacked BCD. AL will have BCD value(CF=1). May want to
OR with 0x30 to get ASCII value
12. AAS: ASCII addjust for subtraction. Similar to AAA, CF
acts as borrow
2.2 Arithmetic Group
13. MUL src; multiply accumulator with source. For 8bit
multiplication, result will be in AX. For 16 bit operation, result
will be in DXAX (DX higher word and AX lower word). If
MSB=0, CF=OF=0. AF,PF,SF and ZF are undefined
14. DIV src; Divide acculator (numerator) by source (the
denominator). For 16 bit / 8 bit, AX holds numerator. AH will
have reminder and AL will have quotient. For 32 bit/16 bit
DXAX holds numerator. DX will have reminder and AX will
have quotient. Might generate divide by zero
interrupt(Exception)
15. CBW: Convert byte to word. Uses AL and AH. Copies MSB
of AL to AH. No flags affected
16. CWD: Convert word to double word. Uses AX and DX.
MSB of AX is copied to DX. No flags affected
Arithmetic Adjustments
DAA- Decimal adjust after addition: After addition, if AL 0-3 >9 OR if AF=1;
AL <- AL+06; if AL4-7 >9 OR if CF=1, AL <- AL+06
DAS Desimal adjust for subtatction: similar to DAA, CF acts as borrow
AAA ASCII adjust after addition: Converts ASCII No. to unpacked BCD.
AL will have BCD value and AH is incremented. CF set accordingly.
User might OR data with 0x30 to get ASCII
AAS-ASCII adjust after subtraction: Similar to AAA, used for subtraction.
CF acts as borrow
AAM ASCII adjust for mulitplication: Multiply two BCD No.s an convert
result to unpacked BCD into AX. Works with AL only. PF,SF and ZF aret
updated; AF,CF and OF are undefined. (might want to OR with 0x30 to
get ASCII)
AAD ASCII adjust for division: (BCD to binary before division):
Converts unpacked BCD in AX to decimal in AL; leave AH=0. PF, ZF and
SF are updated. CF,AF and OF undefined. Might generate /0 erro

Bit manipulation
Typical logical operation. AND, OR and XOR
AND d,s d <- d AND s. Each bit is logically anded.
Similar operation for OR and XOR. CF=OF=0 and AF is
undefined
NOT d d<- NOT(d). bitwise complement. If it is
memory location, need to have byte ptr or word ptr to
indicate 8 or 16 bit data respectively. No flags affected
TEST d,s perform D (bitwise) AND S. D and S are
not affected; flags are updatetd
Shift operation
Left shift corresponds to multiply and right shift operations divide
operations. These are faster than MUL and DIV instructions
SHL/SAL:Shift data left. (MSB) Bit shifted out goes to CF and empty bit
(LSB) is loaded with zero
SHR: Shift Right. Bit shifted out (LSB) goes to CF and empty bit (MSB)
is loaded with zero
SAR -Shift arithmatic right: Similar to SHR, but MSB is retained as it is
ROL: Rotate left. Bit (MSB) shifted out goes to CF and also enters into
empty (LSB) bit
ROR: Rotate right. Bit (LSB) sifhted out goes to CF and also enters into
empty (LSB) bit
RCL: Rotate Circular left. Bit (MSB) shifted out goes to CF, CF goes to
empty (LSB) bit
RCR: Rotate Circular right. Bit (LSB) shifted out goes to CF, CF goes to
empty (MSB) bit
Branch
All unconditional braches are +/-32K (signed 16 bit
offset) and all unconditional branches are +/-128
byres (signed 8 bit offset)
That is jumps are relative
FAR jumps are absolute
Syntax:
JMP label
Jcc Label (cc stands for condition)
JMP [BX]
Jcc [BX+SI]
Branch
JA/JBE Jump Above/Jump Below or Equal (CF OR ZF) = 0
JAE/JNB/JNC Above or Equal/Not Below/No Carry CF=0
JB/JNAE/JC Below/Above or Equal/Carry CF=1
JBE/JNA Below or Equal/Not Above (CF OR ZF) = 1
JE/JZ Equal/Zero ZF=1
JG/JNLE Greater/Not Less or Equal ((SF XOR OF) OR ZF) =1
JGE/JNL Greater or Equal/Not Less (than) (SF XOR OF) = 0
JL/JNGE Less than/Not Greater or Equal (SF XOR OF) = 1
JLE/JNG Less or Equal/ Not Greater ((SF XOR OF) OR ZF) =0
JNE/JNZ Not Equal/Not Zero ZF=0
JNO No Overflow OF=0
JNP/JPO No parity/Parity Odd PF=0
JO Overflow OF=1
JP/JPE Parity/ Parity Even PF=1
JS Sign SF=1
JNS No sign SF=0
LOOP <label> Decrement CX. If CX !=0, jump to the lable
Process Control operations
Process control will operate directly on flags.
Other than the specified flags, no other flags are affected
STC - Set carry: CF=1
CLC Clear carry: CF=0
CMC Coplement carry: CF is complemented
STD Set direction flag: For string operations, SI and/or DI
autometically decremented
CLD Clear direction flag: For string operations, SI and/or DI
automatically incremented
NOP No operations. Does not affect any registers, memory or
flags. Used to generate delay
HLT Halt. Stop execution of program. Interrupt or reset will
bring out of HLT state
String operations
SI and/or DI are used to point to source and destination
SI and/or DI are automatically updated
SI operates within the Data Segment (DS) and DI operates
within Extra Segment (ES)
Instructions should be terminated with either B (for byte) or
W(for word operand). Like LODSB or LODSW. AL is used
for byte and AX is used for word data
LODS load string: Accumulator <- [SI]; update SI
STOS Store string: [DI] <- Accumulator; Update DI
MOVS Move string: [DI] <- [SI]; update SI and DI
SCAS Scan string: compare Accumulator with [DI]; update DI
CMPS Compare string: Compare [DI] and [SI]; update SI and DI
Instruction Encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode D W MOD REG R/M

R/M MOD-> 00 01 10 11 11(W=1)


(W=0)
000 BX+SI BX+SI+d8 BX+SI+d16 AL AX
001 BX+DI BX+DI+d8 BX+DI+d16 CL CX
010 BP+SI BP+SI+d8 BP+SI+d16 DL DX
011 BP+DI BP+DI+d8 BP+DI+d16 BL BX
100 SI SI+d8 SI+d16 AH SP
101 DI DI+d8 DI+d16 CH BP
110 D16/Direct BP+d8 BP+d16 DH SI
111 BX BX+d8 BX+d16 BH DI
Pin configuration
Pin description
AD0-AD15(IO) Address/Data: lower 16 bits of address lines are multiplexed
with data lines. During first clock pulse, address is sent out and during
subsequent clocks, same lines are used for data
A16-A19/S3-S6(O) Address status. Higher nibble of address are multiplexed
with status lines
ALE(O) Address Latch enable: Used to latch address; demultiplex
address/data buses
BHE(O) Bus High Enable: Used to access higher 8bit or 16 bit data
CLK(I) Clock: Input signal, 5 Mhz at 33% duty cycle is used as clock
DEN(O) Data Enable: Used to enable the buffers on data line
GND(I) Ground pin
HOLD(I)/HLDA(O): Hold and Hold Ack. Used for DMA. DMA controllere
requesest the bus via HOLD pin. CPU releases buses and acknowledges
request via HLDA pin
INTR(I)/INTA(O) Interrupt/Ack: External devices request for interrupt via
INRT pin and CPU acknowledges the request via INTA pin
Pin Description
M/IO*(O) Memory/IO*: When this pin is high, CPU accesses data from
memory and when low, accesses the IO device (* indicates active low)
MN/MX*(I) - Min/Max*: In the min. Mode (pin high. Control signals shown in
the blue box), works as stand-alone device and generates all control
signals. max. Mode (pin low) CPU can work with other processors. Signals
are shown near the pins
RD* (O)Read: When the CPU wants to read data, it puts this pin to low.
Ready(I): Used to interface (synchronize with) slow devices
Reset(I): On reset, CPU starts executing from FFFF:0 (or 0xFFFF0)
TEST(I): Wait signal check TEST* If low continues, else waits till it goes low
Vcc(I): +5V power supply
WR*(O) - Write: When the CPU wants to write data, it pulls this pin to low
LOCK(O): Locks the bus. Activated by the LOCK prefix
RQ/GT: Used to synchronize with multiple CPUs
Pin Description
S4 S3 Segment
0 0 Extra Segment
0 1 Stack Segment
1 0 Code Segment
1 1 Data Segment

S2 S1 S0 Action
0 0 0 INTA
0 0 1 IO RD*
0 1 0 IO WR*
0 1 1 HALT
1 0 0 MemRD*
1 1 0 MemWR*
1 1 1

QS1 QS0 Action


0 0 No operation
0 1 First byte from the queue
1 0 Empty queue
1 1 Subsequent byte from queue