What are the various Design constraints used while performing Synthesis for a design? Ans: 1.

Create the clocks (frequency, duty-cycle). 2. Define the transition-time requirements for the input-ports 3. Specify the load values for the output ports 4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip. 5. Specify the case-setting (in case of a mux) to report the timing to a specific paths. 6. Specify the false-paths in the design 7. Specify the multi-cycle paths in the design. 8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold). 19. Specify few verilog constructs which are not supported by the synthesis tool. What are the various design changes you do to meet design power targets? Ans: Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd¶s, by creating Voltageislands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt¶s(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design , clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enable¶s gives a lot of power-savings. As clock-tree¶s always switch making sure that most number of clock-buffers are after the clockgating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage and Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced. related information. what is meant by Library Characterizing Ans: Characterization in terms of delay, power consumption,..

what is meant by wireload model Ans: In the synthesis tool, in order to model the wires we use a concept called as ³Wireload models´, Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for ³n´ number of fanin then we estimate its delay as say ³x´ delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available what are the measures to be taken to design for optimized area Ans: As silicon real-estate is very costly and saving is directly propotional to the company¶s revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets. what all will you be thinking while performing floorplan Ans: Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usuage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise. what are the measures in the Design taken for Meeting Signal-integrity targets Ans: As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let¶s see now by what are all the measures we can reduce/solve it.

As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI. Enable SI aware routing , so that the tool takes care for SI Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other Minimize the parallel run-length wires, by inserting buffers. what are the measures taken in the Design achieving better Yield Ans: Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge. Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to reroute it. For via-reliability issues, use redundant vias, to reduce the chances for via-breakage. In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories. Optimal placing of de-coupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained. what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions Ans: Designing for Optimal integration of Analog and Digital As today¶s IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting closeby, to reduce the noise. Ensure that there exists seperate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro¶s. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion. what are the steps incorporated for Engineering Change Order[ECO] Ans: As more and more complex the IC design is , and with lot of first time application , is more prone to

last minute changes, there should be provision in the design-flow to accomodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO). Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved. what are the steps performed to achieve Lithography friendly Design Ans: Designing for Manufacturability requires validating the design full-filling lithography rules Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets. what does synthesis mean Ans: Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells..

Analog Integrated Circuit Interview question
1) Differentiate between Analog and Digital IC design ? Analog circuit design is different from Digital Circuit design in following aspects: ‡ Layout is critical since the routing should be done according to RF design rules ‡ Layout in digital can be completely automatic which is not the case in analog circuits ‡ Grounding issue is critical in Analog or RFIC compared to Digital IC ‡ Size of analog IC¶s are large compared to digital since it comprises of inductors capacitors and resistors where as digital IC¶s includes only capacitors and resistors. 2) Which are the various processes used for fabrication of IC¶s? The different processes used for fabrication of IC¶s are: ‡ GaAs SiGe CMOS BiCMOS_ should know some fundamentals on each process 3) What is the basic purpose of using EM simulation? Basic purpose of EM simulation is to predict the actual behavior of RF Circuits considering all the parasitic and coupling. This is not considered in circuit simulation.

4) List the instruments required for testing RF Modules and IC¶s Instruments required for RF testing are: ‡ Spectrum Analyzer ‡ Vector Network Analyzer ‡ Noise Figure Meter ‡ Power Meter 5) Which are basic blocks that comprise the RF Transceiver? RF Receiver consists of ‡ Low Noise Amplifier/RF Amplifier ‡ Mixer ‡ Local Oscillator ‡ Demodulator ‡ Automatic Gain controller ‡ Automatic Frequency controller. ‡ Filters ‡ Switch RF Transmitter consists of ‡ RF power amplifier ‡ Modulator ‡ Carrier Oscillator ‡ PLL ‡ Filters ‡ Switch 6) What is the basic function of a power amplifier? The main function of RF power amplifier is to boost the power level of a Signal so that it can travel a significant distance. Power amplifiers are required in all the transmitters 7) What is the basic function of a low noise amplifier? The main function of Low Noise Amplifier is to amplify the weakest possible Signal with Noise Figure as low as possible during reception and to improve the sensitivity and dynamic range of a receiver. 8) What is the basic function of a Mixer? Frequency translation is the key role of Mixer. Output contains the sum or difference of two frequencies i.e. RF frequency and LO(Local Oscillator) Some Good Books: ‡ CMOS Circuit design, layout and simulation, R Jacob Baker, Harry W. Li and David E. Boyce. ‡ Analog Integrated Circuit Design, David Johns, Ken Martin, ‡ CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, ‡ Design of analog CMOS Integrated Circuits, Behzad Razavi, ‡ RF Microelectronics, Razavi

‡ RF microelectronics Thomas Lee ‡ Any Digital books may be rabey Typical questions 1 Gain, (how to improve gain?) 2 Bandwidth, (how to improve bandwidth?) 3 Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!) 4 Slew rate,(How to improve slew rate?) 5 Offset,(how to eliminate offset? Chopper stabilized circuits, auto zero) ? Noise,(what is thermal, flick, shot noise? Or noises of MOSFET? (How to reduce noise) 6 Compensation (what is Miller, lead and Lag compensation? 7 Layout (centroid, interdigital) (how to improve the match of current mirror, differential pairs?, Same surroundings(dummy transistors) and Common-centroid geometry (fingers, interdigitated fingers, what is the purpose of breaking into fingers? 8 Thermal resistance (basic calculation). 9 Filter 10 Oscillator 11 Peak detector 12 Frequency divider 13 Bandgap Reference 14 PLL and its functions VLSI Interview question what is the difference between mealy and moore state-machines Ans: In the mealy state machine we can calculate the next state and output both from the input and state. But in the moore state machine we can calculate only next state but not output from the input and state and the output is issued according to next state. How to solve setup & Hold violations in the design Ans: To solve setup violation 1. optimizing/restructuring combination logic between the flops. 2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx] 3. Tweak launch-flop to have better slew at the clock pin, thiswill make CK->Q of launch flop to be fast there by helping fixing setup violations 4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews) To solve Hold Violations 1. Adding delay/buffer[as buffer offers lesser delay, we go for spl Delay cells whose functionality Y=A, but with more delay] 2. Making the launch flop clock reaching delayed

3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip] What is antenna Violation & ways to prevent it Ans: During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transistor gate connected to these long metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation. The ways to prevent is , by making jogging the metal line, which is atleast one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called accumulative antenna effect. Another way of preventing is adding reverse Diodes at the gates what is tie-high and tie-low cells and where it is used Ans: Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high«(so tie high is a power supply cell)«while the cells which wants Vss connects itself to Tie-low. what is the difference between latches and flip-flops based designs Ans: Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. What is High-Vt and Low-Vt cells. Ans: Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices which have less delay but leakage is high. The thereshold(t) vloltage dictates the transistor switching speed , it matters how much minimum threshold voltage applied can make the transistor switching to active state which results to how

fast we can switch the trasistor. disadvantage is it needs to maintain the transistor in a minimum subthreshold voltage level to make ir switch fast so it leads to leakage of current inturn loss of power. What is LEF mean? Ans: LEF is an ASCII data format from Cadence Design inc, to describe a standard cell library. It includes the design rules for routing and the Abstract layout of the cells. LEF file contains the following, Technology: layer, design rules, via-definitions, metal-capacitance Site : Site extension Macros : cell descriptions, cell dimensions, layout of pins and blockages, capacitances what is DEF mean? Ans: DEF is an ASCII data format from Cadence Design inc., to describe Design related information. VLSI Interview question what is meant by Library Characterizing Ans: Characterization in terms of delay, power consumption,.. what is meant by wireload model Ans: In the synthesis tool, in order to model the wires we use a concept called as ³Wireload models´, Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for ³n´ number of fanin then we estimate its delay as say ³x´ delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available what are the measures to be taken to design for optimized area Ans: As silicon real-estate is very costly and saving is directly propotional to the company¶s revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are

If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets. what all will you be thinking while performing floorplan Ans: Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usuage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise. what are the measures in the Design taken for Meeting Signal-integrity targets Ans: As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let¶s see now by what are all the measures we can reduce/solve it. As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI. Enable SI aware routing , so that the tool takes care for SI Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other Minimize the parallel run-length wires, by inserting buffers. what are the measures taken in the Design achieving better Yield Ans: Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge. Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-

route it. For via-reliability issues, use redundant vias, to reduce the chances for via-breakage. In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories. Optimal placing of de-coupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained. what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions Ans: Designing for Optimal integration of Analog and Digital As today¶s IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting closeby, to reduce the noise. Ensure that there exists seperate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro¶s. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion. what are the steps incorporated for Engineering Change Order[ECO] Ans: As more and more complex the IC design is , and with lot of first time application , is more prone to last minute changes, there should be provision in the design-flow to accomodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO). Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved. what are the steps performed to achieve Lithography friendly Design Ans: Designing for Manufacturability requires validating the design full-filling lithography rules Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets. what does synthesis mean Ans:

Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells.. What are the various ways to reduce Clock Insertion Delay in the Design Ans: 1. Number of Clock sinks 2. Balancing two different clock frequencies 3. Placement of clock sinks. 4. Placement of Clock gating cells 5. Clock tree buffers/inverters drive strength¶s 6. Clock Transition 7. placement of Clockgating cells and the clock sinks 8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockgates) « what are the various functional verification methodologies Ans: TLM(Transaction Level Modelling) Linting RTL Simulation ( Enivronment involving : stimulus generators, monitors, response checkers, transactors) Gate level Simulation Mixed-signal simulations Regression What does formal verification mean? Ans: Formal verification uses Mathematical techniquest by prooving the design through assertions or properties. Correctness of the design can be achieved through assertions with out the necessity for simulations. The methods of formal verification are 1. Equivalence checking In this method of checking the designs are compared based on mathematical equations and compared whether they are equal or not . Original RTL vs Modified RTL RTL vs Netlist Golden Netlist vs Modified/Edited Netlist Synthesis Netlist vs Place and route Netlist Remember : Formal verification doesnt check for functionality of the RTL code. It will be only checking the equivalence. 2. Model checking Property specification languages like PSL or SVA, are formally analyzed to see if they are always true for a design. This can exhaustively prove if a property is correct, but does tend to suffer from state-space explosion: the time to analyse a design is directly propotional to the amount of states.

VLSI Interview question answers Steps involved in designing an optimal padring Ans: 1. Make sure you have corner-pads, across all the corners of the padring, This is mainly to have the power-continuity as well as the resistance is less 2. Ensure that the Padring ful-fills the ESD requirement, Identifyh the power-domains, split the domains, Ensure common ground across all the domains. 3. Ensure the padring has ful-filled the SSN(Simultaneous Switching Noise) requirement. 4. Placing Transfer-cell Pads in the cross power-domains, for different height pads, to have rail connectivity. 5. Ensure that the design has sufficient core power-pads. 6. Choose the Drive-strenght of the pads based on the current requirements, timing. 7. Ensure that there is seperate analog ground and power pads. 8. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O¶s.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with un-connected inputs, as they consume power if the inputs float. 9. Ensure that oscillator-pads are used for clock inputs. 10. In-case if the design requirement for source synchronous circuits, make sure that the clock and data pads are of same drive-strength. 11. Breaker-pads are used to break the power-ring, and to isolate the power-structure across the pads. 12. Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin. 13. In case if required , place pads with capacitance. What is metastability and steps to prevent it. Ans: Metastability is an unknown state it is neither Zero nor One.Metastability happens for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable

after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously. Steps to prevent Metastability. 1. Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the metastable event. 2. Use synchronizers between cross-clocking domains to reduce the possibility from metastability. 3. Using Faster flip-flops (which has narrower Metastable Window). 12. what is local-skew, global-skew,useful-skew mean? Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path. Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain. Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design. what is meant by virtual clock definition and why do i need it? Ans: Virtual clock is mainly used to model the I/O timing specification. Based on what clock the output/input pads are passing the data. What are the various timing-paths which i should take care in my STA runs? Ans: 1. Timing path starting from an input-port and ending at the output port(purely combinational path). 2. Timing path starting from an input-port and ending at the register. 3. Timing path starting from an Register and ending at the output-port. 4. Timing path starting from an register and ending at the register. What are the various components of Leakage-power? Ans:

1. sub-threshold leakage,«.think of ths answer What are the various yield-losses in the design? Ans: The yield loss in the design is characterized by 1. Functional yield losses, mainly caused by spot defects , especially (shorts & opens) 2. Parametric yield losses, due to process variations.

application specific integrated circuit interview questions and answers
1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signals, while NMOS networks are used to product low (0) signals? PMOS is used to drive µhigh¶ because of the threshold voltage-effectThe same is true for NMOS to drive µlow¶.A NMOS device cant drive a full µ1 and PMOS cant drive full µ0 Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing 2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean? The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)If given only one number it¶s the width combined with a default length 3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four? To limit the height of the stack. As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be. 4) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero? Cool What is a transmission gate, and what is it used for typically? Why are transmission gates made with both PMOS and NMOS transistors?

9) What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal¶s path? 10) What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal? 11) What is the difference between a mask layer and a drawn layer in an IC layout? Why do layout designers usually only specify drawn layers? 12) In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each? A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it¶s off grid with 45 degree angle. Polygon is always on-grid, unless it¶s a copy and flip. However, polygon is hard to edit and work with. 13) What is the difference between a contact and a via? What is a ³stacked´ via process? Via: a contact between two conductive layers. Contact:Opening in an insulating film to allow contact to an underlying electronic device. The placement of vias directly over the contacts or other,lower vias is known as stacked via. 14) Why is it that NMOS transistors can be created directly in a P-type substrate, whereas PMOS transistors must be created in an N-type well? 15) Why must transistors be provided with ³bulk´ connections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why? To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules? What is their major purpose? How are design rules created? 17) What are width rules, space rules, and overlap rules? 18) What is a ³vertical connection diagram´?

What is it used for? vertical connection diagram illustrates the relative position, go vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes. 19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why? 20) What are the major advantages of hierarchical IC design? Concurrent design ‡ Design reuse ‡ Predictable schedules
I think there is no or small difference between asic interview and vlsi interview, some vlsi interview questions I am posting, which I have collected 1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signals, while NMOS networks are used to product low (0) signals? PMOS is used to drive high because of the threshold voltage-effectThe same is true for NMOS to drive low .A NMOS device cant drive a full 1 and PMOS cant drive full 0 Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing 2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean? The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)If given only one number it s the width combined with a default length 3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four? To limit the height of the stack. As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be. 4) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero? Cool What is a transmission gate, and what is it used for typically? Why are transmission gates made with both PMOS and NMOS transistors? 9) What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal s path? 10) What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal? 11) What is the difference between a mask layer and a drawn layer in an IC layout? Why do layout designers usually only specify drawn layers?

12) In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each? A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it s off grid with 45 degree angle. Polygon is always on-grid, unless it s a copy and flip. However, polygon is hard to edit and work with. 13) What is the difference between a contact and a via? What is a stacked via process? Via: a contact between two conductive layers. Contact:Opening in an insulating film to allow contact to an underlying electronic device. The placement of vias directly over the contacts or other,lower vias is known as stacked via. 14) Why is it that NMOS transistors can be created directly in a P-type substrate, whereas PMOS transistors must be created in an N-type well? 15) Why must transistors be provided with bulk connections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why? To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules? What is their major purpose? How are design rules created? 17) What are width rules, space rules, and overlap rules? 18) What is a vertical connection diagram ? What is it used for? vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes. 19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why? 20) What are the major advantages of hierarchical IC design? Concurrent design Design reuse Predictable schedules

Most common question is draw basic digital gates using transistor. as an expert of vlsi , I will tell that go through vlsi book, any book is fine, solve as many questions it will enhance your skill and bring more confidence on vlsi interview. What is antenna Violation & ways to prevent it Ans: During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transistor gate connected to these long

metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation. The ways to prevent is , by making jogging the metal line, which is atleast one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called accumulative antenna effect. Another way of preventing is adding reverse Diodes at the gates what is tie-high and tie-low cells and where it is used Ans: Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high«(so tie high is a power supply cell)«while the cells which wants Vss connects itself to Tie-low. what is the difference between latches and flip-flops based designs Ans: Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. What is High-Vt and Low-Vt cells. Ans: Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices which have less delay but leakage is high. The thereshold(t) vloltage dictates the transistor switching speed , it matters how much minimum threshold voltage applied can make the transistor switching to active state which results to how fast we can switch the trasistor. disadvantage is it needs to maintain the transistor in a minimum subthreshold voltage level to make ir switch fast so it leads to leakage of current inturn loss of power. What is LEF mean? Ans:

LEF is an ASCII data format from Cadence Design inc, to describe a standard cell library. It includes the design rules for routing and the Abstract layout of the cells. LEF file contains the following, Technology: layer, design rules, via-definitions, metal-capacitance Site : Site extension Macros : cell descriptions, cell dimensions, layout of pins and blockages, capacitances

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