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# Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8

Entit et architecture

## Exemple1 : Afficheur 7 segment

(1.0.0..0)
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8

## Code Code Segments

A3 A2 A1 A0 A B C D E F G
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
A 1 0 1 0 1 1 1 0 1 1 1
b 1 0 1 1 0 0 1 1 1 1 1
c 1 1 0 0 0 0 0 1 1 0 1
d 1 1 0 1 0 1 1 1 1 0 1
E 1 1 1 0 1 0 0 1 1 1 1
F 1 1 1 1 1 0 0 0 1 1 1

## A = (A1./A3) + (/A0./A2) + (A1.A2) + (A0.A2./A3) + (/A1./A2.A3)

B = (/A2./A3)+(/A2./A0)+(A0./A1.A3)+(A0./A3.A1)+(/A0./A1./A3)
C = (A2./A3) + (/A2.A3) + (/A1./A3) + (A0./A3) + (A0./A1)
D = (/A1.A3) + (A1./A2./A3) + (/A0.A1.A2) + (/A0./A2./A3) + (A0./A2.A3) +
(A0./A1.A2)
E = (A2.A3) + (/A0./A2) + (A1.A3) + (/A0.A1)
F = (/A2.A3) + (A1.A3) + (/A1.A2./A3) + (/A0.A2./A3) + (/A0./A1./A3)
G = A3 + (A1./A2) + (/A1.A2) + (/A0.A2)

Entit et architecture
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8

Programme en VHDL

## Library ieee; library ieee;

Use ieee.std_logic_1164.all; Or use ieee.std_logic_1164.all;
Entity Transcodeur binaire 7 segments is entity Transcodeur binaire 7 segments is
port ( port (A: in std_logic_vector(3 downto 0);
A : in std_logic_vector(3 downto 0); o :out std_logic_vector(6 downto 0));
A, B, C, D,E,F,G: out std_logic); end Transcodeur binaire 7 segments;
architecture VHDL of Transcodeur binaire 7
End Transcodeur binaire 7 segments; segments is
begin
Architecture vhdl of Transcodeur binaire 7 segments is process (A)
begin
Begin
case A is
A<=(A1 AND( NOT A3)) or ((not A0) AND (NOT A2)) or (A1 AND when "0000"=>o<="1111110";
A2) or (A0 AND A2 AND (NOT A3)) or ((not A1) AND (NOT A2) when "0001"=>o<="0110000";
when "0010"=>o<="1101101";
AND A3);
when "0011"=>o<="1111001";
B<=((not A2) AND (NOT A3))or((NOT A2) AND (NOT A0))or(A0 when "0100"=>o<="0110011";
AND (NOT A1) AND A3)or(A0 AND (NOT A3) AND A1)or((not when "0101"=>o<="1011011";
A0) AND A1 AND (NOT A3)); when "0110"=>o<="x011111";
when "0111"=>o<="1110000";
C<=(A2 AND (NOT A3)) or ((not A2) AND A3) or ((not A1) AND when "1000"=>o<="1111111";
not A3)or (A0 AND (NOT A3))or(A0 AND (NOT A1)); when "1001"=>o<="1111011";
when others=>o<="xxxxxxx";
D<=(not A1 AND A3) OR(A1 AND NOT A2 AND NOT A3) OR end case;
(NOT A0 AND A1 AND A2) OR(NOT A0 AND NOT A2 AND NOT end process;
A3) OR (A0 AND NOT A2 AND A3) OR(A0 AND NOT A1 AND A2); end vhdl;

E<=(A2 AND A3) OR(NOT A0 AND NOT A2) OR(A1 AND A3) OR
(NOT A0 AND A1);

## F<=(not A2 AND A3) OR (A1 AND A3) OR (NOT A1 AND A2 AND

NOT A3) OR(NOT A0 AND A2 AND NOT A3) OR (NOT A0 AND
NOT A1 AND NOT A3);

## G<= A3 OR (A1 AND NOT A2) OR (NOT A1 AND A2) OR (NOT A0

AND A2);

end vhdl;
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8

## Exemple 2 : ( Mux 8x1)

n
2 entres dinformation
Une seule sortie
n entres de slection (commandes)

## slection Equation logique

Z=/S2./S1./S0.A+/S2./S1.S0.B+/S2.S1./S0.C+/S2.S1.
S2 S1 S0 Z
S0.D+S2./S1./S0.E+S2./S1.S0.F+S2.S1./S0.G+S2.S1.
0 0 0 A S0.H
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F
1 1 0 G
Programmation en vhdl
1 1 1 H
Library ieee; Library ieee; Library ieee;
Use ieee.std_logic_1164.all; Use ieee.std_logic_1164.all; Use ieee.std_logic_1164.all;
Entity Mux 8x1is Entity Mux 8x1is Entity Mux 8x1is
port ( port ( port (
A,B,C,D,E,F,G,H: in std_logic); A,B,C,D,E,F,G,H: in std_logic); A,B,C,D,E,F,G,H: in std_logic);
s : in std_logic_vector (2 s : in std_logic_vector (2 S0 : in std_logic ;
downto 0); downto 0); S1 : in std_logic ;
Z: out std_logic); Z: out std_logic); S2 : in std_logic ;
End Mux 8x1; End Mux 8x1;
Architecture vhdl of Mux 8x1 is Architecture vhdl of Mux 8x1 is Z: out std_logic);
begin begin End Mux 8x1;
process (A, B, C, D,E,F,G,H,s) with s select Architecture vhdl of Mux 8x1 is
Begin z<=A when 000, Begin
Case s is B when001, Z<=(not s2 and not s1 and not
When000=>Z<=A; C when010, s0 and A) or (not s2 and not s1
When001=>Z<=B; D when011, and s0 and B) or (not s2 and s1
When010=>Z<=C; E when100, and not s0 and C )or( not s2 and
When011=>Z<=D; F when101, s1 and s0 and D )or( s2 and not
When100=>Z<=E; G when110, s1
When101=>Z<=F; H when 111, And not s0 and E )or( s2 and
When110=>Z<=G; - when others; not s1 and s0 and F )or( s2 and
When 111=>Z<=H; end vhdl; s1 and not s0 and G )or (s2 and
when others=>Z<=H; s1 and s0 and H);
end case; end vhdl;
end process;
end vhdl;
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8

## Exemple 3 : dcodeur 3x8

COD SORTIE
A2 A1 A0 S1 S2 S3 S4 S5 S6 S7 S8
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 00
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

S1=** S5=**A2

## S2=A0** S6= A0**A2

S3=*A1* S7=*A1*A2

## S4= A0*A1* S8=A0*A1*A2

PROGRAMM EN VHDL
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8

## Library ieee; OU Library ieee;

Use ieee.std_logic_1164.all; Use ieee.std_logic_1164.all;
Entity dcodeur 3*8 is entity dcodeur 3*8 is

## Port ( A : in STD_LOGIC_VECTOR (2 downto 0);

Port ( A0,A1,A2 : in STD_LOGIC;
S1,S2,S3,S4,S5,S6,S7,S8 : out STD_LOGIC); S : out STD_LOGIC_VECTOR (8 downto 1));
end dcodeur 3*8;
end dcodeur 3*8;
architecture vhdl of dcodeur 3*8 is
Architecture vhdl of dcodeur 3*8 is
begin
begin
S1<=not A0 AND NOT A1 AND NOT A2;
with A select
S2<= A0 AND NOT A1 AND NOT A2;
S<="10000000" when "000",
S3<= NOT A0 AND A1 AND NOT A2;
"01000000" when "001",
S4<= A0 AND A1 AND NOT A2;

## architecture Behavioral of dcodeur 3*8 is "00000000" when others;

begin
process (A) end vhdl;
begin
case A is
when "000"=>S<="10000000";
when "001"=>S<="01000000";
when "010"=>S<="00100000";
when "011"=>S<="00010000";
when "100"=>S<="00001000";
when "101"=>S<="00000100";
when "110"=>S<="00000010";
when "111"=>S<="00000001";
when others=>S<="00000000";
end case;
end process;
end Behavioral;