MZ Dts

/*
* CAUTION: This file is automatically generated by Xilinx.

* Version:
* Today is: Tue Nov 28 16:16:36 2017
*/
/ {
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
adc_if_mem_axis: mem_axis_v1_1@43c10000 {
compatible = "xlnx,mem-axis-v1-1-1.1";
reg = <0x43c10000 0x10000>;
xlnx,fifo-data-width = <0x12>;
};
axi_pps: axi_pps@43c20000 {
compatible = "xlnx,axi-pps-1.0";
reg = <0x43c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
axis_sw_dma_daq_mm2s: axis_switch@83c00000 {
compatible = "xlnx,axis-switch-1.1";
reg = <0x83c00000 0x10000>;
xlnx,arb-algorithm = <0x0>;
xlnx,arb-on-max-xfers = <0x1>;
xlnx,arb-on-num-cycles = <0x0>;
xlnx,arb-on-tlast = <0x0>;
xlnx,axis-signal-set = "0b00000000000000000000000001010011";
xlnx,axis-tdata-width = <0x20>;
xlnx,axis-tdest-width = <0x5>;
xlnx,axis-tid-width = <0x1>;
xlnx,axis-tuser-width = <0x1>;
xlnx,common-clock = <0x0>;
xlnx,decoder-reg = <0x1>;
xlnx,include-arbiter = <0x1>;
xlnx,log-si-slots = <0x1>;
xlnx,num-mi-slots = <0x5>;
xlnx,num-si-slots = <0x1>;
xlnx,output-reg = <0x0>;
xlnx,routing-mode = <0x1>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
};
daq_rt_axis_sw_daq: axis_switch@83c10000 {
reg = <0x83c10000 0x10000>;
};
dma_if_dma_daq: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk m_axi_sg_aclk m_axi_mm2s_aclk
m_axi_s2mm_aclk";
clocks = "clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15";
compatible = "xlnx,axi-dma-1.00.a";
interrupt-parent = <&intc>;
interrupts = <0 29 4 0 30 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 29 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
compatible = "xlnx,axi-dma-s2mm-channel";
};
};
dma_if_dma_muzzle: dma@80420000 {
#dma-cells = <1>;
m_axi_s2mm_aclk";
interrupts = <0 31 4 0 32 4>;
reg = <0x80420000 0x10000>;
xlnx,include-sg ;
};
};
};
dma_if_dma_predet: dma@80410000 {
#dma-cells = <1>;
m_axi_s2mm_aclk";
interrupts = <0 35 4 0 36 4>;
reg = <0x80410000 0x10000>;
xlnx,include-sg ;
};
};
};
dma_if_dma_shock: dma@80430000 {
#dma-cells = <1>;
m_axi_s2mm_aclk";
interrupts = <0 33 4 0 34 4>;
reg = <0x80430000 0x10000>;
xlnx,include-sg ;
};
};
};
fir_s1_axis_fir1_rlc: axis_switch@83c20000 {
reg = <0x83c20000 0x10000>;
};
gpio_if_axi_gpio_ext_in: gpio@81230000 {
#gpio-cells = <2>;
compatible = "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x81230000 0x10000>;
xlnx,all-inputs = <0x1>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x9>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
gpio_if_axi_gpio_ext_out: gpio@81200000 {
#gpio-cells = <2>;
gpio-controller ;
reg = <0x81200000 0x10000>;
};
gpio_if_axi_gpio_gps_pps: gpio@81240000 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller ;
interrupt-controller ;
reg = <0x81240000 0x10000>;
};
gpio_if_axi_gpio_hw_in: gpio@81210000 {
#gpio-cells = <2>;
gpio-controller ;
reg = <0x81210000 0x10000>;
};
gpio_if_axi_gpio_hw_out: gpio@81220000 {
#gpio-cells = <2>;
gpio-controller ;
reg = <0x81220000 0x10000>;
};
};
};
/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "pl.dtsi"
/include/ "pcw.dtsi"
/ {
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram0 rw init=/sbin/init earlyprintk
rootwait devtmps.mount=1 mem=384M maxcpus=1 earlycon";
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
spi0 = &qspi;
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
cpus {
};
};
/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "pl.dtsi"
/include/ "pcw.dtsi"
/ {
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram0 rw init=/sbin/init earlyprintk
rootwait devtmps.mount=1 maxcpus=1 earlycon
ip=192.168.10.50:192.168.10.7::255.255.255.0::eth0:dhcp";
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
spi0 = &qspi;
};
memory {
device_type = "memory";
reg = <0x0 0x18000000>;
};
cpus {
};
shared_mem {
compatible = "xlnx,reserved-memory";
no-map;
reg = <0x18000000 0x28000000>;
};
};
/*
* Copyright (C) 2011 - 2014 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
#size-cells = <1>;
compatible = "xlnx,zynq-7000";
cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
clocks = <&clkc 3>;
clock-latency = <1000>;
cpu0-supply = <&regulator_vccpint>;
operating-points = <
/* kHz uV */
666667 1000000
333334 1000000
>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
clocks = <&clkc 3>;
};
};
fpga_full: fpga-full {
compatible = "fpga-region";
fpga-mgr = <&devcfg>;
#size-cells = <1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
regulator_vccpint: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
amba: amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#size-cells = <1>;
ranges;
adc: adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
clocks = <&clkc 12>;
};
can0: can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 19>, <&clkc 36>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
reg = <0xe000a000 0x1000>;
};
i2c0: i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
reg = <0xe0004000 0x1000>;
#size-cells = <0>;
};
i2c1: i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
reg = <0xe0005000 0x1000>;
#size-cells = <0>;
};
intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
};
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
mc: memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc: ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
reg = <0xf800c000 0x1000>;
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
};
uart1: serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
clock-names = "ref_clk", "pclk";
#size-cells = <0>;
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
#size-cells = <0>;
};
qspi: spi@e000d000 {
compatible = "xlnx,zynq-qspi-1.0";
reg = <0xe000d000 0x1000>;
#size-cells = <0>;
};
smcc: memory-controller@e000e000 {
#size-cells = <1>;
clock-names = "memclk", "aclk";
compatible = "arm,pl353-smc-r2p1";
ranges ;
reg = <0xe000e000 0x1000>;
nand0: flash@e1000000 {
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
nor0: flash@e2000000 {
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#size-cells = <1>;
};
};
gem0: ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#size-cells = <0>;
};
gem1: ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
#size-cells = <0>;
};
sdhci0: sdhci@e0100000 {
compatible = "arasan,sdhci-8.9a";
clock-names = "clk_xin", "clk_ahb";
reg = <0xe0100000 0x1000>;
broken-adma2;
};
sdhci1: sdhci@e0101000 {
compatible = "arasan,sdhci-8.9a";
clock-names = "clk_xin", "clk_ahb";
reg = <0xe0101000 0x1000>;
broken-adma2;
};
slcr: slcr@f8000000 {
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
"gem1_aper", "sdio0_aper", "sdio1_aper",
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
"dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
};
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
};
};
dmac_s: dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
"dma4", "dma5", "dma6", "dma7";
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <4>;
clock-names = "apb_pclk";
};
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
};
efuse: efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
global_timer: timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <1 11 0x301>;
clocks = <&clkc 4>;
};
ttc0: timer@f8001000 {
interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8001000 0x1000>;
};
ttc1: timer@f8002000 {
interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
};
scutimer: timer@f8f00600 {
interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
};
usb0: usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
};
usb1: usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog0: watchdog@f8005000 {
compatible = "cdns,wdt-r1p2";
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
};
};

MZ Dts

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MZ Dts

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/*

* CAUTION: This file is automatically generated by Xilinx.

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