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LCD DRIVER/CONTROLLER

DATA BOOK
1986

1310 Kifer Road


Sunnyvale, CA 94086

(408) 737-0204
CONTENTS

PRODUCT LINE-UP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .1

2 PACKAGING ...................................................... 3

3 DATA SHEET ...................................................... 11

STATIC LCD DRIVER .............................................. 13


MSM58292GS 5 DIGIT LCD DRIVER. - - . - - . - ........................... 14
MSM5219BGS 48 DOT LCD DRIVER ................................... 25
MSM5221GS 56 DOT LCD DRIVER ................................... 31
MSM5265GS 160 DOT LCD DRIVER ................................... 36

DOT MATRIX LCD DRIVER .......................................... 49


MSM5238GS 32 DOT COMMON DRIVER ............................... 50
MSM5839BGS 40 DOT SEGMENT DRIVER ............................... 58
MSM5259GS 40 DOT SEGMENT DRIVER ............................... 65
MSM5260GS 80 DOT COMMON/SEGMENT DRIVER ....................... 74
MSM5278GS 64 DOT COMMON DRIVER ............................... 82
MSM5979GS 80 DOT SEGMENT DRIVER ............................... 89

DOT MATRIX LCD CONTROLLER ..................................... 99


MSM6222B-01GS DOT MATRIX LCD CONTROLLER WITH 16 DOT COMMON
DRIVER AND 40 DOT SEGMENT DRIVER ................. 100
MSM6240GS DOT MATRIX LCD CONTROLLER .......................... '137
MSM6255GS DOT MATRIX LCD CONTROLLER .......................... 162
MSM6265GS DOT MATRIX LCD CONTROLLER .......................... 196

OKI makes no warranty for the use of its products and assumes no responsibility for
any errors which may appear in this document nor does it make a commitment to
update the. information contained herein.
OKI retains the right to make changes to these specifications at any time, without
notice.
PRODUCT D
LINE-UP
PRODUCT LINE-UP
o APPLICATION TYPE NO FUNCTION
OUTPUT
DUTY PACKAGE REMARKS
COMMON SEGMENT

MSM58292 static driver 5 digit (7 segment) 1/1 56 FLT.

MSM5219B static driver 48 dot 1/1 60 FLT.


STATIC LCD
DRIVER
MSM5221 static driver 56 dot 1/1 80 FLT.

MSM5265 static driver 160 dot 1/1 or 1/2 100 FLT.

COMMON
MSM5238
DRIVER
32 - 1/32 - 1/128 44 FLT.

SEGMENT
MSM5839B - 40 1/8 - 1/128 56 FLT.
DRIVER

SEGMENT use with


MSM5259
DRIVER
- 40 1/1 - 1/16 56 FLT.
MSM6222B-Ol
COMMON/ COMMON/
DOT MATRIX
MSM5260 SEGMENT 80 80 1/1 - 1/128 100 FLT. SEGMENT
LCD DRIVER
DRIVER selectable

COMMON
MSM5278
DRIVER
64 - 1/8 - 1/128 80 FLT.

SEGMENT
MSM5279 - 80 1/8 - 1/128 100 FLT.
DRIVER
DRIVER/ with character
MSM6222B CON- 16 40 1/8 - 1/16 80 FLT. generator
-01 TROLLER ROM

CON-
DOT MATRIX
MSM6240
TROLLER
- - 1/32 - 1/144 60 FLT.

LCD
CONTROLLER CON-
MSM6255
TROLLER
- - 1/2 - 1/256 80 FLT. 512K dot

512K dot
software
CON-
MSM6265
TROLLER
- - 1/100 x 2 80 FLT. compatible
with CRT
Controller

Note: 1. MSM5259 and MSM5260 can be used as static display dot dri"es like MSM5219B and so forth.
2. The duty of LCD module is determined by the perform~mce of drivers and the material of LCD panel.
So, to select suitable LCD driver for superior display, it is necessary to study the material of the LCD
panel.

2
PACKAGING
H
PACKAGING
PLASTIC FLAT
PRODUCT PACKAGE GS-K GS-L GS-L2
(No. of Pins)

MSM58292 56 (small) 0

STATIC LCD MSM5219S 60 0


DRIVER
MSM5221 80 0
MSM5265 100 0

MSM5238 44 0 0

MSM5839S 56 (small) 0 0

DOT MATRIX MSM5259 56 (small) 0 0


LCD DRIVER
MSM5260 100 0 0

MSM5278 80 0

MSM5279 100 0
MSM6222S-01 80 0

DOT MATRIX MSM6240 60 0


LCD CONTROLLER
MSM6255 80 0
MSM6265 80 0

Note: Model names suffixed by GS denote plastic mold flat package, while -K, -L or -L2 denote
the direction of the lead bent.

Plastic Flat Package Variations

Top
6
GS-K

..... GS-L/GS-L2 .
o
Bottom

4
- - - - - - - - - - - - - - - - - - - - - - - - - 1 1 . PACKAGING

44 PIN PLASTIC FLAT PACKAGE

121

~\'r
'"
o
33 fI
22

=
:...

12

'"
o

Index mark 1.25 B.O 1.25

~-
1.5 2.0 10.5 2.0
MSM5238GS-K I--I~---------~-_l (Unit: mm)

56 PIN PLASTIC FLAT PACKAGE

12.1

42

o
I\,) in
" (J'1
I\,)

1.025 8.45
MSM58292GS-K 1.5 Index mark 2.0 10.5
MSM5839BGS-K
MSM5259GS-K

5
.PACKAGING.-----------------------------------------------

60 PIN PLASTIC FLAT PACKAGE

2.5,0.4 19.0'0.3 2.5,0.4

~II
Index mark
16

MSM5219BGS-K
MSM6240GS-K

80 PIN PLASTIC FLAT PACKAGE

2.10

64 45

MSM5221GS-K
MSM5278GS-K
MSM6255GS-K
MSM6265GS-K 0 ' 10

6
- - - - - - - - - - - - - - - - - - - - - - - -.... PACKAGING

100 PIN PLASTIC FLAT PACKAGE

fJ
0.15

MSM5265GSK
MSM5260GSK
MSM5279GSK

7
PACKAGING ----------------------------------------------

44 PIN PLASTIC FLAT PACKAGE (LEAD BENT OPPOSITE DIRECTION)

(Unit: mm)

12.1

23
....
It)

ci
0
N
22

;: ==*0
co
<Xi
Ln
en

ci

12
Ln

ci
0
N
11

Index mark

8.0 1.25

2.0 10.5 2.0


1.5

MSM5238GS-L2

o 56 PIN PLASTIC FLAT PACKAGE (LEAD BENT OPPOSITE DIRECTION)

(Unit: mm)

12.1

Index mark

2.0 10.5 2.0

MSM5839BGS-L2
MSM5259GS-L2

8
-------------------------------------------------PACKAGING-

80 PIN PLASTIC FLAT PACKAGE (LEAD BENT OPPOSITE DIRECTION)

(Unit: mm)

MSM6222B-01 GS-L

o 100 PIN PLASTIC FLAT PACKAGE (LEAD BENT OPPOSITE DIRECTION)


(Unit: mm)

MSM5260GS-L

9
10
DATA SHEET
12
STATIC
LCD
DRIVER
OKI semiconductor
MSM58292GS
5-DIGIT STATIC LCD DRIVER

GENERAL DESCRIPTION

11 The OKI MSM58292GS is a 7-segment static LCD driver LSI which is fabricated by low power CMOS metal gate
technology. This LSI consists of 32-bit shift register, 32-bit latch, 5 sets of 7-segment decoder and LCD drivers.

It receives the serial display data from the microcomputer etc, converts it to a parallel data, then output to the
7-segment LCD panel.

The input code for each digit is a 4-bot binary code. The input codes are decoded into digits 0 ~ 9 and alphabetic
letters A - F, to display hexadecimal numbers. The expansion of display can be easily made by using another
MSM58292GS in cascade connection.

The MSM58292GS can directly drive the LCD panel, as the AC driving circuit is integrated on the chip.

FEATURES
5 digit 7-segment LCD display Supply voltage: 3 -7V
Serial input from the microcomputer etc. 56 pin plastic flat package
Expansion of display by cascade connection

PIN CONFIGURATION

n
o
;!:

VSS a1
OSC

SERIAL OUT
0 92
f2

SERIAL IN e2

CLOCK dl

LOAD DP.1

VDD C.I

BI/RBO VDD

OUTPUT DISABLE b.1

a.1

f.l

9.1

e.1

d.l

14
OJ
r
o(")
"
o
(MSD) (LSD)
i>
C)

~
OSC SC a, b, c, d,e,',Q, F, F2 COM COM :0
JOOOOO(
s:
~-
OUTP
DISABLE

BLANKO~--------------~

BCD - to BCD~to BCD~to BCD ~to BCD~to


7 SEGMENT 7 SEGMENT 7 SEGMENT 7 SEGMENT 7 SEGMENT
flBI 01-------- DECODER DECODER DECODER DECODER DECODER b II II 0 BilBRO

en
~

::!
("')

LOAD O . - - - - - - - - - - i 32 BIT LATCH


r
("')
:DP,DP4DPPP1DP,: F, F, BL, B4 BL, BL, BL,
0
0
:0
SERIAL
IN
0 10 "I II ,
II II
I
I i i
II II ." i
SERIAL
<
m
OUT :0
0>-------1
CLOCK
s:
en
s:
U'1
00
N
to
N
C)
en
~

In

~
- STATIC LCD DRIVER MSM58292GS - - - - - - - - - - - - - - - - -

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Limits Unit


Supply voltage Voo -0.3 -7 V
Ta ~ 25C
I nput voltage VI -0.3- V OO V
Storage temperature Tstg - -55 -+150 c

11 OPERATING RANGE

Item Symbol Condition Limits Unit


Supply voltage VOO - 3 -7 V
Operating temperature TOp - -30 -+85 c
BI/RBO N MOS load 1 -
Fan out MOS load 40 -
SERIAL OUT N
TTL load 1 -

DC CHARACTERISTICS
(Voo = 5V 5%, Ta ~ -30 - +85C)

Item Symbol Condition MIN TYP MAX Unit

High Input voltage VIH - 3.6 - - V


Low Input voltage VIL - - - 0.8 V
l
High Output voltage VOH 10 = -511 A 4.95 - - V
l
Low Output voltage VOL 10=5J1A - - 0.05 V
2
High Output voltage VOH 10 = -40 J1A 4.2 - - V
2
Low Output voltage VOL 10 = 1.6mA - - 0.4 V
3
High Output voltage VOH 10 = -50011A 4.5 - - V
3
Low Output voltage VOL 10 = 500l1A - - 0.5 V
4
High Output voltage VOH 10 ~ -250 JlA 4.5 - - V
4
Low Output voltage VOL 10 = 250l1A - - 0.5 V
Input currentS IIH/IIL VI = VOOIVI = OV - - 1/-1 I1A

l -0.2/
Output current 10H/IOL VO=OVIVO=VOO
0.2
- - mA

2 -0.2/
Output current 10H/IOL Vo = 2.5V1V0 = O.4V - - mA
1.6
-10/ -500/
BI/R-t30 short-circuit current 10H/IOL VO=OVIVO=VOO - I1A
10 500
Dynamic current consumption 100 f (OSC) = 360Hz no load - - 500 I1A

Note 1: Applied to the output pins excluding the SERIAL OUT, BI/RBO, COM and COM Pins.
Note 2: Applied to the SERIAL OUT pin.
Note 3: Applied to the COM pin.
Note 4: Applied to the COM pin.
Note 5: Applied to the input pins excluding the OSC pin.

16
- - - - - - - - - - - - - - - - STATIC LCD DRIVER MSM58292GS-

SWITCHING CHARACTERISTICS
(VDD = 5V. Ta = 25C. CL = 15pF)

Item Symbol Condition MIN TYP MAX Unit


Propagation delay time tpHL
(for a shift in the shift register)
- - - 1000 nS
tpLH

tTHL
SERIAL OUT rise/fall time - - - 300 nS
tTLH
Maximum clock frequency ilCK) max - 1 - - MHz
Minimum clock pulse width tw(CK) - - - 500 nS
Minimum load pulse width twILl - - - 500 nS
1
Data setup time SERIAL IN ~CLOCK tsetup - - - 250 nS
2
Data setup time SERI AL OUT ~ LOAD tsetup - - - 500 nS

CLOCK
50% 50% 50%

- - "'""""\ r- -
SERIAL IN 50% _ _ _ _ _ _ ...J 50%
'-

90%
SERIAL OUT

- - - - ; - H - - t se tup2

LOAD 50%

17
STATIC LCD DRIVER MSM58292GS - - - - - - - - - - - - - -

FUNCTION TABLE

SEGMENT OUT (Note 1)


Hexadecimal digit RBI BI/RBO
b c d f g
Display
a e
* * L L L L L L L L (Note 3)
0 * (Note 2) L L L L L L L (Note 4)
I I
0 * H H H H H H H L
1 * H L H H L L L L
L'
,
I
I
2 * H H H L H H L H C
_I
3 * H H H H H L L H
-'
4 * H L H H L L H H '-',
5 * H H L H H L H H ,-,
6 * H H L H H H H H ,-
,_,
I
7 * H H H H L L L L I
, ,,-
8 * H H H H H H H H I -
9 * H H H H H L H H I- I ,
A * H H H H L H H H ,,_, I
(
B * H L L H H H H H
1='
,,-
C * H H L L H H H L
D * H L H H H H L H ,-,,
E * H H L L H H H H I
I-

F * H H L L L H H H C
I

Note 1: The H indicates that the segment is displayed. and the L indicates that the segment is not displayed. The H
is an antiphase output of the COM output. and the L is an inphase output of the COM output.
Note 2: The RI/RBO pin goes to low level only when the RBI pin is at a low level and all the digit are 0 (the display
is blank).
If the BI/RBO pin is forcibly turned to high level. 0 at LSD is displayed.
Note 3: If the BI/RBO pin is forcibly turned to low level. the LSD is made blank.
Note 4: If the RBI pin is turned to low level, the display is placed in the leading zero blanking status, in which the
contiguous Os preceding the MSD are made blank.

18
- - - - - - - - - - - - - -...... STATIC LCD DRIVER MSM58292GS.

FUNCTIONAL DESCRIPTION
SERIAL IN
The SERIAL IN pin is a shift register data input in the order of blank data, flag data, decimal point
pin. The display data are input to this pin synchro- data, then numeric data (beginning with the LSB)
nized with the clock pulses. The data are input (positive logic).
< Data input procedure>

OSERIAL
OUT

SERIAL OUT RBI


The SERIAL OUT pin is a shift register serial output The RBI PIN is an input pin for suppressing the
pin. The data input to the SERIAL IN pin is output display of leading Os. When this pin is at high
from this pin synchronised with the clock pulses, level, the leading Os, if any, are displayed; when
with a delay of the total bit count of the shift this pin is at a low level, contiguous Os preceding
register (32 bits), This pin is used for extension the MSD are not displayed. The RBi pin is con-
ot'digit display capacity. nected to the decoder circuit for the MSD.
Note: The DPt through DPs are not made blank.

CLOCK BIJRBO
The CLOCK pin is a synchronizing pulse input The BI/RBO pin is used for both input and output.
pin used for data input to the shift register or data As an input pin, the input level can forcibly be
output from the shift register. The data is shifted set to low regardless of the output level, since the
at the rising edge (low to high) of each clock pulse. output resistance is treat.
A Schmitt trigger circuit is employed as the CLOCK
input circuit (the hysteresis is approximately 0.5V). For use as an output pin RBO
When the RBI pin is turned to low level, if all
the digits are Os, the display is made blank
LOAD and the RBO pin is turned to low level. If the
The LOAD pin is an input pin for latching the shift RBI pin is at high level or a number including
register contents. When this pin is at high level, some significant digits is displayed, the RBO
the shift register contents' are transferred to the pin is turned to high level. If two MSM58292GS
decoders, and ,:",hen this pin is at ,low level, the chips are connected for extension of the digit
last data to be transferred from the shift register display capacity, the RBO pin of the first chip is
when this pin was at high level is held, so that the connected to the RBI pin of the second ch ip,
display contents are not changed with the change which connects to the MSD of the second chip,
of the shift register contents. so that all the continguous Os preceding the MSD
are made blank.

19
STATIC LCD DRIVER MSM58292GS ....- - - - - - - - - - - - - - - - . . , . -

2 For use as an input pin Bi decimal points (DPI-DPsl. and flags (FI and F z )
The Bi pin is connected to the decoder circuit on the display device.
for the LSD. Therefore, if this pin is turned The seven segment outputs (a - g) for each digit
to low level, only the LSD digit is made blank. are used to display a digit 0-9 or an alphabetic
Since this pin is also used as an output pin letter A-F.
ROB, some current indicated in the rating flows
when this pin is set to low level. level.
The Bi pin may be open when not used. e OSC
Note: The DPI through DP s are not made blank. The OSC pin is an input pin for a signal generator
circuit which outputs AC signals required for driving

11 SEGMENT OUT (al-9s, OPI-0PS, F I , Fz)


The SEGMENT OUT pins are output pins for
driving the seven segments of digits (a I - gs),
a LCD panel. The oscillator starts to generate AC
signals only by connecting a resistor and a capacitor
to the OSC pin as shown in the figure below.

f(OSC) = 360 Hz when the VDD = 5V, C = 0.068pF, and R = 100 kn

VDD

R
OSC

C.L
T LSI I>--

COM,COM OUTPUT DISABLE


The COM pin is an output pin for sending an anti- The OUTPUT DISABLE pin is an input pin for
phase signal of the seven segment outputs required control of the COM pin. Setting this pi!) to high
for AC-driving the LCD panel. The COM output level places the COM pin in the normal status (the
drives the COMMON pin on the LCD panel. COM pin is used as an ordinary output pin), and
The COM pin is an output pin for sending an in- setting this pin to low level makes the COM pin
phase signal of the seven segment outputs (antiphase impedance high, so that the COM pin can be used
of the COM pin!. This pin is not necessary in general as an input pin.
display. When two MSM58292GS chips are interconnected
Both the COM and COM pins output square waves in a cascade, the OUTPUT DISABLE pin of the
whose frequency is one eighth of the oscillator second chip is set to low level and the COM pin
output appearing at the OSC pin (with a duty factor is used as an input pin.
of 50%).

20
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM58292GS.

BLANK Blanking a specific digit position


The BLANK pin is an input pin for making the Any given digit position of the 5 digit display can
display blank. Setting this pin to high level makes be made blank by setting the MSM58292GS to
normal display, and setting this pin to low level ON. A specific digit position can be made blank
makes the entire display blank. by setting a bit of the shift register bits 28-32, as
shown in the table below.

Shift register bit setting Digit position which is made blank


Set bit 28 to 1 Digit position with segments as - gs (MSD)
Set bit 29 to 1 Digit position with segments a4 - g4
Set bit 30 to 1 Digit position with ~egments a3 - g3
Set bit 31 to 1 Digit position with segments a2 - g2
Set bit 32 to 1 Digit position with segments al - gl (LSD)

Decimal points Output circuit


A digit position for which a decimal point has been Each output pin consists of a CMOS FET, and the
specified is not subject to zero blanking even though BI/RBO pin and SERIAL OUT pin Ol,ltput signals
that digit position contains the value O. A decimal at high or low level.
point can be used as a flag by setting the blank bit The output pins for display (for segments, decimal
corresponding to that digit position to 1 to suppress points, and flags) output pulse signals which are
the a - g segment display of that digit position antiphase of the COM pin output when displaying,
(when the RBI pin is at low level I. and output pulse signals which are inphase of the
COM pin output when not displaying. The output
pins for display can directly drive the LCD panel.

Output pins

21
STATIC LCD DRIVER MSM58292GS ....- - - - - - - - - - - - - -

Application circuit
I. 10 digit display (using two MSM58292GSs. cascade connection)

(32 - 64 Hz)
COM

LCD
Segment
outPr-u_t_---.:l'--_ _-I

"""' Segment
output

series

+5V
VDD

Note: 0.0 is the abbreviation of OUTPUT DISABLE.

II. 5 digit display

LCD

DO

OLMS-40
series VDD COM

+5V output LOAD


port 1 1 - - - - - - 1 SERIAL (MsM58292Gs)
IN
' + - - - - - - 1 CLOCK
GND VSS OsC

~ __ ~ _________________ +-~~-+-JVV~~ ___ ~ VDD


O.068pF lOOK

Note: 0.0 the abbreviation of OUTPUT DISABLE.

22
- - - - - - - - - - - - - - - t l . STATIC LCD DRIVER MSM58292GS

Data input example (FM 103.25 MHz)

i--!Yi- -l'-- -i!--~j --'I 1;'99()~ r


(MHz)
DP s DP, DP I (FM)
DP DP F F

BCD to BCD to BCDto BCD to BCD to Flag


Dlcimal
7 segment 7,egmenl 7 segment 7 segment 7 segment
pOint
decoder! ~ecoder! decoder! decoder! decoder!
driver driver
driver driver driver driver drlv<?r

8 4 2 , 8 4 2 , 8 4 2 , 8 4 2 , 8 4 2 ,

LOAD
'[2[3[4 5[6[71819[1O['~'2 '1'~ki'~'1'~'912o 21222124[2 261271281291301313~

j 1
SERIA 0 -
'~141'51'61'7 ~81l9120 2,12 2312412512~21~~2~3~3J32
SERIAL
IN
,12131415161718191101,,1,2 OOUl
CLOC~

Input
data
- ~~:~:~:~:O 0 1 0 110.Vla 0 0
I I I I I: 0O.
I / / : 1 " 8 lank datd
I Decimal MHz FM,I
POlllt

SERIALIN~ ____________ SL
I Dat.} setup lime is 250 Il~ or more
,M" "
CLOCK~ ______ _ _______ JL
500
t
os 01 more

LOAD
--------------------~7__ 500 ns 01 1l10re
- - - Shifting direction

23
f!

I\)
.eo m
><
CJ en
3 -I
"'0
-I
(1)
0
...... n
DP s DP 4 DP., DP 1 DP) r-
5" n

r
COM d4 e4 g4 f4 as bs Cs d4 e4 g4 f4 a4 b4 C4 d~ e~ 9.1 1.1 a.l b.1 c, d1 e1 g, I, a, b,C2 d)e)9)I)a)b)cl F)hCOM d e q 1 a b c DP
1 II II II II II 1111111111111,11111 1 II II II II 1 1 II II II II II II 1 1 II II II II Irlr lrlrn lr II 1 .... 0
..,en

WIll!
(") 0
0 :JJ
::l
::l
en <:m
~8 ....
(")

43 4445 46 47 49/5051 5253 54 5556 :JJ


c)"
,
Ii~ ,-
:,-,: ~
::l
~
;:.:
:s:
en
41
2
1-
3
Example of output pin connection to ::r :s:
U1
L-- I---- a digit of LCD. r- 00
L---
40 4 n N
39 5
0 CO
N
'----JB 6
G)
en
37 MSM58292GS 7
36 (view from the bottom) 8
35 9 PCB
34 10
3:J 11
MSM58292GS
32 12
Note: The LCD is mounted on the rear, and
31 13 the MSM58292GS is mounted on the
30 14 top. It is necessary to bore a hole
through the PCB in which to place
29
the MSM58292GS.

p8i7 P

I~ '~il 0 0
0 0 ..J
> ..J u
u
(/)
0>
(/)
(/)
OKI semiconductor
MSM5219BGS
48DOT STATIC LCD DRIVER

GENERAL DESCRIPTION
The OK I MSM5219BGS is a 48 dot static LCD driver which is fabricated by low power CMOS metal gate technology.
This LSI consists of 48bit shift register, 48bit latch and 48bit LCD driver. The display data, which was input to the
48bit shift register, is shifted to the 48bit latch by the LOAD signal. Then the data is output to the LCD panel
through the 48bit LCD driver.

FEATURES
48 dots static LCD driving capability LCD driving AC frequency is directly input exter-
Simple interface with microcomputer chip (con- nally
trolled by three input signals) Applicable as an output expanrler
Bit-tobit correspondence between the input and Supply voltage: 3 -7V
the output 60 pin plastic flat package (bent lead)
Cascade connection capability

PIN CONFIGURATION
(Top View) 80 Lead Plastic Flat Package

C/J en en C/J en en en en en Vl en Vl Vl Vl Vl
m m m m m m m m m m m m m m m

~ ~ *~ 3 ~ ~ ~
o ~ ~ ~ ~ ~

LOAD SEG32

SEG31

DATAIN SEG30

SEG29

SEG28

GND SEG27

VDD SEG26

SEG25

SEG24

ALL ON SEG23

BLANK SEG22

COM SEG21

SEGl SEG20

SEG2 SEG19

Vl Vl Vl Vl Vl Vl Vl Vl C/J en C/J C/J C/J en


m m m m m m m m m m m m m m
8 ~ ~ Cl
C1l 8 5l fJ ~
o
~ :: Cl
w
~ Cl
~
'" '" C1l

25
STATIC LCD DRIVER MSM5219BGS .
---------------

BLOCK DIAGRAM
LCD driving output
~~----------~'~------~----~"

BLANK
ALLON
F
I
SEG 1

LCD Driver & EOR


w-__________~~------------~
SEG48

LOAD ~~-------4-8-.-b-it-D-a?ta~La-t-c-h----------~
DATA IN 48bit Shift Register DATA OUT 48

CLOCK DATA OUT 32

COM

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Limits Unit


Supply voltage VDD - VSS Ta = 25C -0.3 -+7 V
Input voltage VI Ta = 25C VSS - 0.3 -VDD + 0.3 V
Storage temperature T stg - -55-+150 c

OPERATING RANGE

Item Symbol Condition Limits Unit


SelfOsciliation circuit 4-7 V
Supply voltage VDD - VSS
External oscillation 3-7 V
Operating temperature Top - -40-+85 c

26
----------------11. STATIC LCD DRIVER MSM5219BGS-

DC CHARACTERISTICS
(Voo - VSS = SV. Ta = -40 -+8SoC)

Item Symbol Condition MIN TYP MAX Unit


"H" Input voltage* 1 VIH - 3.6 - - V
"L" Input voltage* 1 VIL - - - 1.0 V
Input leakage current* 1 IIH/IIL VI = SV/VI = OV - - 1/-1 Jl.A
SEG "H" Output voltage VOHS 10 = -30Jl.A 4.8 - - V
SEG "L" Output voltage VOLS 10 = 30Jl.A - - 0.2 V
COM "H" Output voltage VOHC 10 = -lS0Jl.A 4.8 - - V
COM "L" Output volta!le VOLC 10 .. lS0Jl.A - - 0.2 V
-100/
SEG Output current 1 IOHS1/ I OLSl VOH = 4.SV/VOL = O.SV - - Jl.A
100
-400/
SEG Output current 2 IOHS2/10LS2 VOH = lV/VOL = 4V 400
- - Jl.A

COM Output current 1 = 4.SV/VOL = O.SV


-soot - -
IOHC1/ I OLCl VOH
500
Jl.A

COM Output current 2 IOHC2/ I OLC2 VOH = lV/VOL = 4V -2/2 - - rnA


"H" Output voltage*2 VOH 10 = -40Jl.A 4.2 - - V
"L" Output voltage*2 VOL 10 = 1.6mA - - 0.4 V
-0.2/
Output current*2 10H/IOL Vo = 2.5V/V0 = O.4V
1.6
- - V

*3 5 - -
Clock pulse width tw J1.S
*4 O.S - -
*3 0.1 - -
Max. clock pulse frequency fMAX MHz
*4 1 - -
Input signal rising/falling time t r. tf *5 - - 5 J1.S
Static current consumption 1001 - - - 100 Jl.A
No load when
Active current consumption 1002 ROSC = 150 kn. - - 2 rnA
COSC = 0.015 Jl.F
COM Frequency
(Self oscillation) fCOM No load when VOO = 5V 25 - 300 Hz

*1: Applicable to all terminals except OSC. This condition is applied to OSC in the external oscillation mode.
*2: Applicable to DATA OUT 32. DATA OUT 48.
*3: Applicable to OSC.
*4: Applicable to CLOCK.
*S: Applicable to all terminals except OSC terminal.

27
STATIC LCD DRIVER MSM5219BGS ....- - - - - - - - - - - - - -

FUNCTIONAL DESCRIPTION
Operational Description to the 48-bit latch by the LOAD signal and it is
The display data is input to the shift register by the output to the LCD panel through 48-bit LCD
DATA IN signal and CLOCK signal. It is transferred driver.

DATA IN

CLOCK

LOAD

DATA LATCH output


(inside LSI)

o CLOCK 2 BLANK
The clock, which is used to generate the COM When this pin is set at high level, all segments display
signal and the LCD driving signal, is input to this turn off. The ALL SEG ON pin has the priority
pin. over this pin.

DATA IN CLOCK l o SEG 1 - SEG48


DATA I N is a data input pin which enables the LCD driving output pins. The reversed phase of the
LCD to display when DATA I N pin is at high level. COM signal, which is used to display the data, is
The 48-bit shift register is shifted at the rising edge output from these pins when SEGl - SEG48 are
of the CLOCK signal. Initially, the first bit of the set at high level, while there is no' display on the
shift register contains the current logic level of the LCD when these pins are set at low level. The
DATA IN pin, and the bit N (N = 2 - 48) contains data which was input from the DATA IN pin is
the data which was in bit N - 1 (N = 2 -48) before output from these pins to the LCD panel. The
the start of the operation. The data which was SEG N pin corresponds to the bit N of the shift
in bit 48 before the operation start is considered register.
invalid.
COM
o LOAD Output terminal for the LCD. It is connected to the
The data in the 48-bit shift register is shifted to the common side of the LCD.
48-bit latch when the LOAD pin set at high level,
while the last data which was transferred to the DATA OUT 32, DATA OUT 48
latch when the LOAD pin was set at high level is Output pin of the shift register. It is used when the
constantly output when the LOAD pin is set at MSM5219BGS is connected in a series (cascade
low level. connection). It is connected to next MSM5219BGS's
DATA IN terminal.
ALL SEG ON
When this pin is set at high level, all segments display
turn on. This pin has the priority to the BLANK
pin described as below.

28
- - - - - - - - - - - - - - - t I . STATIC LCD DRIVER MSM5219BGS.

APPLICATION CIRCUIT
Single MSM5219BGS

LCD (Static) f--

>
- ---- --------- 1 >
<>
-"'. BLANK
SEG1 SEGN SEG48
" ALL ON
" LOAD COM -
"DATA IN MSM5219B
_,CLOCK,
CLOCK 2

I
*1: When this IC is used under a strong external noise or large-capacity LCD load, this resistor prevents latch-up to
be caused by a low output impedance of the COM pin.
The resistance is about lOOn.

Cascade connection

LCD (Static)
~
BLANK SEG1
t ~ 48 -
t
SEGl - 48
*1
*2
.---
.----
t
I
SEG1 - 48
*1

*2
ALL ON
LOAD Master r:o" 0
,---
- Siove
COM
- Sldve
COMU
l
DATA IN DATA (lIlT LID
CLOCKI CLOCK, CLOCK2
CLOT'
1 1 --

*1: The COM pin of the slave MSM5219BGS can be WI RED OR.

*2: When this IC is used under a strong external noise or large-capacity LCD load, this resistor prevents latch-up to
be caused by a low output impedance of the COM pin.
The resistance is about lOOn.

29
STATIC LCD DRIVER MSM5219BGS .....- - - - - - - - - - - - - -

Output Expander
As explained above, this I C can drive the static used as an output pin expander for a microcomputer
LCD with the COM pin. In addition, it can also be with the following connections:

r--------,
I I
r--------l r--- --- --..,
I I
: LED driv.!r
L ______ J
I :
IL _______
F L T driver
...J
I
: lL Relay driver
_______
:
oJ
l L
\,

,---
~~---IBLANK SEG1 - 48 - r-----
. ~ t--1rl>---i A L LON r---- -
f t--1H-.......-ILOAD r--
I-t-+-+--i
- :-- ---
~ 8 ~H--+---iDA TAl N OU T 48
______ t--1H--+-~~.C_L_O_C_K~I_~C~L~O~C~K.,~

+*1 + *1 +*1

*1: In this example, "H" is output by the positive logic, that is, when "H" is written from DATA IN, "H" is output
with a LOAD signal. If the OSC pin is connected to VDD, the output has the negative logic, that 1s, the logic
level input from the DATA I N pin is inverted and output.

30
OKI semiconductor
MSM5221GS
56-DOT STATIC LCD DRIVER

GENERAL DESCRIPTION
The OKI MSM5221GS is a 56 dot static LCD driver which is fabricated by low power CMOS metal gate technology.
This LSI consists of 56-bit shift register, 56-bit latch and 56-bit LCD driver. The display data, which was input to the
56-bit shift register by the DATA IN signal and CLOCK signal, is transferred to the 56-bit latch by the LOAD signal
and the data is output to the LCD through the 56-bit LCD driver.

FEATURES
56 dots static LCD driving capability Fully controlled by the software
Simple interface with microcomputer chip (control- LCD driving AC frequency is directly input exter-
led by three input signals) nally
Bit-to-bit correspondence between the input and Applicable as an output expander
output Supply voltage: 3 -7V
Cascade connection capability 80 pin plastic package (bent lead)

PIN CONFIGURATION
(Top View) 80 Lead Plastic Flat Package

(f) (f) (f) (f) (f) (f) (f) (f) (f) (f)
'"m m'" '"m
(f) (f) (f) (f)
m m m m m m m m m m m m m m '"
m

~ ~ ~ ~ ~ ~ ~ ~ z
()
z
()
z ()
n
z ()
z z
.() ~ t ~ ~ ~ ~
0 ~ 8 (Xl

SEG56 25 SEG37
LOAD
CLOCK SEG36
SEG35

.DATA IN SEG34
NC SEG33
DATA OUT 56 SEG32
COM IN SEG31
vDD SEG30
NC SEG29

VSS SEG28
ALL SEG ON SEG27
BLANK
SEG26
COM OUT SEG25
SEG 1 SEG24
SEG 2

SEG 3 0 SEG23
SEG22

(f)
m
(f)
m
en
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m z z z z Z 2 (f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
() () () () () n
~ ~ g) 8 ~ f2 Cl ~ ~ ~ ~ ~ ~ ~
'"' ~
Cl
~ 8
0 tV W .... (Xl
'" C'>
(]1

31
STATIC LCD DRIVER MSM5221GS ...- - - - - - - - - - - - - -

BLOCK DIAGRAM

Output to the LCD panel


r~--------~A~--------~l
SEGl - - - -- --- - SEG56
BLANK ,..---0------ - -,

ALLS:::: i
I

DATA IN DATA OUT 56

CLOCK

COM IN COM OUT

VDD

VSS
t--
t::.-

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Limits Unit


Supply voltage VDD':"" VSS Ta = 25C -0.3 -+7 V
Input voltage VI Ta = 25C VSS - 0.3 - VDO + 0.3 V
Storage temperature T stg - -55-+150 c

OPERATING RANGE

Item Symbol Condition Limits Unit


Supply voltage VDD - VSS - 3-7 V
Operating temperature TOp - -40-+85 c

32
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5221GS.

DC CHARACTERISTICS
(VDD-VSS=sv. T a =-40-+8SoCI

Item Symbol Condition MIN TYP MAX Unit


"H" Input voltage VIH - 3.6 - - V
"L" Input voltage VIL - - - 1.0 V
Input leakage current IIH/IIL VI = SV/VI = OV - - 1/-1 J1A
"H" SEG Output voltage VOHS 10 = -30J.lA 4.8 - - V
"L" SEG Output voltage VOLS 10 = 30J.lA - - 0.2 V
"H" COM Output voltage VOhC 10 = -lS0J.lA 4.8 - - V
"L" COM output voltage VOLC 10 = lS0J.lA - - 0.2 V
-100/
SEG Output current 1 IOHS1/ I OLSl VOH = 4.SVIVOL = O.SV
100
- - J.lA

-400/
SEG Output current 2 IOHS2/ I OLS2 VOH = lV/VOL = 4V
400
- - J.lA

-SOO/
COM Output current 1 IOHC1/ I OLCl VOH = 4.SVIVOL = O.SV - - J.lA
SOO
COM 04tput current 2 IOHC2/ I OLC2 VOH = lVIVOL = 4V -2/2 - - mA
"H" Output voltage* 1 VOH 10 = -O.lmA 4.S - - V
"L" Output voltage* 1 VOL 10 = O.lmA - - O.S V
Clock pulse width * 2 tWcjJ - O.S - - J1S
Maximum clock pulse
frequency * 2 fcjJMAX - 1 - - MHz

Input signal rising/falling time trcjJ. tup - - - S J1S


Static current consumption IDD VIN = VDD. VSS - - 100 J.lA

*1: Applied to DATA OUT S6.


*2: Applied to the clock for shift register.

33
STATIC LCD DRIVER MSM5221GS ....- - - - - - - - - - - - - - -

FUNCTIONAL DESCRIPTION
Operation Description
The display data is input to the shift register by the to the 56-bit latch by the LOAD signal and it is
DATA I N signal and CLOCK signal. It is transferred output to the LCD panel through 56-bit LCD driver.

CLOCK

LOAD
DATA LATCH output
(inside LSI)

COMIN BLANK
Input pin to generate the COM OUT signal. The When this pin is set at high level, all segments display
same phase signal as the COM IN pin is output turn off. The ALL SEG ON pin has the priority
from the COM OUT pin. over this pin.

DATA IN, CLOCK SEG1 -SEG56


DATA IN is a data input in which enables the LCD LCD driving output pins. The reversed phase of the
to display when DATA IN signal is at high level. COM signal, which is used to display the data, is
The 56-bit shift register is shifted at the rising edge output from these pins when SEG1 - SEG56 are
of the CLOCK signal. Initially, the first bit of the set at high level, while there is no display on the
shift register contains the current logic level of the LCD when these pins are set at low level.
DATA IN pin, and the bit N (N = 2 - 56) contains The display data which was input from the DATA
the data which was in bit N - 1 (N = 2 - 56) before IN pin is output from these pins to the LCD panel.
the start of the operation. The data whi~h was in bit The SEG N pin corresponds to the bit N of the shift
56 before the operation start is considered invalid. register.

LOAD COM OUT


The data in the 56-bit shift register is shifted to the Output terminal for the LCD. It is connected to the
56-bit latch when the LOAD pin is set at the high common side of the LCD panel.
level, while the last data which was transferred to
the latch when the LOAD pin was set at high level DATAOUT56
is constantly output when the LOAD is set at low Output pin of the shift register. It is used when the
level. MSM5221 GS is connected in a series (cascade
connection). MSM5221GS's DATA OUT 56 is
ALL SEG ON connected to the next MSM5221GS's DATA IN
When this pin is set at high level, all segments display terminal.
turn on. This pin has the priority to the BLANK
pin described as below.

34
- - - - - - - - - - - - - -..... STATIC LCD DRIVER MSM5221GS.

APPLICATION CIRCUIT
Single MSM5221GS to the LCD panel

t-
LCD panel (static)

>
- -- -- - - - --- ---- <-~

SEG 1 SEG N SEG 56


BLANK
ALL SEG ON
LOAD MSM5221GS COM OUT r--

DATA IN
CLOCK
COM IN

COM IN --------------------------------~

RI: A resistor is provided to prevent latch up as required.

Cascade connection

LCD panel (static)

MSM5221GS
--
> MSM5221GS MSM5221GS
56 R, ~ 56 ~
RI > ,
56 R,
>
?
~
BLANK r-- ;--
-r- SEGI - 56
~r----- SEGl - 56
SEGI - 56
- -
ALL SEG ON
LOAD
DATA IN
-
- r-
~
~
COM OUTr----

0.0.56
COM OUT

0.0.56
-
r--- COM OUT 1--'

CLOCK r- COMIN r- COM IN


- COM IN

COMIN t t t ----

--
- ---
--
-

RI: Same as RI in (1).

35
OKI semiconductor
MSM5265GS
l60-DOT LCD DRIVER

GENERAL DESCRIPTION
The OKI MSM5265GS is an LCD driver which can directly drive up to 80 segments in the static display mode, while
it can directly drive up to 160 segments in the 1/2 duty dynamic display mode.

The MSM5265GS is fabricated by low power CMOS metal gate technology, consisting of 160stage shift register,
160-bit latch, 80 sets of LCD driver and a common signal generator.

The display data is serially input from the DATA-IN terminal to the 160-stage shift register synchronized with the
CLOCK pulse. The data is shifted to the 160-bit latch by the LOAD signal. Then the latched data is directly output
to the LCD from the 80 sets of LCD driver as serial output.

The common signal can be generated by the on-chip generator, or can be externally input. The common synchroniza-
tion circuit which is used in the dynamic display mode is integrated on the chip.

FEATURES
80 segments display drive (in the static display mode) Can be synchronized with the external common
160 segments display drive (in the dynamic display signal
mode) Testing terminals for all-on (SEG-TEST) and all-off
Simple interface with microcomputer (BLANK)
Bit-to-bit correspondence between input data and Applicable as an output expander
output data LCD driving voltage can be adjusted by the com-
H : Display L : No display bination of VLCl and VLC2
Cascade connection capability Supply voltage: 3.0'" 6.0V
On-chip common signal generator 100 pin plastic flat package (bent lead)

PIN CONFIGURATION
(Top View)

36
- - - - - - - - - - - - - - - - 1 1 . STATIC LCD DRIVER MSM5265GS.

BLOCK DIAGRAM

To LCD panel

VDD

GND

LOAD

DATA-IN DATA-OUT2

34
DATA-OUT1
DIS

O"SC-ODT

OSC-OUT
48
OSC-IN COM-A
Oriver
49
EXTIINT COM-B
46
SYNC COM-OUT

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Limits Unit


Supply voltage VOD Ta = 25C - 0.3 -+6.5 V
I nput voltage VI Ta = 25C GND - 0.3 - VDO + 0.3 V
Storage temperature Tstg - - 55-+ 150 c

37
STATIC LCD DRIVER MSM5265GS 11-.- - - - - - - - - - - - - -

OPERATING RANGE

Item Symbol Condition Limits Unit


Supply voltage Voo - 3-6 V
Operating temperatu re TOp - -40-85 c
LCO driving voltage VOO - VLC2 - 3 - V OD V

RECOMMENDING OSCILLATION CIRCUIT CONDITION

Item Symbol Corresponding pin Condition MIN TYP MAX Unit


Oscillator
resistance
Ro 00 OSC-OUT - 56 100 220 kn

Oscillator
capacitance
Co [ll] OSC-OUT Film capacitor 0.001 - 0.047 J.lF

Current limiter
resistance
RI 00 OSC-IN RI ~ 10 Ro 0.56 1 2.2 Mn

Common signal [}[] COM-A


frequency fCOM
[}[] COM-B
- 25 - 150 Hz

38
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5265GS.

D.C. CHARACTE R ISTICS


(VDD = S.OV Ta= -40-+8SoCI

Item Symbol Corresponding pin Condition MIN TYP MAX Unit


"H" Input
VIH
~ SEG-TEST
- 3.6 - - V
voltage
~ BLANK
[ill LOAD
"L"lnput
V1L
~ DATA-IN
- - - 1.0 V
voltage
~ CLOCK
@] DIS
Input
~ EXT/INT
leakage IlL @ill OSC-IN VI = S.OV/OV - - 1 p,A
current
"H" Output
@1l DATA-OUTl
voltage VOH @] DATA-OUT2 10 = -100p.A 4.S - - V
@ill COM-OUT

[m OSC-OUT
~ OSC-OUT 10 = -200p.A 4.S - - V

[Q]-[!QQ] OJ-@Q] VLC1 = 2.SV VLC2 = OV 4.8 - - V


output of all segments 10 = -30p.A

@ID COM-A VLC1 = 2.SV VLC2 = OV 4.8 - - V


~ COM-B 10 = 150p.A

"M"Output @ID COM-A VLC1 = 2.SV VLC2 = OV 2.3 - 2.7 V


voltage VOM @J COM-B 10 = 150p.A

"L" Output
~ DATA-OUTl

voltage VOL ~ DATA-OUT2 10 = 100p,A - - O.S V


[J COM-OUT

em OSC-OUT
10 = 200p,A - - O.S V
@ill OSC-OUT

[ill-ITOOl [J]-I]Q] VLC1 = 2.SV VLC2 = OV - - 0.2 V


Output of all segments 10 = 30p,A

@m COM-A VLC1 = 2.SV VLC2 = OV - - 0.2 V


@g) COM-B 10 = 150p,A

@ SYNC 10 = 250p,A - - 0.8 V

Output Vo = SV - - S p,A
leakage ILO ffi] SYNC
when internal Tr is off
current

Segment [ill-[QQJ [I]-@Q] VLC1 = (S + VLC2"2 - - 10 kn


output RSEG VLC2 = 0 -2V
Output of all segments
impedance

39
STATIC LCD DRIVER MSM5265GS - - - - - - - - - - - - - - -

Item Symbol Corresponding pin Condition MIN TYP MAX Unit


Common output
RCOM
~ COM-A VLC1 = (5 + VLC2)/2
- - 1.5 k!1
impedance ~ COM-B VLC2=0-2V
Static mode Set all input level
IDDl 100 J.LA
consumption current either "H" or "L"
Dynamic mode
~ VDD
No load oscillation.
consumption current IDD2 Ro = 100 k!1, 0.12 0.5 mA
Co = 0.01 J.LF, R 1 = 1M!1

11 SWITCHING CHARACTERISTICS
0
(VDD=3.0-6.0V Ta =-40-+85 C)

Item Symbol Corresponding pin Condition MIN MAX Unit

Maximum clock frequency f</>MAX - 1 - MHz


Clock "H" time tH - 0.3 - J.Ls
Clock "L" time t</>L [B] CLOCK - 0.5 - J.Ls
Clock pulse rising/ tqf - - 0.1 J.Ls
falling time t</>t
Data setup time to-ef> ~ DATA-IN - 0.1 - J.Ls
Data hold time t</>-D ~ CLOCK - 0.1 - J.Ls
"H", "L" propagation tpHL
[W DATA-OUTl When 15PF output
delay time tpLH
[]]] DATA-OUT2 capacitors are locaded - 0.8 J.Ls
[ll] CLOCK ~ and ~.
LOAD "H" time width tL [ll] LOAD - 0.2 - J.Ls
CLOCK ~ LOAD time t</>_ L tEj CLOCK
LOAD
- 0.1 - J.Ls
OSC-IN Maximum
input frequency fOSCMAX ~ OSC-IN - 5 - kHz

SYNC "L" time width ts (] SYNC - 0.2 - J.Ls

33 DATAI~,I

32 C'_OCK

31 LOAD

34 DA T A-OUT 1

35 DATA-OUT2

45 SYNC

(VH = 0.8 VDD, VL = 0.2 VDD)

40
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5265GS.

FUNCTIONAL DESCR IPTION


Operational description
The MSM5265GS consists of 160-stage shift register, CLOCK pulse and it is shifted to the 160-bit latch
160-bit latch, and 80 sets of LCD driver_ The display when the LOAD signal is set at "H" level, then it
data is input from the DATA-IN terminal to the is directly output to the LCD panel from the 80 sets
160-stage shift register at the rising edge of the of LCD driver_

DATA-IN

CLOCK

LOAD -------------~H\r-_------In'---
r----
DATA L A T C f . i I I - - - - - - - - - - - - - - - - - - - f ( ( I f - - - - - - - - ,
fi~~?~~
the IC) X..____ )}

OSC-IN, OSC-OUT, OSC-OUT


By connecting the external registors R o , R I and from the COM-OUT terminal. (EXT/INT should be
external capacitor CI with OSC-I N, OSC-OUT and set at low level.)
OSC-OUT respectively as shown in the figure below, The resistor RI is to limit the current on the OSC-IN
an oscillating circuit to generate the common signal terminal's protecting diodes. The value of the R I
is formed_ should be 10 times more than that of Ro-
This frequency is divided into either 1/8 or 1/4 by When the external common signal is used, the EXT/
the internal dividing circuit. The 1/8 divided fre- INT terminal should be set at high level and the
quency is used in the static display mode, while external common signal should be input from the
the 1/4 divided frequency is used as the common OSC-IN terminal.
signal in the dynamic display mode which is output

fOSC = 1/2.2 CoRo

fOSC

41
STATIC LCD DRIVER MSM5265GS - - - - - - - - - - - - - - -

DIS DATA-OUT!
When this pin is set at high level, the MSM5265GS The 80th stage of the shift register contents is
operates in the dynamic display mode, while it output from this pin.
operates in the static display mode when this pin When more than two MSM5265GSs are connected
is set at low level. in a series (cascade connection) in the static display
mode, this pin should be connected to the next
EXT/INT MSM5265GS's DATA-IN terminal.
When the external common signal is used, this pin
should be set at high level and the external common
signal is to be input from the OSC-I N terminal. DATA-OUT2

11 The input common signal is used same as the internal


common signal and is output from the COM-OUT
pin through the buffer_
When the on-chip common signal generator is used,
The 160th stage of the shift register contents is
output from this pin.
When more than two MSM5265GSs are connected
in a series (cascade connection) in the dynamic
this pin should be set at low level. display mode, this pin should be connected to the
When the MSM5265GS is used as an output next MSM5265GS's DATA-IN terminal.
expander, this pin should be set at high level and
the OSC-IN pin should be set at low level.
LOAD
The signal for latching the shift register contents is
COM-OUT
When more than two MSM5265GSs are connected input from this pin.
in a series (cascade connection), this pin should be When LOAD pin is set at high level, the shift register
connected with all of the slave MSM5265GS's contents is shifted to the 80 sets of the LCD driver.
OSC-IN terminal. When this pin is set at low hivel, the last display
data, which was transferred to the 80 sets of LCD
driver when LOAD pin was set at high level, is held.
SYNC
This pin is an input/output pin which is used when
more than two MSM5265GSs are used in a series
(cascade connection) in the dynamic display mode_ VLC2
Supply voltage pin for the 80 sets of LCD driver.
All of the involved MSM5265GS's SYNC pins
The input level to this pin should be the low level
should be connected in a same line so that they
output voltage of segment output (SEG1 -SEG80)
should be pulled up by the common resistor, which
and common output (COM-A, COM-S).
makes phase level of all involved MSM5265GS's
In this case, the high level of segment output and
COM-A terminals and COM-B terminals equal.
common output is VDD level, while low level of
When single MSM5265GS is used in the dynamic
segment output and common output is VLC2 level.
display mode, SYNC should be pulled up by the
V LC2 should be set at more than ground level.
resistor.
In the static display mode including single
MSM5265GS's operation, cascade connection and VLCl
output expander operation, this pin should be set Supply voltage pin for the middle level voltage of
at ground level. the common output. The input level of this pin
is the middle level output voltage of the common
DATA-IN, CLOCK output (COM-A, COM-B) in the dynamic display
The display data is serially input from the DATA- mode.
I N terminal to the 160-stage shift register at the The value of the VLC1 is calculated by the following
rising edge of the CLOCK pulse_ The high level of formula.
the display data is used to turn the display on, VLC1 = (VDD + VLC21/2
while low level of the display data is used to turn In the static display mode, this pin should be set at
off the display. open level.

42
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5265GS.

COM-A, COM-B
LCD driving common signal is output from these In the select mode the, same phase level as the
pins and these pins should be connected to the COM-OUT signal is output.
common side of the LCD panel. In this case, VOO or VLC2 is output at high
level or low level respectively_ In the non-select
In the static display mode
mode, VLCl is output at the middle level.
Same phase pulse as COM-OUT terminal is
In the select mode of COM-A (non-select mode
output from both of COM-A and COM-B. In
of COM-B), the 1st ,..., 80th latched data contents
this case high level is VOO level and low level
are output from the 80 sets of LCD driver to
is VLC2 level.
the LCD panel.
In the dynamic display mode In the select mode of COM-B (non-select mode
The COM-A and COM-B output signal are of COM-A), the 81st '" 160th latched data
alternately changed within each COM-OUT contents are output from the 80 sets of LCD
output cycle, resulting in alternately repetition driver to the LCD panel.
of select and non-select modes.

Dynamic display mode Static display mode


(O/S: H) (O/S: L)

COM-OUT

- JlJlJl
---Jl-Jl-J
VOO
COM-A - VLCL

- - VLC2

rL rL n ~ _~::1 - n n n
uu
COM-B .

U=---VLC2~ U U I

43

i
/
STATIC LCD DRIVER MSM5265GS . - - - - - - - - - - - - - - -

SEG 1 '" SEG80


LCD segment driving signal is output from these In the dynamic display mode
pins and these pins should be connected to the Output of the SEG N corresponds as follows.
segment side of the LCD panel.
When COMA is select mode:
"H" level : VDD level, "L" level : VLC21evei Nth bit of the latched data contents
In the static display mode
When COMB is select mode:
Since the Nth bit of the latched data contents
(SO + N)th bit of the latched data contents
corresponds to the SEG N, the data after S15t
bit is invalid for the display in the static display When the display turns on, the inversed phase

IJ
mode. signal as the common signal is output, while
The inversed phase signal as the COMOUT the same phase signal as the common signal is
signal is output to the LCD, when the display output when the display turns off.
turns on, while the same phase signal is output
when the display turns off.

Dynamic display mode Static display mode


(DIS: H) (DIS: L)

COMA COMA

COMB COMB

, I I
3UU1SI
SEG N
:J-+l1J-fL
Off On I Off On
SEG N
Off

~ On

fn 10n On

ISO+N N N

SEGTEST BLANK
This pin is used to test the segment output (SEG 1 '" This pin is also used to test the segment output
SEGSO)' All display turn on when this pin is set at (SEG1 '" SEGSO). All display turn off when this
high level, while the display becomes the same pin is set at high level, while the display becomes the
condition before this pin was set at high level, when same condition before this pin was set at high level,
this pin is set at low level. This pin has the priority when this pin is set at low level.
over BLANK terminal. When SEGTEST pin is set at high level, the input
on this pin is invalid.

44
- - - - - - - - - - - - - - - - - . - STATIC LCD DRIVER MSM5265GS-

APPLICATION CIRCUIT

1) Single MSM5265GS operation in the static display mode.

LCD panel
COM ~
80 segments (static)

- - - - - - - - - RCOM
.
SEG 1 - -- - - - - - - - SEG 80
SEG-TEST
. BLANK COM-A f--

From LOAD MSM5265GS


controller VLC2

1
DATA-IN

CLOCK
SYNC
r--
DIS EXT/INT OSC-IN OSC-OUT OSC-OUT VLC 2

77" 7~
>RI
1Mn
lco .. Ro

100kn. TJ'r
To01/1F

2) Single MSM5265GS operation in the dynamic display mode.

COM-B I---
LCD panel
80 x 2 segments (dynamic)
COM-A I - - V DD
~7

>
- - - - - - - - - RCOM
x2 ')
>
>

- - - - - - - - - SEG 80
~
. SEG-TEST
SEG 1

VLC1

COM-A 1 -
BLANK
~
From
controller
LOAD MSM5265GS COM-B I---
DATA-IN VLC2

CLOCK SYNC "-- 7


DIS EXT/INT OSC-IN OSC-OUT OSC-OUT VL C2

1
).
)-
22k

Voo T RI
1Mn
lco
TO.01/1F
Ro
100kn

45
~
.j:>o
en ~
en
Q ~
~
Cl
Q.

~
CD
n C")
0
::I
::I r-
CD C")
~
0' C
::I
C
2- :0
LCD panel (80 x n segments) static
3:
en
3:
U1
<
m
N :0
COM en
U1
G')
~
s:
en
r
VLC2
VLC2

80
RCOM
80
RCOM
80
RCOM
---- ..:j'
=r
CD
~
~
s:U1
N
m
U1
n' G)
Q. en
SEG-TEST COM-A COM-A
~'
iii'

VLC2 <
BLANK MSM5265GS VLC2 MSM5265GS
3
0
COM-OUT Q.
LOAD !II
DATA-IN DATA-OUT 1 DATA-IN DATA-OUT 1
:e
~
~
AI
C.
GI
n
0
:::I
:::I
GI
g.

(
0
:::I

LCD panel (160 x n segments) 1/2 duty dynamic 2-


VOO s:
(I)
COM-A COM-B s:U1
I\J
RLC en
U1
C)
- VLCI ~
RLC --
-- :,.
_ VLC2 ~
.~COM '~O 'I-- 80 GI

.> RCO~
'1'80 RCOM
RCOM:> ~ RCOM RCOM } C.
VLC2 : c
<:::I
AI
3
SEG-TEST COM-A f- ..--- COM-A I - .--- COM-A I- 0"
c.
BLANK MSM5265GS CO~I-B I--- roo- MSM5265GS
COM-B I - - .---- MSM5265GS COM-B
~ ~"
Qj
LOAD COM-OUT '"-- r-- r-- <
3 en
DATA-IN DATA-OUT 2 DATA-IN DATA-OUT 2 DATA-IN DATA-OUT 2 :..-- -- 0
c. -i

!D
CLOCK SYNC I- r- SYNC ~ ..-- SYNC l -
:::!
OIS EXT/INT ~ DIS EXTIINT OSC-IN DIS EXTIINT OSC-IN (")

tJ lW~~c
22kn
rol I fool 1
-- --
r-
(")
C
C
:0
<:
m
- - :0
- -
- -
-- s:en
~
(.TI
N
en
(.TI
C)
:. en
....

~
STATIC LCD DRIVER MSM5265GS . - - - - - - - - - - - - - - -

5) Output-expander

80 outputs (same logic as input data)

SEG 1 - - - - - - - - - - SEG 80

SEG-TEST

BLANK
From
LOAD MSM5265GS
controller
DATA-IN

--11----1 CLOCK

*The output logic can be reversed in respect to the input data by setting OSC-I N to "H" level.

48
DOT
MATRIX
LCD
DRIVER
OKI semiconductor
MSM5238GS
DOT MATRIX LCD 32 DOT COMMON DRIVER

GENERAL DESCRIPTION
The OKI MSM5238GS is a dot matrix LCD's common driver LSI which is fabricated by low power CMOS metal gate
technology. The scanning signal in one matrix display frame can be divided into up to 1/32 duty. This LSI consists
of 32-bit shift register, 32-bit level shifter and 32-bit 4-level driver.

This LSI can drive a variety of LCD panel because the bias voltage, which determines the LCD driving voltage, can be
optionally supplied from external source.

FEATURES

Supply voltage: 3 "'7V Bias voltage can be supplied externally


LCD driving voltage: 3 "'16V 44 pin PLASTIC FLAT Package
Applicable LCD duty: 1/32 "'1/64
(Two chips of MSM5238GS are required to drive 1/64
duty LCD panel).

PIN CONFIGURATION
(Top View)

1
O2

03
0 0.12

0.11

0.10

04 0 29

0 28
o~

0 6 027

0 7 026

0 25
as
0 9 0 24

023

0 22
all

0 0
..
0 0
'" 0
0 0 0
.,
0
c:-
5 0
o
o
~

*Pin 17 is an auxiliary pin. It shall be connected to the power supply or disconnected to any other terminal.

50
------------_i_ DOT MATRIX LCD DRIVER MSM5238GS-

BLOCK DIAGRAM

01
...-------0-- - - - - - - - - - - - - - - - - - - -0----....,
Voo
VI o---t---i
V 1 o----I-~ 32bit 4 Level OriVer
V 1 o---t----i
Voo
VEE(V 4 )cr~----Lr_------__::::;:::oo-==:__------..J

OFo-_ _ _...J

VSS
01
32bit Shift Register

CP

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Limits Unit


Supply voltage VOO -0.3 -7 V
Supply voltage VOO - VEE Ta = 25C 0-16 V
I nput voltage VI -0.3 -VOO V

Storage temperature Tstg - -55 -+ 150 c

OPERATING RANGE

Item Symbol Condition Value Unit

Supply voltage VOO - 3-7 V

Supply voltage VOO - VEE - 3 "'16 V


U
Operation temperature Topr - -40"'+ 85 c
Fanout N MaS load 5 -

51
DOT MATRIX LCD DRIVER MSM5238GS - - - - - - - - - - - - -

D.C. CHARACTER ISTICS

Condition Limits
Item Symbol Unit
VOO VSS VEE
MIN TYP MAX
(V) (V) (V)

"H" *1 0- 3.6/
5 0
-9
-
4.2
- -
input VIH 1/
V
voltage VIH 2 0- 5.2/
7 0 - - -
-7 6.0

"L" *1 0- 0.8/
5 0
-9
- - - 0.4
input VILli V
voltage VIL2 0- 1.1/
7 0 -
-7 0.5
Input IIH 7 0 -7 VI = 7V - - 1
IlA
voltage IlL 7 0 -7 VI = OV - - -1
0-
"H" 5 0
-9
100 = -401lA 4.2 - -
*2
output V
voltage VOH 0-
7 0 10D = -561lA 5.8 - -
-7
0-
"L"
*2
5 0
-9
100 = 0.2mA - - 0.4
output V
VOL 0-
voltage 7 0 100 = 0.3mA - - 0.4
-7
0 0 Vo: ORV output - 500 2000
5 Vo - Vi = 0.25V
0 -5 - 250 1000
RON Vi = VEE - (VOO - 0.25V) n
(Vi. V4) 0 0 Vo - V 4 = 0.25V - 350 1400
7
ON 0 -7 V4(VEE): MAX OV - 200 800
Resistance
0 0
VN =V2 or V3
- 800 3200
5
RON 0 -5 V = ORV output - 450 1800
n
(V2. V3) Vo - VN = 0.25V
0 0 - 550 2200
7 VN = VEE'" (VOO - 0.25V)
0 -7 - 350 1400

OFF Lead 5 0 -9 - - - 5
current IOFF IlA
7 0 -7 - - - 5
Power supply 5 0 -9 - - - 0.5
mA
current 100
7 0 -7 - - - 1.0
Input
capacitance CI - - 5 - pF

* 1 VIHl and VI Ll are input pins for 01 and OF. while VI H2 and VI L2 are input pins for CPo
*2 VOH and VOL are output pins for Do.

52
- - - - - - - - - - - -.....- DOT MATRIX LCD DRIVER MSM5238GS-

SWITCHING CHARACTERISTICS

VDD
Item Symbol Condition MIN TYP MAX Unit
(V)

5 - 400 - -
Maximum clock frequency t (cp) KHz
7 - 550 - -
5 - 400 - -
Clock pulse width tw (cp) ns
7 - 300 - -

5 - 100 - -
Data setup time (DATAIN ~CP) tsetup ns
7 - 50 - -
5 - 800 - -
Data hold time (DATAIN ~CP) thold ns
7 - 500 - -
tr (cp) 5 - - - 0.5
Clock pulse Rising/Falling time ms
tr (cp) 7 - - - 0.1

tf (cp)

CP 50% 50%
10%
tw (cp)

PIN DESCRIPTION VOO. Vss


VDO is a supply voltage pin. Usually it is used at
VDO = 3.0 -7 .OV VSS is a ground pin. (VSS = OV)
01
The data from LCD controller LSI is input to 32bit
0 1 - 0 32
shift register from DI. (Positive logic) Display data output pins which correspond to
This LSI is applicable up to 1/32 duty LCD panel each data bit in the latch. One of VI. V2. V3
because this LSI consists of 32-bit shift register. and V 4 is selected as a display driving voltage source
according to the combination of latched data level
CP and OF signal. Refer to the truth table and Time
Clock pulse input pin for 32bit shift register. The Chart. Output signal is a analog signal. 0 1 - 032
data is shifted to 32-bit level shifter at the falling are connected to the common side of the LCD panel.
edge of the clock pulse. A data set up time (tsetup)
and data hold time (thold) is required between Latched data OF Display data output level
01 and CP signal. (Refer to SWITCHING L V2
CHARACTERICS.I Schmit circuit is included in L
H V3
CP input circuit.
L V4
H
OF H VI
Alternate signal input pin for LCD driving waveform.

53
- DOT MATRIX LCD DRIVER MSM5238GS - . . . - - - - - - - - - - - - -

VOO = 5V
VOO

VI C
V2
C

MSM5238GS C VLCO

VSS VSS
Fig. 1

-7 - -9V -7 - -9V
1/32 duty C = 0.1 pF or less 1/32 duty C = 0.1 pF or less
1/7 bias R = 0.5 KQ-6 1/7 bias R = 0.5 kQ- 5kQ
VR = 5kQ-10kQ
*Ttie value of R should be decided according to the power consumption and LCO panel size.

V 1,V 2,V3,V4 00
Bias supply voltage pin to drive the LCO. Bias Shift register contents output pin. The data which
voltage divided by the registance is usually used was input from 01 is output from 00 with 32 bits'
as supply voltage source. delay. synchronized with the clock pulse. By
Fig. 1 shows the case when the bias voltage, which connecting 00 with next MSM5238GS's 01. this
determines the LCO driving voltage. is supplied LSI is applicable to the LCO. the duty of which
from the external source. is 1/64. Refer to the Fig. 2 below.

X32

> 64 x n

\
LCO panel

Frame
X32
I V
signal"'-- Ol
0 1 0 32
00 - 01
0 1 0 3200

,....-- OF MSM5238GS r--- OF MSM5238GS

Clock .... ~~CP VOOV I V 2 V 1 V 4 VSS


r~ CP VOOV: V 2 V3 V 4 VSS
.1
GNO
OF
1

+5V . .ry:J..A. .rrlYl~


A. .... .AAA .. A A. ...
T
L 9 - -11V

R R 5R R R VR
, ... ,
Fig.2
To SEGMENT Orivers

54
- - - - - - - - - - - -..... DOT MATRIX LCD DRIVER MSM5238GS.

TIME CHART
1/32 duty. 1/7 bias

01 ---Fl--------------- ~
(Frame signal) 32 : 1 ! 2 3 ----------- 32 1 2 3

CP
..JLJLJL..JL.JL-----------~
SR 0, ~------------~
a,
~__________ \1____
(InsIde the
circuIt)

a" SlL--_____________ SlL--_____


OF

VOO
Va

Vb --t--t---+---t--+-+--1r-- - - - - - -I-+---+---+--+-+-+-t-
0, -+-+--+--+-+-+--If-- - - - - - ---+--+--t--I--t-+--+--t-
Vc -+-+--+---+--+-+-t- - - - - - __I-t--+---+--+-+-+-t-
Vd _"--.......,....+-_-4..__1..---1.-""_ _ _ _ _ _ _"---'--.,....+-_-4..---I.---I.-""---l.....
Ve --_....1--"'------- - - - - - .---.......1---------
1 frame
VOD ------------,.......,------
Va - ......,..--.-..,..---+---'--r--r- - - - - - - -.....,..__ .........-__....--
....,.--,~-t--

Vb -+-+-+-+--+--+--1- - - - - - ---t--1-+--+---+---+--+-t-
0,
-+--+--+--+---+--t-I--- - - - - ----t-1-+--+---+---+--+-t-
Vc -+-+-+-I---+--t-I-- - - - - - --t--t-+-+---+---+-t--l-
Vd _ooI__-L-...............,..-+_--I_'__ - ---- -- - ...............---..........,...-t---.............--

Ve

VOO ---.--r-------- - - - - --- - -......,..-,--------


Va
Vb

0 . ,
Vc
Vd
Ve L L
VOO VOO

.-J R~
--
-01
V,
CP
OF
V, fo-
. Va
Vd VOO- l'7VLCO

--
~
0,
0,
CI)
t:)

~ 3R
R.
Vb
Vb VOO 2i7VLCD
Vc -VOO 517VLCO

I ~
CI)
Vc
Vd" VOO-6I7VLCO

I ::E R' Vc VOO VLCO

J.. 0 . , V.I ' - - >Vd VLCO LCD driving vclt.19"

:
V. ~ ~c-'"
~
VR

-5 --7V

55
DOT MATRIX LCD DRIVER MSM5238GS - .- - - -

LCD DRIVING WAVEFORM


1/32 duty, 1/7 bias

Common

Voo I 1 I 2 I 3 I 4 1------- I 32 I 1 I

th IVoo----r........-----
I I I I I

-
0, ~

~: o,~; --.--r--II,--t-'---r-I' ~II~II,


'II
II
! I : : T:
T
1---'---'----'-111
I I

~: ~" " ' d


~H H~

0, r: 11111I11 II III

VLCO _ _ _ __

Common 0, .- Segment 01 5!7VLCO II


[I 1
(Non-selected waveform) 117V

Va "VOO--l17VLCO
Vb" VOO- -2I7VLCO
1I7V~:~ I
J II II I

Vc" VOO -517VLCO
Vd ~ VOO-.6I7VLCO 517VLCO ~==================
VLCO _ _ _ __

56
-i
-<
~
n

r-
LCD panel 32 X 200
J
WU HHlIHtI ~IIII !ttl! iUti \ ~
~

" fHtFfITtfl r-

~ tHl nfH mit um C")



-i
r (5
r-----~I DI 0, - 0.12 2
MSM5238GS CP
~N'7 C")

ri DD
V, VSS V2
DF
V.l VEEIV4) r--
.-- CP MSM5839B
LOAD GS
0 40
D0 40
OC 20
DI21
DI,
CP
LOAD
0
'
MSM5839B
GS DI21
DI,
0,
::c
C")
c
=i
~
DF CK DF CK
VDDVSSV2V3VEEIV4) VDDVSSV 2 VJVEEIV~)
~~~Mf: D~~~ I

gE
) )'
CP OUT c
0
LOAD OUT -i
DF
s:
VDD
VSS
R
.(
\'

-i
> \\ ::c
R X
CONTROLLER
TIMING GEN
ROM IC.G.!
{ RAM 3R
~ \\ r-
C")
C
R ~ c
::c
R :>
<
m
~
::c
~ Brightness R = 0.5KD - 5KD
-') Adjustment
VR
VR=5KD-l0KD
s:
en
OV +5F -7 - -9V
~
U'1
N
W
00
G')
en
en
.....

~
OKI serniconauctor
MSM5839BGS
DOT MATRIX LCD 40 DOT SEGMENT DRIVER

GENERAL DESCRIPTION
The OKI MSM5839BGS is a dot matrix LC~'s segment driver LSI which is fabricated by low power CMOS metal
gate technology. This LSI consists of 40-bit shift register (two 20-bit shift registers), 40-bit latch (tVIO 20-bit latches),
40-bit level shifter and 40-bit 4-level driver.

It converts serial data, which is received from LCD controller LSI, to parallel data and outputs LCD driving waveform
to the LCD panel.

This LSI can drive a variety of LCD panel because the bias voltage, which determines the LCD driving voltage, can
be optionally supplied from the external source.

FEATURES
Supply voltage: 4.5 - 5.5V Bias voltage can be supplied externally
LCD driving voltage: 8 -18V 56 pin plastic flat package
Applicable LCD duty: 1/8 -1/128

PIN CONFIGURATION
(Top View)

NC
NC
NC
OF

LOAD

VDD

*This pin is internally connected with VOO, so it must not be connected to other signals. It is also prohibited to
use the 21 pin as a VOO independently. This pin may be used as a line reinforcing VOO.

58
- - - - - - - - - - - - . . - DOT MATRIX LCD DRIVER MSM5839BGS-

BLOCK DIAGRAM

-l I

40bit 4 Level Oriver VDDI


VEE( V 4 ) q--1r-~----------------~~~--------------~ t I

r-L----------'-_-'--------\VEE I
-- I

OF

LOAOD----t
~------~~------~

01,
CP

I I

L- ----o-u---- -.---
OO~I
---1

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Value Unit


Supply voltage (1) VOO Ta = 25C -0.3 -6 V

VOO - VEE*1 Ta = 25C 0-18 V


Supply voltage (2)
VOO - VEE:~ Ta = 25C 0-18 V
I nput voltage VI Ta = 25C -0.3 -VOO + 0.3 V
Storage temperature T stg - -55-+150 c

*1 : VOO > V2 > V3 > VEE


*2 : When a series resistance of more than 47n is connected as shown below.

MSM5839BGS
VOO-VEE 8+
-V
V

V EE _--~A"",-_

VSS RS~47n

59
DOT MATRIX LCD DRIVER MSM5839BGS - - - - - - - - - - - -

OPERATING RANGE

Item Symbol Condition Limit Unit


Supply voltage (1) VOO - 4.5"'5.5 V

VOO - VEE*l - 8'" 16 V


Supply voltage (2)
VOO - VEE:~ - 8"'18 V
Operating temperature Top - -20 "'+ 85 c

*1 : VOO > V 2 > V3 > VEE


*2 : When a series resistance of more than 4 7n is connected as shown below.

VOO

MSM5839BGS

VSS
V3

VEE I---'V'J'V----I
n -V
RS~47.l"
ti +V

D.C. CHARACTERISTICS
0
(Voo = 5V 10%, Ta = -20'" +85 C)

Item Symbol Condition MIN TYP MAX Unit


"H" input voltage VIH*l - 0. 8V OO - - V
"L" input voltage VIL*l - - - 0. 2V OO V
"H" input current IIH*l VIH = VOO - - 1 J.LA
"L" input current II L *1 VIL = OV - - -1 J1A
"H" output voltage VOH*2 10 = -O.4mA VOO - 0.4 - - V
"L" output voltage VOL*2 10 = O.4mA - - 0.4 V
VOO = VEE = 10V
ON registance RON*4
IVN - V O I=0.25V*3 -
3.5 7 kn
CP= OC
Power consunption IDO - - 100 J.LA
VOO - VEE = 18V No load

*1 : LOAO, CP, Oil, 0121, OF


*2 : 0020,0040
*3: VN = VOO "'VEE, V2 = ~ (VOO - VEE), V3 = ~(VOO - VEE)
*4 : Applicable to 0 1 '" 040

60
- - - - - - - - - - - - - - - DOT MATRIX LCD DRIVER MSM5839BGS-

SWITCHING CHARACTERISTICS

Item Symbol Condition MIN TYP MAX Unit


tpLH
"H", "L" propagation delay time - - - 250 ns
tpHL
Max. clock frequency fCp DUTY = 50% 3.3 - - MHz
Clock pulse width tW(CP) - 125 - - ns
LOAD pulse width tW(L) - 125 - - ns
Data setup time DI ~ CP tsetup - 50 - - ns
CP ~ lOAD time tCl - 250 - - ns
lOAD ~ CP time tlC - 0 - - ns
DATA hold time DI ~ CP thold - 50 - - ns
tr(CP)
CP Rising/Falling time
tf(CPI
- - - 50 ns

tr(ll
lOAD Rising/Falling time - - - 1 J.Is
tf(ll

CP

tsetup

O.BVDD
0.2VDD
D0
20
.D0
40
-----------------------+-----'

LOAD ___________________________0_.2_V_D_D-JL.~

61
DOT MATRIX LCD DRIVER MSM5839BGS - - - - - - - - - - - -

PIN DESCRIPTION

Oil VI (Vool. V2. V3. VEE (V41


The 1st - 20th data from the LCD controller LSI Bias supply voltage pin to drive the LCD. Bias
is input to shift register from Oil' (Positive logicl voltage divided by the resistance is usually used
as supply voltage source.

CP
Clock pulse input pin for the two 20-bit shift regis- LOAO
ter. The data is shifted to the two 20-bit latch at the The signal for latching the shift register contents
falling edge of the clock pulse. A data setup time is input from this pin.
(tsetupl and data hold time (tholdl are required When LOAD pin is set at "H", the shift register
each between 011. 0121 and CP. contents are transferred to 40-bit 4-level driver.
Schmit circuit is included in CP input circuit. When LOAD pin is set at "L", the last display
output data (0 1 - 0401, which was transferred
when LOAD pin was at "H", is held.
0020
The 20th bit of shift register contents is output
from 00 20 synchronized with the clock pulse. 0 1 -040
By connecting 0020 with 0121. two 20-bit shift Display data output pins which correspond to
registers are connected and becomes 40-bit shift each data bit in the latch.
register. One of VOO, V 2 , V3 or VEE is selected as a display
driving voltage source according to the combination
of latched data level and OF signal.
01 2 1
The 21st - 40th data from the LCD controller LSI These pins should be connected to the SEGMENT
is input to shift register from 0121' By connecting side of the LCD panel. Refer to the truth table
0020 with 0121. two 20-bit shift registers are below.
connected and becomes 40-bit shift register.

Latched data OF Display data output level


0040
The 40th bit of shift register contents is output H VEE (V 4 1
from 0040 synchronized with the clock pulse. H
L VOO
By connecting 0040 with next MSM5839BGS's
Oil, this LSI is applicable to a wide screen LCD. H V3
L
Refer to the sample application circuit. L V2

OF
Alternate signal input pin for LCD driving waveform.

VOO(V I I. VSS
Supply voltage pin. VOO should be 4.5 -5.5V.
VSS is a ground pin (VSS = OVI.

62
- - - - - - - - - - -___ DOT MATRIX LCD DRIVER MSM5839BGS-

TIME CHART
1/64 duty. 1/9 bias

1 - 6 4 + 1 + 2 .. -1-64-t-1 -+- 2.
LOAO
---1LJLJL JLJL1L
LATCH
DATA ~~
OF

LOAD
01,
OF CP
DOlO

LOAD --lL------ ~ 01" V,


0,

~---~
Vu:.O
01, v,
I ---

CP ~ ___ --1L.JtSU 04 (,

LATCHOArA ~ ~
Vss
1-64 + 1 -I- 2. I- 64-t- 1 + 2 . /-64+ 1 ~
LOAO
--1L.JLJL JLJL1L --1LJL..JL -9 -llV

LATCH
DATA ~ ~ ~
(O,'s lewl)
OF ~ ~ ~

VOO
I

T
Va
t
Vb

0,

Vc
Vd
Ve
I
I 1
Va VOO 1.9VLCO

Vb VOO -2/9VLCO

Vc VOO-719VLCO

Vd VOO- 8 19VLCO

"P. VOO-VLCO

63
E!
al
.j::o
__ -t
al
.j::o
-<
""C

C
0
~
Q. -
(") -t
-:'
~ r- ~
f\
~

-t
LCD Qio ""C
x64 ) on
""C JJ
64 x 120 dots r- X
" (")
r-
(")
0}-064 0080 -t C
r-- DI.
COM/SEG OF
CP f--
"0~o, ~rN02 ~rN03 0
2:
(")
C
JJ
<:m
~ LOAD MSM5260GS
VOO Vl VJ Vs VSS
,....---

r - - CP
01.
O. - 0 40

MSM5839B
00 40
00 10
---
-
01.
CP
O. - 0 40
MSM5839B
GS
00 4 I - 01.
00 10 -
O. - 0 40

!;P MSM5839B
0040
0010
JJ
(")
C
JJ
- LOAD
GS r- LOAD ..- LOAD
GS

FRP
'---
OF
Oil.
VOO V l VJ VEE VSS
0 OF
Oil.
VOO V l VJ VEE VSS
0 OFVOO V l VJ VEE
Oil.
VSS
-t ~
en
~
00. I
CJ1
CO

, I
I W
VOO
I
I
1 J.
J cg
OJ
VSS C')

CP R l
OV +5V
en

LIP R
FRM

5R.
~
LCD
R

Controller
R

~ Brightness
) adjustment

VEE
OKI semiconductor
MSM5259GS
DOT MATRIX LCD 40 DOT SEGMENT DRIVER

GENERAL DISCRIPTION
The OKI MSM5259GS is a dot matrix LCD's segment driver which is fabricated by low power CMOS metal gate
technology. This LSI consists of 40-bit shift register (two 20bit shift registers), 40bit latch and 40bit 4-level driver.

It converts serial data, which is received from LCD controller LSI, to parallel data and output LCD driving waveform
to LCD.

Expansion of display can be easily made according to the number and structure of characters. Its 40bit shift register
consists of two 20bit shift registers and this make it possible to allot bits efficiently according to the numbers of
characters.

The MSM5259GS can drive a variety of LCD panel because the bias voltage, which determines the LCD driving
voltage, can be optionally supplied from the external source.

FEATURES
Supply voltage: 3.5 "'6.0V Interface with MSM6222GS (LCD controller LSI
LCD driving voltage: 3.0'" 6.0V with 16bit common driver and 40-bit segment
Applicable LCD duty: 1/8'" 1/16 driver)
56 pin plastic flat package (bent lead)
Bias voltage can be supplied externally

PIN CONFIGULATION
(Top View)

0" NC

0'0
o NC

NC

0,. OF

0,. LOAD

O~II 011

{Vaal CP

0l' Vaa
0H Vss

02.\ \to:!
0,. v,

*21 pin is used as a VDD supporting pin, however, 21 pin alone cannot be used as VDD pin.

65
- DOT MATRIX LCD DRIVER MSM5259GS - - - - - - - - - - - - - - - -

BLOCK DIAGRAM

-~~~:
. I
40-blt 4-Level Driver I

OF ...,....--.... I
LOA
VSS

CP Register

I I

L -- - -----0-0------ _ ~

ABSOLUTE MAXIMUM RATINGS

Item Symbol Condition Limits Unit


Supply voltage (1) VOO -0.3 """+6.5 V
Supply voltage (2) VOO - VS*l Ta = 25C 0"""+6.5 V
Input voltage VI -0.3""" VOO + 0.3 V
Storage temperature T stg - -55"""+150 c

OPERATING RANGE

Item Symbol Condition Limits Unit


Supply voltage (1) VOO - 3.5 """6.0 V
Supply voltage (2) VOO-VS*l - 3.0 """6.0*2 V
Operating temperature Top - -20"""+85 c

*1. VOO > V 2 ;::: V3 > Vs ;::: VSS (Dynamic display)


VSS = V3 > V 2 = Vs = VSS (Static display)
*2. To decide the LCD driving voltage, change the value of V s. (Minimum OV)

66
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5259GS.

D.C. CHARACTERISTICS
(Voo = 5 10%, Ta = -20 _85C)

Item Symbol Condition MIN TYP MAX Unit


"H" input voltage VIH*1 - 0. 8V OO - - V
"L" input voltage VIL*l - - - 0. 2V OO V
"H" input current IIH* 1 VIH = VOO - - 1 J.l.A
"L" input current IlL * 1 VIL = OV - - -1 J.l.A
"H" output voltage VOH*2 10 = -40J.l.A 4.2 - - V
"L" output voltage VOL*2 10 = O.4mA - - 0.4 V

ON resistance RON*3
VOO-Vs =5V
I VN - Vo I = 0.25V*4 - - 5 kn.
Current consumption 100 CP = ~C, No load - - 0.5 mA

*1. Applicable to OF, LOAD, 011 and 01 21 terminals.


*2. Applicable to 00 2 0 and 0040 terminals.
*3. Applicable to 0 1 - 040 terminals.
2 1
*4. VN = VOO -Vs, V 2 = "3(VOO - V s ), V3 = :r(VOO - V s )

67
DOT MATRIX LCD DRIVER MSM5259GS. - - - - - - - - - - - - -

SWITCHING CHARACTERISTICS
0
(VDD = 5 10%, Ta = -20 _+85 C, CL = 15pF)

Item Symbol Condition MIN TYP MAX Unit

tpLH
"H", "L" propagation delay time
tpHL
- - - 250 ns

Max. clock frequency fCp Duty = 50% 3.3 - - MHz


Clock pulse width tW(CP) - 125 - - ns
Load pulse width tW(L) - 125 - - ns
Data set-up time, 01 -+ CP tsetup - 50 - - ns
CP -+ LOAD time tCL - 250 - - ns
LOAD -+ CP time tLC - 0 - - ns
Data hold time 01 -+ CP thold - 50 - - ns

tr(CP)
Clock pulse Rising/Falling time
tf(CP)
- - - 50 ns

tr(L)
Load pulse Rising/Falling time - - - 1 J1s
tf(L)

tf(CP)

CP

0111

LOAD 0.2VDD

68
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5259GS.

PIN DESCRIPTION

01 1,01 21 LOAD
The date (1 st - 20th bit) from the LCD controller The signal for latching the shift register contents
LSI is input to 20-bit shift register from 011' The is input from this pin.
data (21st - 40th bit) is input to another 20-bit When LOAD pin is set at "H" level, the shift register
shift register from 01 21 , contents are transferred to the 40-bit 4-level driver.
(Positive logic) When LOAD pin is set at "L" level, the last display
output data (0 1 - 0 40 ), wh ich was transferred
CP when LOAD pin was at "H" level, is held.
Clock pulse input pin for the two 20-bit sh ift register.
The data is shifted to 40-bit latch at the falling VOO, VSS
edge of the clock pulse. A data set up time (tsetup) Supply voltage pins. VDO should be 3.0 -6.0V.
and data hold time (thold) are required between VSS is a ground pin (VSS = OV)
a Dl1 signal and a clock pulse.
Clock pulse rising time (t r ) and clock pulse falling VOD, V2, V3, Vs
time (tf) should be maximum 50ns respectively. Bias supply voltage pins to drive the LCD. Bias
voltage divided by the register is usually used as
0020 supply voltage source.
20th bit of the shift register contents is output from Refer to the application circuit.
0020' The data which was input from 011 is output
from this pin with 20 bits' delay, synchronized 0 1 -040
with the clock pulse. By connecting 00 20 to 0121, Display data output pin which corresponds to each
two 20-bit shift registers can be used as a 40-bit data bit in the latch_
shift register. One of VDD, V2, V3 and Vs is selected asa display
driving voltage source according to the combination
0040 of latched data level and OF signal.
40th bit of the shift register contents is output from (Refer to the truth table below)
0040' The data which was input from 01 21 is out-
put from this pin with 20 bits' delay, synchronized Latched data OF Display data output level
with the clock pulse. By connecting 0040 to the
next MSM5259GS's Oil, this LSI is applicable to "H" H Vs
a wide screen LCD. (Selected) L VDD
Refer to the application circuit.
"L" H V3
(Non-selected) L V2
OF
Alternate signal input pin for LCD driving.
Truth Table

69
DOT MATRIX LCD DRIVER MSM5259GS . - - - - - - - - - - - - -

TIME CHART
1/5 bias, 1/16 duty

Frame
signal
--......Jr:--l----_____ -- - - ~
I

LOAD
+16+ 1 +- 2+ 3~ T2+3 + -------- +16+ 1

~-------~
11 LATCH
DATA
=~----------==
~rL _______ JLIl..JL.SL.Jl.
OF
: I
--- ................
- ......
I ---
I ......................

OF
--; .....
1 _ _ _ _ _ _- ___
-- - -------..~1...._ _ _ __
LOAD --1l __ ___ nL...-_ _
01

CP

LATCH
=-----=
JULJLJl..JL ____ J1..JL..JL..flJ
_______ ___
~'-- -~== X\.... _ _ __
.....J

DATA

LOAD JLJLJLJLJL_________ JLJL.-1LJLJL


LATCH
....Jr---t
H L r---1
l.....b...-' L L _______ .......Jr---1
H L::--..::.. L . -H- - -H- ,L.
H L....':.-J
DATA

OF

VOO

1
Va ~

VOO -'5 VLCD


2
Vb ~

VOO -'5 VLCD


3
Vc ~
VOO -'5 VLCD
4
Vd = VOO -'5 VLCD

Ve - VOO-VLCO

VLCO = LCD driving voltage

Vss

70
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER . MSM5259GS.

LCD DRIVING WAVEFORM


1/5 bias, 1/16 duty

Common ~ VOO 1 +....:.--2_+_3_+~4_+_-_-_-_-_-~~_16....;+,.....1.....+~-1


---,.'1:---.-

t-l\, ~~ \II IIII I II : II [ t


,--1..r---.---.---------3
-ffi-e-ffl-ffic-ffi- Vel I
~~~~ I I

--~. ..--.
OO

~ : ~= ~~:=;=
~- -r- : J= :- +L=~-4-+1 ===-= - :t :l ~=~'~,
o. V --L-----.--

=-i:tJ-ffH+ 0, -=:===-: =:::::!1----41 I ===t=J----l--


0, .l -{tJ-ft}-tIl-Hl-+9- I 1

Il
0,. -ffi-e-{f}-ffi-ffi- VOO -,-1--.-_ _ _ _ _ _ _ _ _----;'_ _- -

~:: O,~
t
OJ' ~~ ~~~---------3~~---
JII IE Ve
DOL

:
Segmcnt-. : :

~: ~:H~~:: O'v~~ ==:::~1


~ [~=I
~ p==========]J~~!--,
-+i~~~~~--------~~.~~~
UJ Ve
Voo -~ VLCD
1
I I
I I

,,
1
~VLCD I I r I I 1 I r1
Common at-Segment 0 1 a
1 ~ I I tJ L I I I I
(Select waveform) -"5 VLCD

VLeD

VLCD

3 0 I
"5 VLCD

l~
I

~VLCD
Common 02-Segment 0 1 I 13 1 R I
(Non-select waveform) -~ VLCD
-~ VLCD
! !
1
I
II
I
-VLCD
1 frame ,I

71
l!
'-I
N - -I
b> ~ c
5""D a
n
:ll
[
-I
s:
~
LCO or
s:
en""D
-I
JJ
S:""D _
~ ~ ~~ ~ N
0) r_ X
N n r
~ n
ren -I
_ C
n a c
SEG1-40 0 1 - 0 40 0 1 - 0 40 0 1 - 0 40 0:2
n JJ
_
COM1-16
00 011 MSM 0040 011 MSM 0040 011 MSM 00 40
g n <
.., JJ m
.--- CP
5259GS
0020 . . - - - CP 5259GS 00
20 .--- CP 5259GS 00 20 g, n JJ
- LOAO 01 21 tJ r--- LOAO 01 21 ] .--- LOAO 00 21 ] ! c
s:
MSM6222GS
.-- OF
VOOVSSV2 V3 Vs
- OF
VOOVSSV2 V3 Vs
- OF
VOO VSS V 2 V3 Vs
-I
en
s:
U1
CP N
U1
L (g
G)
OF en
VOO
GNO

VI
V2
V3
V4
'Is \

R R R R R
...... ...
..yyy .,1
TV"
=rc =r ;:c T
AlA AA A AA
YV' YY. VYT V T
c
C;:i OV
-i
The MSM5259GS is applicable to a static LCD by setting V 2 and Vs at ground level, connecting V3 to VOO and' -<
"'C
inputting COMMON SIGNAL to OF pin. n

This sample application circuit below is the case when the MSM5259GS is applied to a SObit LCD panel by connect r
ing two MSM5259GS in series.
"'C
"'C
r
n

-i
0
2
n
:JJ
80 Dot LCD PANEL n
__________________ Seg Seg. , SP.<J80 c
COM Seg, ----------------- =i
:OM
J----------------- ---f f---------------------4 "TI
0
:JJ
M

32 -1
:69f ;.
'tr r--
0, - - - - - - - - - - - - - - - - - - - - - 0 4
VDD
v,
[:
0,
VDD
V,
- - - - - - - - - - - - - - - - - - - 0
en
-i

C
0
-i
Duty l% I-- V 1 V1 -i s:
n
~
C ION
JAL
t 0.---- V,
OF
MSM5259GS
~ V,

OF
MSM5259GS
C
en
-i
:JJ
.---- J.- LOAD LOAD "'C
r
X
o

I

IN 01, DO 01, r
S
K CP ,-- '-- CP -< n
C
c
J1.... ~ VSS(GND) 00,0 01" ..- VSSIGND) 00'0 01" C
~ -..:-
- :JJ
L-...J L-J <:m
LOA ~

---JL
:c
s:en
S
C1I
N
C1I
(C
G)
..... en
Col

~
OKI semiconductor
MSM5260GS
DOT MATRIX LCD 80 DOT COMMON/SEGMENT DRIVER

GENERAL DESCRIPTION

11
The OKI MSM5260 is a dot matrix common/segment LCD driver LSI which is fabricated by low power CMOS. metal
gate technology. This LSI consists of 80bit shift register, 80-bit data latch, 80-bit level shifter and 80-bit 4-level
driver.

It converts serial data, which is received from LCD controller LSI, to parallel data and outputs LCD driving waveform
to LCD.

This LSI can drive a variety of LCD pannel because the bias voltage can be optionally provided from the external
source.

FEATURES
Supply voltage: 4.5 ....... 5.5V Can be used either as common driver or segment
LCD driving voltage: 8 ....... 18V driver
Duty 1/1 ....... 1/128 Interface with MSM6240GS LCD controller LSI
Bias voltage can be supplied externally 100 pin plastic flat package

PIN CONFIGURATION
(Top View)

999999999999PPPPPP22PP292?9PB9
- = .c. =-
:t -c
..J 'J' .. '_ 1.,1 - ::: '7 _l ':' 'J, .. W tJ - :::

0 1
NC
V.I
VDD"
ep
NC
011

NC
NC

NC
OOKO
NC
LOAD

OF

NC
COM/SEG
Vs

~~~~~illillW~~
2
V

*VDD must be supplied to both 40 pin and 97 pin.

74
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.

BLOCK DIAGRAM

O2 019 0 80

--O-O--VD~l
- - - - - - - - - - - - - - - - - - -

4 Level Oriver x 80 t I
Vs

Voo I

COM/SEG
LOAO 80 Bit Latches V!S I
~ VSS

01, ~------------~--~-------------~------<)OORO
I
CP .80 Bit Shift Register I I
I
L- ____ ---~

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Limit. Unit


Supply Voltage (1) VOO Ta = 25C -0.3 -6 V
VOO - VS*l Ta = 25C 0-18 V
Supply Voltage (2)
VOO - Vs:~ Ta = 25C 0-20 V
Input Voltage VI Ta = 25C -0.3 - VOO + 0.3 V
Storage Temperature V stg - -55 -+150 c

*1 : VOO > V 2 > V3 > Vs


*2 : When a series resistance of more than 47n is connected as shown below:

Voo
I 1
V2 r- Voo-Vs

~AA I ~t-I
MSM5260GS v 3 !-

Vs ~ v >V
Vss
RS;;>47rl

.J,.

75
DOT MATRIX LCD DRIVER MSM5260GS. - - - - - - - - - - - - -

OPERATING RANGE

Parameter Symbol Condition Limit Unit


Supply Voltage (1 )*1 VOO - 4.5'" 5.5 V

Supply Voltage (2):~


VOO - VS*1 - 8"'16 V
VOO - Vs:~ - 8"'18 V
Operating Temperature Top - -20 "'+85 c

*1 :VOO>V2>V3>VS
*2: When a series resistance of more than 47nis connected as shown below:

I r
VOO
V1r-

MSM5260GS V]f- VT~J+V


Vs 11
yyv
I.,.. --'I
VSS
RS>47n

rh-

D.C. CHARACTER ISTICS


0
(VOO = 5V 10% Ta = -20 "'+85 C)

Value Unit
Parameter Symbol Condition
MIN TYP MAX
"H" Input Voltage VIH*l 0. 8V OO - - V
"L" Input Voltage VIL*l - - 0. 2V OO V
"H" Input Current IIH*l VIH = VOO - - 1 JiA
"L" I nput Current II L * 1 VIL = OV - - -1 JiA
"H" Output Voltage VOH*2 10 = -0.4 rnA VOO - 0.4 - - V
"L" Output Voltage VOL*2 10 = 0.4 mA - - 0.4 V

'(DO - Vs = 10V
ON Resistance RON*4
IVN -VOI=0.25*3
- - 2 kn

CP = DC
Power Consumption 100
VOO - Vs = 18V No load - - 100 JiA

*1 Applicable to LOAD, CP, OTl, OF and COM/SEG pins.


*2 00 8 0
*3 VN = VOO "'Vs V 2 = 8/9 (VOO - V s ) V3 = 1/9 (VOO - Vs)
*4 Applicable to 0 1 '" 0 80' display data output pin.

76
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.

SWITCHING CHARACTERISTICS
(VOO = 5V 10%, Ta = 20"" 85C. CL = 15 p F)

Value
Parameter Symbol Condition Unit
MIN TYP MAX
tpLH
"H", "L" Propagation Delay Time - - - 250 ns
tpHL
Max. Clock Frequency fCp Duty = 50% 3.3 - - MHz
Clock Pulse Width tW(CP) - 125 - - ns
LOAD Pulse Width tWILl - 125 - - ns
Data Set-up Time 01 ~CP tsetup - 50 - - ns
CP ~ lOAD Time tCl - 250 - - ns
LOAD ~ CP Time tlC - a - - ns
Data Hold Time 01 ~ CP thold - 50 - - ns

tr(CP)
CP Rising/Falling Time - - - 50 ns
tf(CP)
trll) - -
lOAD Rising/Falling Time - 1 J,ls
tf(l)

CP

00 80

lOAD

PIN DESCRIPTION

011 0080
The date from the lCO controller lSI is input to 80th bit of the shift register contents is output
80-bit shift register from 011' (Positive logic) from 00 80 , The data which was input from 011
is output from this pin with 80 bits' delay,
CP synchronized with the clock pulse. By connecting
Clock pulse input pin for 80-bit shift register. The 00 80 with next MSM5260GS's Oil, this lSI is
data is shifted to 80-bit latch at the falling edge of applicable to a wide screen LCD. Refer to the
the clock pulse. A data set up time (tsetup) and a application circuit.
data hold time (thold) are required between a 011
signal and a clock pulse.
Clock pulse rising time (t r ) and clock pulse falling
time (tf) should be maximum 50 ns respectively.

77
DOT MATRIX LCD DRIVER MSM5260GS. - - - - - - - - - - - - -

LOAD COM/SEG
The signal for latching the shift register contents Selection signal input pin. MSM5260GS is used
is input from this pin. either as common driver or segment driver according
When LOAD pin is set at "H" level, the shift register to input signal level at COM/SEG pin.
contents are transferred to 80-bit 4-level driver When this pin is set at high level, MSM5260 is used
through 80-bit level shifter. as a common driver, while it is used as a row driver
When LOAD pin is set at low level, the last display at low level.
output data (0 1 - 0 8 0), which was transferred
when LOAD pin was at high level, is held. The display driving data 01 - 080, which are
determined according to the combination of latched
data and OF signal, are shown in the Table 1 below.
OF
Alternate signal input pin for LCD driving.

Latched Display data output level


COM/SEG OF Note
data level (0 1 -0 80 )

High H VDD Common driver


(Selected) L Vs
H
Low H V3
(Non-selected) L V2
High H Vs Segment driver
(Selected) L VDD
L
Low H V3
(Non-selected) L V2

Table 1

When MSM5260GS is used as common driver, both side's non-selected level is to be supplied to V 2
LOAD pin and COM/SEG pin are to be connected and V3 pins.
to VDD. In this case, a bias voltage of common

VDD

(Common driver) (Segment driver)

VDD, Vss
Supply voltage pins. VDD should be 4.5 - 5.5V:
VDD t-----....--------tVDD
VSS is a ground pin (VSS = OV)
MSM
5260GS
VDD, V2, V3. Vs
Bias 'supply voltage pin to drive the LCD. Bias MSM
voltage divided .by the register is usually used as 5260GS
supply voltage source.
Figure 1 shows the case when bias voltage, which
is used to drive the LCD, is obtained by the
t - - - - - - - " - i V3
voltage disivion by external registers.

0 1 -080
Display data output pins which correspond to the
80bit latch contents.
One of VDD, V 2 , V3 and Vs is selected as a display VSS
VSS
driving voltage source according to the combination
of latched data level and OF signal. (Refer to the
time chart and Table 1.)
Contrast adjustment
1/64 duty 1/9 bias

Figure 1

78
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.

TIME CHART (COMMON DRIVER)


1/64 duty. 1/9 bias

0, ~ __ ---1L-__ ~
InSide 0, ~ __ ----.JL_~_~
the IC
__ ~ ___ ..IlL-_ _
~
l COJSEG
LOADVDCf--
VOO

.... 01

"1
..... CP
V, I-- Va
a,
iI
VOO ~)

1-
I
Va I 5R
I
Vb >\l c
1
I VLCO
v.
~a
0,. f--
a,
VLCO
0 8
V. f - - Vr

1
Vss ~
Ve /' VR
Vd
Ve 9--11V
~1lrame --I
VOO
Va
Vb

0,

Vc
Vd
Ve

VOO
Va
I
Vb
Va~ VOO-1/9VLCO
0 Vb ~ VOO--2/9VLCO
Ve - VOO-7,'9VLCO
Vd 0 VOO-S/9VLCO
Ve Vc "VOO-VLCO
Vd
Ve VLCO LCD drivong voltage

79
DOT MATRIX LCD DRIVER MSM5260GS. - - - - - - - - - - - - -

TIME CHART (SEGMENT DRIVER)


1/64 duty. 1/9 bias

.....
I
I
..... .......
I .....
.....
t
DF - -__. ._. . . . 1
.
LOAD
-.-ll ~
~---~
___ ----"------A--

CP ~ ___ JU1JLJ
LATCH DATA
~ ~
LOAD
r + +
64 1 2 - - + + +
64 1 2 -- - +- + -+- 64 1 2

~ JLJLJL -1LJLJL -9 - -llV

1
I
I

I
I 1
Va = VDD - 1/9VLCD
Vb = VDD -- 2/9VLCD
Vc = VDD - 7/9VLCD
Vd=VDD - 8/9VLCD
Ve =VDD - VLCD

80
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.

APPLICATION CIRCUIT
STATIC display

Level Shifter

30 - l20Hl slgllal

.f1...I1.' 5V
o.---<I_--.
OV
D~~A .fUL
CLOCK Jl..IUUL

The MSM5260GS can make a static drive of a LCD by controlling the supply voltage. So it can be used to drive a
color LCD which requires high driving voltage. The value VDD - V S must be l8V > VD D - V s i:; 5V.

1/64 duty. 1/9 bias

OV +5V
LIP
R
FRM
5R
MSM6240GS
R

LCD Controller Contrast adjustment

VEE

81
OKI semiconductor
MSM5278 GS
DOT MATRIX LCD 64 DOT COMMON DRIVER

GENERAL
The OKI MSM5278GS is a dot matrix LCD's common driver LSI which is fabricated by low power CMOS metal gate
technology. This LSI consists of 64-bit bidirectional shift register, 64-bit level shifter and 64-bit 4-level driver.

This LSI has 64 output pins to be connectec1 to the LCD. By connecting more than two MSM5278GSs in series, this
LSI is applicable to a wide LCD panel.

This LSI can drive a variety of LCD because the bias voltage, which determines the LCD driving voltage, can be
optionally supplied from the external source.

FEATURES

- Supply voltage: 4.5 - 5.5V - Bias voltage can be supplied externally


- LCD driving voltage: 8""" 20V - 80 pin plastic flat package
-Applicable LCD duty: 1/64 -1/128
Two chips of the MSM5278GS are required to drive
1/128 duty LCD.

PIN CONFIGURATION
(Top View) 80 Lead Plastic Flat Package

p p
f' p
? ? ? ~ ? .? ? 9 ? 9 ? ? P p
? p
? ? .~ P

0 411
10'4

NC 0

vEE 0"
v, 0,

v, 0"
v, D.n

NC D.,.

VOO 0"
SHL 0-'2

VSS 0"

NC 0.,,,

OF

NC 0,.
CP 0"
NC 0"

10, 0,.

s:- .'? '? P fl P '? 9 P 5' 5' 5' 5' 5' 5' 5' 5' 5' 5' .'?
f :? 9 f?

82
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5278GS.

BLOCK DIAGRAM

v.
--l
0 63 0 64

64-bit 4-Level Driver V.

t
VEE VEE
I

DF 64-bit Level Shifter ~~;;j


t
SHL
64-bit Bidirectional Shift
10. 1064
Register
CP

~~:h
ABSOLUTE IVIAXIMUM RATINGS

Parameter Symbol Condition Value Unit


Supply voltage (1) VDD Ta = 25C -0_3 -6 V
Supply voltage (2) VDD - VEE*l Ta = 25C 0-22 V
I nput voltage VI Ta = 25C -0.3 - VDD + 0.3 V
Storage temperature T stg - -55-+ 150 c

OPERATING RANGE

Parameter Symbol Condition Limits Unit


Supply voltage (1) VDD - 4.5 -5.5 V
Supply voltage (2) VDD - VEE*l - 8-20 V
Operating temperature - -20-+ 85 Vc
Top

83
DOT MATRIX LCD DRIVER MSM5278GS. - - - - - - - - - - - - -

D.C. CHARACTERISTICS
(Voo = 5V 10%. Ta = -20 _+85C)

Parameter Symbol Condition MIN TYP MAX Unit


"H" I nput voltage V,H*1 - 0. 8V OO - - V
"L" I nput voltage V,L *1 - - - 0. 2V OO V
"H" Input current "H *1 V,H = VOO - - 1 J1A
"L" Input current ',L *1 V,L = OV - - -1 J.1A
"H" Output voltage VOH*2 10 = -O.4mA VOO-0.4 - - V
"L" Output voltage VOL*2 10 = OknA - - 0.4 V

VOO - VEE = 1.8V *3


ON Resistance RON*4 - 1 2 kr2
IVN - vol= 0.25V
CP = OC
Power consumption 100
VOO-VEE = 18V No load
- - 100 J.1A

I nput capacitance C, f = 1MHz - 5 - PF

*1 Application to CPo 10,. 1064 SHL and OF terminals.


*2 Applicable to 10,. and 106 4 terminals.
. 10 1
*3 VN = VOO -VEE. V 2 = TI (VOO - VEE). Vs = '1'1 (VOO - VEE), VOO = VI
*4 Applicable to 01 - 064 terminals.

SWITCHING CHARACTERISTICS
(VOO = 5V 10%. Ta = -20-+85C CL = 15pF)

Parameter Symbol Condition MIN TYP MAX Unit

tpLH
"H" "L" propagation delay time - - - 250 ns
tpHL
Max. clock frequency fCp - 1 - - MHz
Clock pulse width tW(CP) - 125 - - ns
Oata set-up time 10 1 (l064)~CP tsetup - 100 - - ns
Oata hold time la, (1064)~CP thold - 100 - - ns

tr(CP)
Clock pulse Rising/Falling time - - - 50 ns
tf(CP)

CP

tsetup

0. 8V OO
0. 2V OO

84
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5278GS.

PIN DESCRIPTION

101,1064, SHL
10 I and 10 6 4 are 64-bit bidirectional shift register by the H/L condition of SHL pin. Refer to the table
input/output pins. The shifting direction is selected below.

Shifting
SEL 10 1/ 10 64 Input/output Pin description
direction
The scanning data from the LCD controller LSI
10 1 Input is input from 10 1 synchronized with the clock
pulse. * 1
L 0 1 -+064
Shift register c'ontents output pin. The data
which was input from 10lis output from 1064
10 64 Output
with 64 bits' delay. synchronized with the
clock pulse. Refer to the application circuit.
The scanning data from the LCD controller LSI
1064 Input is input from 1064synchronized with the clock
pulse. * 1
H 064 -+0 1
Shift register contents output pin. The data
which was input from 1064is output from 101
10 1 Output
with 64 bits' delay. synchronized with the
clock pulse. Refer to the application circuit.

*1 The combination of the scanning data.IO I or 1064.and theLCD driving output. 0 1 ....... 0 64. is shown in the table
below.

10 1,106 4 LCD driving output


H Selected level (VI. VEE)
L Non-selected level (V2. V s )

CP
Clock pulse input pin for 64-bit bidirectional shift
register. The data is shifted to 64-bit level shifter at
the falling edge of the clock pulse. VDD
VDD

...-.....- - - - - - -.....--1V\
OF
Alternate signal input pin for LCD driving. R
Normal frame inversion signal is input.
1-~_----------1V2

VOO, VSS
R
Supply voltage pins. VDD should be 4.5 ....... 5.5V.
VSS is a ground pin. (VSS = OV) MSM
7R 5278GS
VI, V2, Vs, VEE
Bias supply voltage pins to drive the LCD. Bias R
voltage divided by the resistance is usually used r-~~-------~Vs

as supply voltage source.


The below figure shows the case when bias voltage R
is divided by the resistance. V I is not necessarily J--+--------/ VEE
connected to VDD. VSS

11 - -13V VI. VEE ..... Selected level


V 2, V 5 Non-selected level
1/11 Bias. 1/100 Duty

85
DOT MATRIX LCD bRIVER . MSM5278GS. - - - - - - - - - - - - -

The figure below shows the case when bias voltage


is supplied by the Op-Amps. By using Op-Amps.
the bias voltage becomes low impedance and the
power consumption of MSM5278 becomes low.

VDD

VDD
VI

J R
R

7R
MSM5278GS
Op-Amp voltage follower

R
1/11 Bias. 1/100 duty

VR

-11 - -13V VSS

01 - 0 6 4
Display data output pins which correspond to source according to the combination of the latched
64-bit shift register contents. One of V 1. V 2. V 5 data level and OF signal. (Refer to the truth table
and VEE is selected as a display driving voltage below'!

OF Latched data level Display data output level (0 1 -064)


L L V2
L H VEE
H L Vs
H H V1

Truth table

86
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5278GS.

TIMING CHART
1/100 duty,l111 bias

VOO
I
~--~-~
100 I' 2 3 100 1 2 3 100 1 2 3 4
CP -A.JU1.JL ____ ---1lJ1Jl.JL ____ ~
. ,
o, (O~--~---~ 0,
I , 0,
O,(O,~ __ ~ __ ~
Inside
, I
the
I.C. t
a"
~
(0,001 1 I
__ ---IL--___ Sl 0

OF ---1 I __ ~-- - 1 ...._ _


I
VOO (V, I_I_ __

1
Va --~r--
I Voo
Vb ---+--- v,

0,
VLCD
v, R
R
v~
Vb

}
0"
VLCD

Vc
Vd
---+--_.-
- - _ _-L._ _
..
7R

R
V1
Vd

Ve
Ve _ _ _ L - - - -- 1
I 1 frame -11 .~ -13V
VOl) (V, 1, _ _ _ __

Va
Vb

0,

Vc
Vd
Ve

VJ!0(V, I -.-.."r-----
I
Vb

0 100
Va ~ VOO--l/11 VLCO
Vb = VOO- 2/11 V LCD
Vc = VOO-- 9/11 VLCD
Vd = V0010/ll VLCO
Vc Ve = VOO-,VLCO,
Vd
Ve
, -
VLCO: LCD driving voltage

87
r!
co
co l>
." 0

."
r- 0
-i
n
l> ~
-i l>
-i
VDD+5V -
-- 0 :0
--
---
II Z
C')
X
r-
-~
:0 C')
- C') 0
Controlier C
}44 4 }4 4
0
14 -i :0
8
FRAME
MSM5278
LOA
ECLK
P D.-D, ,,-VEE
VSS i -
SHL >-- -
LOAtf Do-D, V,-VEE

ECLK
VSS I-
SHL r- -
CP Do-D, V, -VEE
LOAD
ECLK
VSS
SHL
-
-
<:m
LOAD CP 10.. MSM5279 VODr-- >-- VDD _ :0
~~~ ~ f ~D
DF
~
'-i~;c
4 ____
00'0 - 0 ' 0,
EL Shifting ER
~,~~,,"--
I----------i
0 .. E
nable
direction
EL MSM5279
~ 0' 0,_- ____ 0..
-----------1
-

x
---
8 -
- EL MSM5279
'0,_ - - - --D..
\--------i
ER

~
CJ)

ECLK
re~o'O.. SEGI SEGSO SEGSI SEGl60 SEG561 SEG640 ~
~r-- ~vss 36 ....., 01
~~ 640xlOO 1/100 Duty N
4 v, '-VE' 100 -...J
CP LCD PANEL (640 x 200) 00
CP 10,4 64 100 C)
Voo CJ)
f - - ~vss .10 1
SHL r'
D,,-D,(UP) ............ OF -,
SEG641 SEG720 SEG721 SEGSOO SEGI201 SEGl2S0
--
VI -VEE
4
4
D. -D3(DOWN) CP
6
t---------- t Ellable
direction 1--------4 xS
--- ------1
4
'--- ~;DO
Vss ... '0, DFu"o ... --:---- 0, 0. 0 0,
-
pFo,o _____ 0,
SHLL
OF
r-- :'hift,ng EL f r-- DF MsM5279 - EL ER MSM5279 EL
4 VI -VEE
r-- ER direction VDD ER VDD 1------ - VDC
-
~
-=- -
1- ECLK MSM5279 SHL r-- ECLK SHL ECLK SHL
SS
MSM527S
1- LOAPo
_C
VSS
-D j V, -VEE
r- r-
LOAD VSS
r.F Do -D, V, -VEE r-- L0t'pttJo-D, V,_VEVE
VDD 0
V,
4 }4 4 14 4 J4

!~
V,
~
---
---
I~
V,
~

::=--
I~ ~ -
I~ :---"
V,
----
I~ ~
V
OKI semiconductor
MSM5279GS
DOT MATRIX LCD 80 DOT SEGMENT DRIVER

GENERAL
The OKI MSM5279GS is a dot matrix LC~'s segment driver LSI which is fabricated by CMOS low power metal gate
technology. This LSI consists of SO-bit bidirectional shift register, S(}'bit latch, S(}'bit level shifter and S().bit 4-level
driver.

It receives the display driving data, which consists of 4-bit parallel, from the LCD controller LSI, then output the
LCD driving waveform to the LC~'.

The MSM5279GS has the power down function which enables the MSM5279GS's power consumption low.

The MSM5279GS can drive a variety of LCD panel because the bias voltage, which determines the LCD driving
voltage, can be optionally supplied from the external source.

FEATURES
Supply voltage: 4.5 - 5.5V 4-bit parallel data processing
LCD driving voltage: S - 20V Can be interfaced with the MSM6255GS,
Applicable LCD duty: l/S -1/12S MSM6265GS, LCD controller LSI
Bias voltage can be supplied externally 100 pin plastic flat package
Power down function

PIN CONFIGURATION
(Top View)

ER
NC
VEE
v.
V.
V,
NC
OF
NC
VDD
SHL
VSS
D .
0,
0,
DC)
CP
ECLK
LOAD
EL

89
DOT MATRIX LCD DRIVER MSM5279GS. - - - - - - - - - - - - -

BLOCK DIAGRAM

Ic--"--'-------
----- ----- - -'- - '- --l
-,
11 SObit 4-Level Driver

VEE
VEE
t

OF
SObit Level Shifter
VDD

LOAD VSS
t
SO bit Latch (Edge trigger by DF/F)

SHL
4-bit x 20 Bidirectional Shift Register
I
......0 VDD

SHIFT CP
I
.Jl.J1.... CP r,VSS

EL
I
ER
ECLK

--~
JL!
I
*P.D; Power Down

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Limits Unit


Supply voltage (1) VDD Ta = 25C -0.3 -6 V
v
Supply voltage (2) VDD - VEE*1 Ta = 25 C 0-22 V
v
Input voltage VI Ta = 25 C -0.3 -VDD + 0.3 V
Storage temperature T stg - -55-+ 150 Vc

90
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5279GS.

OPERATING RANGE

Parameter Symbol Condition Limits Unit


Supply voltage (1) VDD - 4.5 -5.5 V
Supply voltage (2) VDD - VEE*I - 8-20 V
Operating temperature Top - -20 -+ 85 Vc

DC CHARACTERISTICS
0
(VDD = 5V 10%, Ta = -20 _+85 C)

Parameter Symbol Condition MIN TYP MAX Unit

"H" Input voltage VIH*I - 0.8VDD - - V

"L" Input voltage VIL*I - - -- 0. 2V OD V

"H" Input current IIH* I VIH = VDD - - 1 J.LA


"L" Input current IlL * I VIL = OV - - -1 J.LA
VDD-
"H" Output voltage VOH*2 10 = -0.2mA - - V
0.4
"L" Output voltage VOL*2 10 = 0.2mA - - 0.4 V

VDD - VEE = 18V


ON resistance RON*4 IVN - Vo 1= 0.25V
;
- 2 4 kn.
CP = 1 MHz
Standby current consumption IDDSBY
VDD - VEE = 18V, No lo~d*5
- - 200 J.LA

CP = 1 MHz
Current consumption (1) IDDI - - 4 rnA
VDD - VEE = 18V, No load*6
CP = 1 MHz
Current consumption (2) IV
VDD - VEE = 18V, No load*7 - - 100 J.LA
Input capacitance CI f = 1 MHz - 5 - PF

*1 Applicable to LOAD, CP, Do -D3, ECLK, EL, ER, SHL, DF terminals.


*2 Applicable to EL, ER terminals.

*3 VN = VDD - VEE V3 = 1~ (VDD - VEE), V2 = it (VDD - VEE), VDD = V I


*4 Applicable to 0 1 - 0 80 terminals.
*5 Display data 1010 - DF = 40Hz, Current from VDD to VSS when the display data is not processing .
.*6 Display data 1010 - DF = 40Hz, Current from VDD to VSS when the display data is processing.
*7 Display data 1010 - DF = 40Hz, Current on VI, V3, V 4 and VEE terminals.

91
DOT MATRIX LCD DRIVER MSM5279GS . - - - - - - - - - - - - -
SWITCHING CHARACTERISTICS
(Voo = 5V 10%. T a = -20""'-' +B5C CL = 15pF)

Parameter Symbol Conditions MIN TYP MAX Unit

tpLH.
"H". "L" propagation delay time - - - 250 ns
tpHL
MAX. clock frequency fCp DUTY = 50% 3 - - MHz
CP ELCK pulse width tw - 125 - - ns
Load pulse width tW(L) - 125 - - ns
Data setup time tsetup - 100 - ... ns
CP -+ LOAD time tCL - 250 - - ns
LOAD -+CP time tLC - 0 - - ns
Data hold time CP -+ 0 0 ""'-' 03. ECLK -+ LOAD thold - 100 - - ns

tr
Clock pulse Rising/Falling time - - - 50 ns
tf
tr( L)
Load pulse Rising/Falling time
tf(L)
- - - 1 J1s

CP -+ ECLK time tCE - 0 - - ns


ECLK -+CP time tEC - 150 - - ns

tf
tw tw i tf

I O.BVO~
~r-O.BVOD O.BVOO iit>:BVoo
CP
I\r 0.2VOO ,JrO. 2V oo ~ 0. 2V OO
tsetup thold tsetl!Q thold

On -03

>-
faB
k-Voo

0.2
Voo
O.B ~
VOO
1

:,.-- teE
K
tCL
~
O.B
rVOO Vo~

b.2
Voo
O.B ~

0.2
Voo
t
tr tw I

. ~O.BVoo o.BVoo -'r- tEC


ECLK
-L 0. 2V oo tf \r-O.2VDO

t r ( Ll tsetup thold tt(L)

tLC
I)f"o.BV oo twILl ~~n-~
LOAD. ER(EL) Pt- 0 .2V OO
r 0. 2V OO
(Input) tpLH
tpHL

EL(ER) '}tc..
I- O.BVOO
0 . 2V ::m
(Output)

92
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5279GS.

POWER DOWN FUNCTION


When more than two MSM5279GSs are being connected in series, cascade connection, power down function of
MSM5279GS can be utilized using the ENABLE F/F (flip flop circuit) in individual MSM5279GSs. (Regarding
the internal circ'uit configuration of MSM5279GS, refer to the figure below.) The display data is processed only in
the MSM5279GS, the ENABLE F/F of which is being activated by setting its ER and EL at high level, while the
display data is not processed in the MSM5279GS, the ENABLE F/F of which is not being activated and the low
power consumption condition (lDD SBY) is being held. The activated condition of this ENABLE F/F is being shifted
to next MSM5279GS one after another so that the ENABLE F/F of only one MSM5279GS out of the cascade
connected MSM5279GSs should be being activated.

-~
CP 4-bit x 20
SHIFT CP I

EL
>-...- ___-<1 ER

ECLK

SHL("")---.....- -
Internal circuit I
___ c_o_n_fi_9U~tion of MSM52~~

LOAD
(1st MSM5279GS's Ell

CP

ECLK

E F/F(ERI
1st
MSM5279GS
{ SHIFT CP

E F/F(ELl - - - - I J - - - - - . . ; . . J
2nd
E F/F(ER)
MSM5279GS
{
SHIFT CP

SHL="H" (EL=lnput ER = Output)


First MSM5279GS's ER should be
connected to second MSM5279GS's E L

Timing chart when MSM5279GS's are connected in series (cascade connection)

93
DOT MATRIX LCD DRIVER MSM5279GS . - - - - - - - - - - - - -

PIN DESCRIPTION

ER, EL

Pin I nput/Output SHL Description


ER Input Input pin to ENABLE F/F of MSM5279GS.
L
Output pin of ENABLE F/F. EL is connected to next MSM5279GS's ER
EL Output
when MSM5279GSs are connected in series (cascade connection).

EL Input Input pin to ENABLE F/F of MSM5279GS.


H
Output pin of ENABLE F/F. ER is connected to next MSM5279GS's EL
ER Output
when MSM5279GSs are connected in series (cascade connection).

ELCK
Clock pulse input pin for ENABLE F/F. The active falling edge of the clock pulse. The clock pulse,
condition of ENABLE F/F is shifted to next which was input when the ENABLE F/F is not
MSM5279GS's ENABLE F/F at the falling edge active condition, is invalid.
of the clock pulse. ELCK is required every 20
CPo (Clock Pulse). SHL
ER and EL can be used as either input pin or output
pin according to the HI L condition of SH L. The
CP
Clock pulse input pin for the .4bit parallel shift shifting direction of each data, Do - D 3 , the Inputl
register. The data is shifted to 80-bit latch at the Output condition of ER and EL and the H/L
condition of SHL are described in the table below.

SHL ER EL Shifting direction

Do ~ 01 ~ Os - 0 7 7
Dl ~ 02 ~ 06 ~078
L Input Output
D2 ~ 03 ~ 0 7 ~079
D3 ~ 04 ~ Os ~080

Do ~ 080 ~ 0 76 ----+ 04
Dl ~ 0 79 ~ 075 ----+ 03
H Output Input
D2 ~ 078 ~ 0 74 ----+ O2
D3 ~ 0 77 ~ 073 ----+ 01

t t
end data start data

0 0 ,0 1 ,0 2 ,03 combination of Do - D3 level, DF signal, display


Data input pins for 4-bit parallel shift register and data output level and the display on the LCD panel
it is input synchronized with the clock pulse. The is described on the table below.

DO-D3 OF Display data output level Display on the LCD

L L V3 OFF

H L VI ON

L H V4 OFF
H H VEE ON

LOAD When more than two MSM5279GSs are connected


The signal for latching the shift register contents in series, cascade connection, the first MSM5279GS's
is input from this pin. When LOAD pin is set at EL terminal (when SHL = "H") or ER terminal
"H" level, the shift register contents are transferred (when SHL = "L") should be connected with first
to 80-bit latch at the falling edge of the LOAD pulse. MSM5279GS's LOAD terminal.

94
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5279GS.

OF Vt. V3. V4. VEE


Alternate signal input pin for LCD driving. Frame Bias supply voltage pin to drive the LCD. Bias
inversion signal is input to this terminal. voltage divided by the resistance is usually used
as supply voltage source. The figure below shows
VOO. Vss the case when bias voltage, which determines the
Supply voltage pins. VDD should be 4.5 - 5.5V. LCD driving voltage, is supplied from the external
VSS is a ground pin (VSS = OV) source. VI is not necessarily connected with VDD'

VDD
VDD
VI

MSM
V2 5279GS

V3 V, VEE.- Selecting level

V 3, V 4 - Nonselecting level
V4

Vs

1/11 Bias, 1/100 Duty


VEE
VSS

-11 --13V

The figure below shows the case when 'the bias


voltage is supplied by using Ope-Amps, which
enables the bias source low impedance and low
power consumption.

VDD

VI VDD
MSM
V2 5279GS

V3

V4 Ope-Amp voltage follower

Vs

1/11 Bias, 1/100 Duty


VEE
VR
VSS

--11 - -13V

0 1 - 0 80
Display data output pin which corresponds to the
OF Latched data Display data output level
respective .Iatch contents. One of VI, V3, V4
and VEE is selected as a display driving voltage L L V3
source according to the combination of the latched L H VI
data level and OF signal. (Refer to the truth table
on the right). H L V4
H H VEE
Truth table

95
DOT MATRIX LCD DRIVER MSM5279GS. - - - - - - - - - - - - -

TIME CHART
1/100 duty. 1/11 Bias

1-100-1-- 1 + 2 -- +100+ 1 +2-

11 ~
LOAD
I
JL.Jl..---1L-

[
LATCH
DATA =cx=x=
I
~ VOO

OF ~ ~
II

OF ~L-~ _ _ __ vJ
LOAD V~ I VLCO
Ou -0 ..

CP
vel
Vd

LATCH DATA Ve

VR

[~:::HOATA ~
~
I I -11--13V

~~
~~"
Voo(Vd
1+ --.J---+I ~
I
I
I
I

l
Va I ! I
I
I I I va=vDD-lI11 VLCD
Vb
I
Vb'VOO-2111 VLCD

_1 VLCO

J
I I
VC=VOO-9111 VLCO
I
Vc Vd=VOO-l0Ill VLCO

Vd
Ve=VOO-VLCO
Ve

~
ER input I
SHL="L" (MSM5279GS's load signal)
ECLK

First MSM5279GS'~ EL output


Ne.t MSM5279GS's ER input
Ne.tMSM5279~G~S~'s____________~__________________ -i.r-__________ ~

EL output

Interface with MSM6255GS

96

."
."
r
n

:::!
VOO + 5V o
VSS OV
JJ, 11 II ::----- :2
n

Controller
III, ,rl 1 I II ,11 1 I " -:~-- :c
n
c
MSM5278
=i
LOA1) O-OJ V,-VEE
FRAME
ECLK SHL ~
Vss
LOAD
EL MSM5279 VOO
OF ER
OF 0------0
x8

ECLK

C
CP
4100
LCD PANEL 1640 x 200)
o~
Do -03IUP) r:: s:
SEG641 SEG720 SEG721 SEG800 SEG1201

--------1
SEG1280

-i
61 x8
00-0) (DOWN) vOO
1 :c
~:8~-v
vss OF080MSM5:179 - 0,

j
t-_ _ _-+-I SHL
X
~
--- ER e~D f--
ECLK SHL r
MSM5278 LOAD VSS n
]p 0 0 -03 V,-VEE c
h f4 c
:c
II' ' I lj 1 I II III 1 I II ~~~_ <:
m
:c
II' 11 1l---~-======~----.J
s:
(I)
V s:
01
f\)
.....
e.g
G)
(I)
ID
.....

~
98
DOT
MATRIX
LCD
CONTROLLER
OKI semiconductor
MSM6222B-01GS
DOT MATRIX LCD CONTROLLER WITH 16 DOT COMMON DRIVER AND 40
DOT SEGMENT DR IVER

GENERAL DESCRIPTION
The OKI MSM62228-01 GS is a dot matrix LCD controller which is fabricated by low power CMOS silicon gate tech-
nology. In combination with 4-bit/8-bit microcontroller, character display on the dot matrix character type LCD can
be effected. This LSI consists of 16 dot COMMON driver, 40 dot SEGMENT driver, DISPLAY RAM, character
generator RAM, character generator ROM and control circuit.
Max. 80 characters' display can be controlled by MSM62228-01 GS by using together with the MSM5259GS.

The OKI MSM62228-01GS has the same. performance as HD44780. There is, however, slight differences between
these two devices as described in the table on page 101.

MSM62228 has ROM area for character code that can be programmed by custom mask. -01 GS is the standard version
with 160 characters, with small letter font 5 X 7, and 32 characters, with capital letter font 5 X 10, in this ROM area.

FEATURES
Easy interface with an 8-bit or 4-bit microcontroller. Character patterns can be programmable by CG
Dot matrix LCD controller/driver for small letter RAM. (Small letter font: 8 kinds, 5 X 8 dots, Capital
font (6 X 7 dots) or capital letter font (5 X 10 dots). letter font: 4 kinds, 5 X 11 dots).
Automatic power ON reset. Oscillation circuit for external register or ceramic
COMMON signal drivers (16) and SEGMENT signal resonator.
drivers (40). 1/8 duty (1 line; 5 X 7 dots + cursor), 1/11 duty
Control up to 80 characters when used in combina- (1 line; 5 X 10 dots + cursor), or 1/16 duty (2 lines;
tion with MSM5259GS. 5 X 7 dots + cursor), selectable.
Character generator ROM for 160 characters with Clear display even in case of 1/5 bias, 3.0V LCD
small letter font (5 X 7 dots) and 32 characters driving voltage.
with capital letter font (5 X 10 dots).

100
- - - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B01GS

PIN CONFIGURATION
(Top View)

,... <.0 U1 '" M N

88g8888~~~

SEG 33 DB 1
SEG 37 UB 0
SEG 36

SEG 34 RS
SEG 33 DD
SEG 32
S~G 31 VDD
SEG 30 CP
SEG 29
SEG 28 V.
SEG 27 V,
SEG 26 V .
V,
SEG 25
SEG 24 V,

SEG 23 osc 2

N co .....
............ (,0
__ .n ~
.... COl
__ N
co - t.O .n
........ O'l 'Of M N
~ 0 u
~~~~~~~~~~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ w
V)
Z
<.:l
V)
0

Item HD44780 MSM6222B-Ol GS

LCD driving voltage


1/4 bias 3.0 -- 11.0 (V) 3.0 -- 8.0 (V)
1/5 bias 4.6 -- 11.0 (V) 3.0 -- 8.0 (V)

Bus interface speed


1 MHz (1000 ns) 1.5 MHz (667 ns)
with CPU
Signal rising/falling time is quite
fast. So, the conduction between
lines of the PCB and the cable
assignment are very important.

The increment and The address counter is incre- The address counter is incre-
decrement of the mented or decremented 6 p sec mented or decremented during
address counter in (when fosc = 250 KHZ) after the busy condition.
writing/reading the the busy condition i~ released. So, data can be written into/
data to/from the (Period of busy condition is read out from the RAM immedi-
CGRAM/DDRAM. 40ps) ately after the busy condition
So, the data cannot be written was over.
into/read out from the RAM
for 6 psec after the busy
condition was over.

101
~
o
N
tc
r-
C
0 0
(") -I
~
c s:
VOO r----------------------------------------------------------------------o L -I
GNO r---------------------------------------------------------------------~O CP
l>
G) :tI
~----------------------------------------------------------------------O OF jJ
X
s: r-
OSC 1 (")
OSC2
c
(")
Cursor blink
0

~
16-bit
control shift 2:
register -I
E
8 Iinstruction
c:J COMl-16
jJ
0
RS r-
decoder Parallell r-
R/W (101
Character
generator
M serial
c~Jnver-
sIan
m
jJ

OBo - DB"
RAM
(CGR~
s:
C/)
5 s:
0)

~ter
I\)

r
8 I\)
OB4 - OB 7
I\)
tc
:~~~~I.r ~40-~
it ~seg-

-
generator
ROM 140-bil
0 ment
signal SEG 1 _ 40
6
latc driver
(CG RAMI Q
C/)

VI 0--- ,
i
~ Display data

I ~n~~:~::
0---

F
V2
V.l 0--- RAM
V4 0--- (DO RAMI
V, 0---
L.--J L.--J
Y DO
- - - - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6222B-01GS -

ABSOLUTE MAXIMUM RATING

Applicable
Parameter Symbol Condition Value Unit terminal
Supply voltage Voo Ta = 25C -0.3 -+ 7.0 V VOO - GNO
Supply voltage for Vi. V2. V3 VOO - 9.0- Vi. V 2 V3
LCO displaying Ta = 25C V
V4. V S VOO + 0.3 V4. V S
R/W. RS. E.
Input voltage VIN Ta = 25C -0.3 -VOO + 0.3 V OBo -OB7
OSC1
Permissible loss Po - 500 mW -
Storage temperature T stg - -55 -+ 125 c -
Operating temperature Topr - -20 -+75 c -

OPERATING RANGE

Applicable
Parameter Symbol Condition Value Unit terminal

Supply voltage VOO - 4.5 -5.5 V VOO


VOO-Vs(31 1/4 bias (1) 3.0 -8.0 V
LCO driving voltage (VLCO) VOO. Vs
1/5 bias (2) 3.0-8.0 V

Operating temperature Topr - -20 -+75 c -

(1) This voltage should be applied to VOO - V s.


Voltage applicable to Vi. V2. V3 and V4 are as follows.
(2) V l = VOO - 1/4 (VOO - Vs)
V2 = V3 = VOO -1/2 (VOO - V s )
V4 = VOO - 3/4 (VOO - V s )
(3) Vl = VOO -1/5 (VOO - Vs)
V 2 =VOO-2/5(VOO-Vs)
V3 = VOO -3/5 (VOO - Vs)
V4 = VOO - 4/5 (VOO - Vs)

103
DOT MATRIX LCD CONTROLLER MSM6222B-01GS ....- - - - - - - - -

DC CHARACTERISTICS
(VDD=4.S-S.sv, T a =-20-+7SoCI

Parameter Symbol Condition MIN TYP MAX Unit Applicable terminal


"H" input
VIH1 - 2.2 - VDD V
voltage R/W, RS, E,
"L" input DBo -Dth
voltage VIL1 - -0.3 - 0.6 V

"H" input
voltage VIH2 - VDD - 1.0 - VDD V
OSC1
"L"input
voltage VIL2 - -0.3 - 1.0 V

"H" output
VOH1 10 = -0.20SmA 2.4 - V
voltage
DBo - DB 7
"L" output
VOL1 10 = O.4mA - - 0.4 V
voltage
"H" output
VOH2 10 = -40JlA 0.9VDD - V
voltage DO, CP, L,
"L" output DC,OSC2
VOL2 10 = 40JlA - - 0.1VDD V
voltage
COM voltage 10 = SOJlA
drop
Vc - - 2.9 V COMI -COM 16
Note 1
SEG voltage 10 = SOJlA
drop
Vs
Note 1 - - 3.8 V SEGI -SEG 40

Input leak VIN = OV - - -1 JlA E


current IlL
VIN = VDD - - 1 JlA
"L" input VDD = S.OV -50 -12S -2S0 JlA R/W RS
current IlL
VIN = OV -30 -92.S -185 JlA DBo - DB 7
"H" input
current
IIH VIN = VDD - - 2 JlA

104
- - - - - - - - - - - . . DOT MATRIX LCD CONTROLLER' MSM6222B01GS

Parameter Symbol Condition MIN TYP MAX Unit Applicable terminal


VDD = 5.0V
E = L level
registor oscillator
Current = 270KHz
consumption IDDI
R/W, RS, and
DBo to DB,
- 0.35 0.6 mA VDD
(1)
are open.
Output terminals
are all no load.
See Note 2.

VDD = 5V, cera-


mic oscillator.
fOSC = 250 KHz.
E is in "L" level.
Current
R/W, RS, and
consumption IDD2 - 0.55 0.8 mA VDD
DBo to DB, are
(2)
open. Output
terminals are all
no load.
See Note 2.
Rf clock fOSC OSCl
Rf = 91 Kn 2% 380 KHz
oscillation 200 300 OSC2
Note 3
frequency
Clock input fiN OSC 2 is open.
150 250 380 KHz OSCl
frequency Input from OSCl
Input clock
fDuty Note 4 45 50 55 % OSCl
duty
Input clock
tfr Note 5 - - 0.2 J1S OSC1
rise time
Input clock
fall time
tft Note 5 - - 0.2 J1S OSCl

Ceramic filter fOSC Rf = 1 Mn, 245 250 255 KHz OSCl


oscillation CI = C2 OSC2
frequency = 680 PF,
Rd = 3.3 Kn,
and ceramic
filter CS8250A.
See Note 6.
LCD driving VLCD Refer to the VDD - Vs
bias input interface between 4.0 8.0 V potential
voltage L~D and
MSM5839GS.

(Note 1) Applied to the voltage drop (VC) occuring from terminals VDD, VI, V4, and Vs to each COMMON
terminal (COM1 to COM16) when 50 J-LA is flown in or out to and from all COM and SEG terminals,
and also to voltage drop (VS) occurring from terminals VDD, V2, V 3 , and Vs to each SEG terminal
(SEGl to SEG401.

When output level is at VDD, VI, or V 2 level, 50 p.A is flown out, while 50 p.A is flown in when the
output level is at V3, V4 or Vs level.

This occurs when 5V or -5V is input to VDD, VI, and V3 or to V2, V4, ann Vs, respectively.

(Note 2) Applied to the current value flown in terminal VDD when power is input as follows:
VDD =5V, GND = OV, VI = 3.4V, V2 = 1.8V, V3 = 0.2V, V 4 = -1.4V, and V2 = -3V.

105
DOT MATRIX LCD CONTROLLER MSM6222B-01GS ...- - - - - - - - -

(Note 31

Rf=91Kfb2%
OSC1P
Rf
OSC2
Minimum wiring is recommended between OSC 1 and Rf and
between OSC 2 and Rt.

(Note 41

Applied to pulse input


from OSC 1.

fDuty = tHW/(tHW + tLwl x 100 (%1

(Note 51

Applied to pulse
input from OSC 1.
0.3VDD

ttr
tff

(Note 61

C1
OSC 1

/'v-t=l-4-~c"'m;' I.""
..-.-..R-'V'\f

OSC 2
Ad 2ti
Ceramic filter CSB250D (MURATA SEISAKUSHO Works I
At 1Mn 10%
C1 = C2 680pF 10%
Ad 3.3Kn 5%

106
- - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B01GS.

(Note) Input the voltage listed in the table below to VI - V 5:

~ Terminal

VI
number!

V
lline mode

VLCD V
2line mode

VLCD
DD- - 4 - DD- - 5 -

V VLCD V 2VLCD
V2 DD- - 2 - DD - --5-.

V VLCD V 3VLCD
V3 DD- - 2 - D D - --
5
V 3VLCD V 4VLCD
V4 D D - -- DD- - - 5 -
4

Vs VDD - VLCD VDD - VLCD

VLCD is the LCD driving voltage. (For UN (LCD line number!, refer to the initial set of the instruction code.)

INPUT/OUTPUT CIRCUIT

VDD

Applied to terminal E. Applied to terminals R/W


and RS.

VDD VDD

VDD

VDD

~CONTROL

~DATA Applied to DO, CP, L,


and DF.

Applied to DBo - DB7'

107
DOT MATRIX LCD CONTROLLER' MSM6222B01GS .11---------

PIN DESCRIPTION

Terminal Name Function


R/W Read/write selection input terminal.
"H": Read, and "L": Write
RS Register selection input terminal.
"H": Data register, and "L": Instruction register
E Input terminal for data input/output between CPU and MSM6222B.Q1 GS and for
instruction register activation.
DBo - DB, Input/output terminal for data send/receive between CPU and MSM6222B.Q1 GS
OSC1,OSC2 Clock oscillating terminal required for internal operation upon receipt of the LCD drive
signal and CPU instruction.
COM 1 -COM16 LCD COMMON signal output terminal.
SEG1 -SEG40 LCD SEGMENT signal output terminal.
DO Output terminal to be connected to MSM5259GS to expend the number of
characters to be displayed.
CP Clock output terminal used when DO terminal data output shifts the inside of
MSM5259GS.
L Clock output terminal for the serially transfered data to be latched to MSM5259GS.
OF The alternating signal (OF, display frequency) output pin.
VDD Power supply pin.
GND Ground pin.
Vl -Vs Bias voltage input pin to drive the LCD.

10B
- - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6222B01GS-

FUNCTIONAL DESCRIPTION
1. Instruction Register (I R) and
Data Register (DR)
These two registers are" selected by the register When an address code is written to IR, the data (of
selector (RS) terminal. the specified address) is automatically transferred
The DR is selected when the "H" level is input and from the DD RAM or CG RAM to the DR. By
I R when the "L" level is input. having the CPU subsequently read the DR (from
The I R is used to store the address code and the DR data), it is possible to verify DD RAM or
instruction code of the display data RAM (DD CG RAM data.
RAM) or character generator RM (CG RAM). After the writing of DR by the CPU, the DD RAM
The IR can be written into, but not be read out by or CG RAM of the next address is selected to be
the microcontroller (or CPU). ready for the next CPU writing.
The DR is used to write into/read out the data to/ Likewise, after the reading out of DR by the CPU,
from the DD RAM or CGRAM. DD RAM or CG RAM data is read out by the DR
The data written to DR by the CPU is automatically to be ready for the next CPU reading.
written to the DD RAM or CG RAM as an internal Write/read to and from both registers is carried out
operation. by the READ/WRITE (R/W) terminal.

Table 1 Register and R/W terminals function table

R/W RS Function
L L IR write
H L Read of 'busy flag (B F) and address counter (ADC)
L H DR write
H H DR read

2. Busy Flag (BF) deciding whether it is DD RAM or CG RAM, the


address code is transferred from I R to ADC. After
When the busy flgag output is at "H", it indicates writing (reading) the display data to (from) the
that the MSM6222B-01 GS is engaged in internal DD RAM or CG RAM, the ADC increments (decre-
operation. ments) by 1 as its internal operation.
When the busy flag is at "H" level, any new instruc- The data of the ADC is output to DBO - DB6 under
tion is ignored.
the conditions that R/W = "H", RS = L, and BF =
When R/W = "H" and RS = "L", the busy flag is
"L".
output from DB7.
New instruction should be input when BF is "L"
4. Timing Generator Circuit
level.
When the busy flag is set to "H", the output code This circuit is used to generate timing signals to
of the address counter (ADC) cannot be fixed. activate internal operations upon receipt of CPU
instruction and also from such internal circuits as
the DD RAM, CG RAM, and CG ROM.
It is so designed that the internal operation caused
by accessing from the CPU will not interfere with
3. Address Counter (ADC) the internal operation caused by LCD display.
The address counter (ADC) allocates the address Consequently, when data is written from the CPU
for the DD RAM and CG RAM write/read and also to DD RAM no ill effect, e.g., flickering occurs in
for the cursor display. other than the display area where the data is written.
When the instruction code for a DO- RAM address I n addition, the circuit generates the transfer signal
or CG RAM address setting is input to I R, after to MSM5259GS for display character expansion.

109
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - - -

5. Display Data RAM (DD RAM)


This RAM is used to store display data of 8-bit
character codes (see Table 21-
DD RAM address corresponds to the display posit-
tion of the LCD. The coordination between the two
is described in the following.

DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:


DB6 DBo

ADC MSB LSB

Hexadecimal notation Hexadecimal notation

(Example)
When DD RAM L H L H L H L
address is 2A

2 A

(1) Coordination between address and display position in the 1-line display mode

First
digit 2 3 4 5 79 80 ~ Display position

I 00
I 01 0'2 03 04 ~ 4E 4 F f - - DD RAM address (hex.)

MSB
f
LSB

When the MSM6222B-01 GS is used alone, 8 characters max. can be displayed from the first digit to the eighth
digit.
First
digit 2 3 4 5 6 7 8

I 00 01 02 03 04 05 06 07

When the display is shifted by instruction, the coordination between the LCD display position and the DD RAM
address changes as shown below:

First
(Display digit 2 3 4 5 6 7 8
shifted
to right)
I 4F
I 00 01 02 03 04 05 06

First
(Display digit 2 3 4 5 6 7 8
shifted
to left) I 01 02 03 04 05 06 07 08

110
- - - - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6222B-01GS

When the MSM6222GS is used with one MSM5259GS, 16 characters max. can be displayed from the first digit
to the sixteenth digit as shown below:

First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

I 00 01 02 03 04 05 06 07 08 09 OA OB OC 00 OE OF

MSM6222B01GS display MSM5259GS display

When the display is shifted by instruction, the coordination between the LCD display and DO RAM address
changes as shown below:

First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(Display shifted to right) 14F 1 00 I I 01 02 1 03 1 04 1 05 1 06 1 07 1 08 1 09 1OA I I
OB OC 100 I I
OE

MSM6222B-01GS display MSM5259GS display

(Display shifted to left) \ 01 \ 02\ 03 \ 04 \ 05\ 06\ 07 \ 08\ 09\ OA \ OB \ OC \ 00 \ OE \ OF \10 \

Since the MSM6222B-01 GS has a DO RAM capacity for 80 characters, max. 9 pieces of MSM5259GS can be
connected to MSM6222B-01 GS so that 80 characters can be displayed.

First

MSM6222B-01GS display MSM5259GS (11 display MSM5259GS (2) MSM5259GS (9) display
- (8) display

111
DOT MATR IX LCD CONTROLLER MSM6222B01GS ...- - - - - - - - -

(2) Coordination between address and display position in the 2line display mode
First

First line
Second line
digit
00 01
2

I 40 I 41 I 42 I
3
02
4
03
43
5
04

I 44 I
39
26

I 66 I
::V-
40 - Display position

DO RAM ,dd"" (hox.J

(Note) Note that the last address of the first line is not consecutive to the head address of the second line.

When MSM6222B-01 GS is ued alone, 16 characters (8 characters x 2 lines) max. can be displayed from the first
digit to the eight digit.
First

First line
Second line

When the display is shifted by instruction, the coordination between the LCD display position and the DD
RAM address changes as shown below:
First
2 3 4 5 6 7 8
First line
(Display shifted to right)
Second line

2 3 4 5 6 7 8
First line
(Display shifted to left)
Second line

When the MSM6222B-01 GS is used with one MSM5259GS, 32 characters (16 characters x 2 lines) max. can be
displayed from the first digit to the sixteenth digit.

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
First line
Second line

MSM6222B-01 GS display MSM5259GS display

112
- - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B-01GS

When the display is shifted by instruction, the coordination between the LCD display position and the DD
RAM address changes as shown below:

(Display shifted to right)


First
digit 2 3 4 5 6 7 a 9 10 11 12 13 14 15 16
First line
Second line

I\,
y Y
MSM6222B-01 GS display MSM5259GS display

(Display shifted to left)


First
digit 2 3 4 5 6 7 a 9 10 11 12 13 14 15 16
First line
Second line

J\.
y y
MSM6222B-01 GS display MSM5259GS display

Since the MSM6222B-01 GS has a DD RAM capacity for 80 characters, max. 4 pieces of MSM5259GS can
be connected to the MSM6222B-01 GS in the 2-line display mode.

3 4 5 6 7 a 9 10 11 12 13 14 15 16 17
First line
Second line
~ ________ ~ ________ -J~ ________ ~ ________ .-J'~~ ________ ~ _ _ _ _ _ _ _ _- J

MSM6222B01GS display MSM5259GS (1) display MSM5259GS MSM5259 (4) display


(2)-(3)
display

6. Character Generator ROM (CG ROM)


The CG ROM is used to generate 5 X 7 dot (160
kinds) character patterns or 5 X 10 dot (32 kinds)
character patterns from an abit DD RAM character
code signal.
The coordination between abit character codes
and character patterns is shown in Table 2.
When the abit character code of a CG ROM is
written to the DD RAM, the character pattern of
the CG ROM corresponding to the code is displayed
on the LCD display position corresponding to the
DO RAM address.

113
~
~

:-
Table 2 Table of correspondence for character codes and characters (character pattern)

c
o
-f

~ s
MSB
Lower BIT

-
1101
0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1110 1111

,
4 BIT

0000
LSB
CG
RAM (1) 08 @fij p ~ " .... p p -
'/ ~ : ~ 0: liP -f
::0

! 1 Ag X
Q~ a~ q~ 'J :,
'Ii .~ 'Iq
...
(2)
! I D ri
0001 r
n
r ftP He
.. I. r [ f
0010
(3) 2 ~.. B B R f( b 1:.1 r
., ,
....
01 c
n
0011
(4)
"i C 55 3::=; c cC sS .1 "'.~ ''''l 0000 '. :e f,
~
.~
o
:2
-f
$$ 44 DD T I
0100

0101
(5)

(6)
55 EE u l
~ ~..
d c:I I t ... , I I,t- \' l' ~ IJ Q~
eEl uL .
~" ' t 'J ~ 13 iiU
'

. ::0
o
r
r
m

--
::0
0110
m && 6 F vU 6 F ff vl) 7::; 11 '3 r: I;
Pp S
0111

1000
(8)

(1)
,

(
77 ~
wLL gg J 77
( 88 HH xX hh xx [ .j
G [ ... w ... :-' ::<
'/ ., i:;
,~ ~g

" 1.1 V .,
rrJl
~
\:.-,.:..
en
S
en
I\)
I\)
I\)

I Yy ii . .J '.J to
) It -I
Yy
.
(2) ) 9Q I Y~ ~ 'r
6
1001 " 'l
-i ....a

lJ zZ i..l zz !~
iJ r~
G')

**+ ; ::E ..... " ."1 " [I en


(3) '
1010 ' 1.

1011
(4)
+ ; K~ [ [ klc: { { ~" "~ "t II Ij X :-:
lin
1100
(5)
. J LL I 1 I I '.' .,., >:J ,..,.I "- (l
'.I l' .~ 1'1 PI
--
"

== MM I ] mfil } } " ::a: ..... :-:-


. ?? NN
(9)
'..:I "
:"J

"0.
1101

1110 (7)
, > ) 1\ A
n rl -~ '3 1:~ : ;t . .. ...
~ n
I.)
1111
(8)
1/ o (
- - 0 --Eo ' IIJ 'J
"~
a
- - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6222B-01GS-

7. Character Generator RAM (CG RAM) character code "00" (hex.l or "OS" (hex.l.
When the S-bit character code of the CG
The CG RAM is used to display user's original char- RAM is written to the DD RAM, the
acter patterns other than the CG ROM. character pattern of the CG RAM is dis-
The CG RAM has the capacity (64 bytes = 512 bits) played on the LCD display position cor-
to write S kinds for 5 X 7 dots and 4 kinds for responding to the DD RAM address. (DD
5 X 10 dots. RAM data, bit 0-2 correspond to CG
When displaying character patterns stored in the RAM address, bit 3-5.)
CG RAM, write Sbit character codes (00-07 or
02 to OF; hex.) on the left side as shown in Table 2.
(2) When character pattern is 5 x 10 dots
It is then possible to output the character pattern
(See Table 3-2)
to the LCD display position corresponding to the
DD RAM address. A method to write character pattern into
The following is a description on how tel write and the CG RAM by the CPU
read character patterns to and from the CG RAM. Four bits of CG RAM address, bit 0-3,
correspond to the line position of the char-
(1) When the character pattern is 5 X 7 dots acter pattern.
(See Table 3-1).
First, set increment or decrement by the
A method to write character pattern into CPU, and then input the address of the CG
CG RAM by CPU: RAM.
Three bits of CG RAM address 0-2 corre- After this, write the character pattern code
spond to the line position of the character into the CG RAM, line by line from DBo-
pattern. DB7.
First, set increment or decrement by the DBo to DB7 correspond to CG RAM data,
CPU, and then input the CG RAM address. bit 0-7, in Table 3-2.
After this, write character pattern codes It is displayed when "H" is set as the
into CG RAM through DBo "'" DB7 line by input data, while it is not displayed when
line. "L" is set as the input data.
DBo to DB7 correspond to CG RAM data As the ADC is automatically incremented or
0-7 in Table 3-1. decremented by 1 after the writing of
It is displayed when "H" is set as input data to the CG RAM, it is not necessary to
data and is not display when "L" is set set the CG RAM address again.
as input data. The line in which the CG RAM address a
Since the ADC is automatically incremented to 3 is "A" (hex) is ORed with cursor at
or decremented by 1 after the writing of the cursor position and displayed on the
data to the CG RAM, it is not necessary to LCD.
set the CG RAM address again. When the CG RAM data, bit 0-4, CG
The line, the CG. RAM address 0-2 of RAM address, bit 0-3, is "a" "'" "A",
which are all "H" ("7" in hexadecimal it is displayed on the LCD as the display
notation), is the cursor position. It is ORed data. When the CG RAM data, bit of 5-7,
with the cursor at the cursor position and and CG RAM, bit data is 0-4 and CG RAM
displayed to LCD. address data is "B" "'" "F", it is not output
For th is reason, it is necessary to set all to the LCD.
input data that become cursor positions But in this case, CG RAM can be used as
to "L". RAM and it can be written into/read out.
Although CG RAM data 0-4 bit are output So, it can be used as the data RAM.
to the LCD as display data, CG RAM data
bit 5-7 are not. The latter can be written A method to display the CG RAM character
and read to and from the RAM, it is there- pattern to the LCD:
fore allowed to be used as data RAM. The CG RAM is selected when 4-upper
Accordingly, it is necessary to set all input order bits MSB of the character code are
data which become cursor positions to "H". all "L".
0-4 bit of CG RAM data are output to the As MSB and LSB of character code LSD
LCD as the display data, however, 5-7 bit are invalid, the display of "year" ~ in Kanji
of CG RAM data are not. But it can be used character is selected by character codes
as RAM because data can be written/read "00", "01", "OS", and "Og" (hex.l as in
into/from it. Table 3-2.
A method to display the CG RAM character When the CG RAM character code is written
pattern to the LCD: to the DD RAM, the CG RAM 'character
The CG RAM is selected when 4-upper pattern is displayed on the LCD display
order bits MSB of the character code are position corresponding to the DD RAM
all "L". address.
As character code bit 3 is invalid, the dis- (DD RAM data bit 1, 2 correspond to CG
play of "a" in Table 3-1, is selected by RAM address bit 4,5.)

115
DOT MATRIX LCD CONTROLLER' MSM6222B-01GS .....- - - - - - - - -

CG RAM data DD RAM data


CG RAM address
(character pattern) (character code)
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 543 2 1 0
MSB LSB MSB LSB MSB LSB
L L L L L L X X X L H H H L
L L H H L L L H
L H L H L L L H
L H H H L L L H

L
\L
H
H
H
H
H L
L
L
H
H
L
L
H
L
H
L
\ H
H
L
L
X X X H
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
H
L L L L X L L L

l~
L L H

~
L H L H L H L L
L H H H H L L L
H L L H L H L L L L L L X L L H
H L H H L L H L
H H L H L L L H
H H H L L L L L
I-- _________ -

I~-
- ~~ -----.....
H H H L L L X X X LI!!..H,!!JL
L H L L H L L

~
L
L H L L L H L L

)
L H H L L H L L
H L L L L H L L L L L t X H H H
H L H L L H L L
H H L LfE Hf:ilL
H H H L L L L L

X: Irrespective of H/L

Table 3-1 Relation between CG RAM data (character pattern) vs. CG RAM address and DO RAM data vs. charac-
ter pattern when the caracter pattern is 5 X 7 dots. Above example indicate "OKI".

116
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6222B01GS.

CG RAM data DO RAM data


CG RAM address
(character pattern) (character code)
5 4 3 2 1 0 7 6 5 432 1 0 76543210
MSB LSB MSB LSB MSB LSB
L L L L L L X X X L fHlL L L

H~
L L L H
L L H L IH L LIH L
L H
L L H H L H H H H
L H L L L HITIH L
L H L H IHHHHH L L L L X L L X
L H H L L L L H L
L H H H L L L L L
H L L L L L L L L
H L L H L L L L L
HLHL LLLLL
-- - - \-1- - -- - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - f-- - - - - - - - - - - - - - - - - -
H L H H X X X X X

~~~; )
L H L L L L X X X L L L L L
L L L H L L L L L
L L H L L H H H H

I~ H~ ~
L L H H
L H L L
L H L H L L L L X L H X
L H H L L H H H H
L H H H L L L L H
H L L L L L L L H
H L L H L H H H L
H L H L L L L L L
-- - - tTH- [- "H-R - - - - - - - -- - -X-X-X -X -X- - -- - - - - - - - - - - - - - - - - - - - - - ------

)
:H H L L )
IH H L H
IH H H L
:H H H H
--- -- ______ I--::
/~----...--
L L L L X X X L L L L L
L L- L H L L L L L
L L H L H H L H H
L L H H L H L H L
L H L L IHLLLIHl L L L L X H H X
L H L H IHLLLIHI
L H H L L H H H L
L H H H L L L L L
H L L L L L L L L
H L L H L L L L L
IH L H L L L L L L
IH-I.-"H-"H-- - ---- --- -- -X-X-X- X-)f ---:--- -- - - -- - - -- -- --- - -- -------
:H H L L
:H H L H
:H H H L
IH H H H
)
X: Irrespective of H/L

Table 3-2 Relation between CG RAM dada (character pattern) example vs. CG RAM address and DO RAM data
vs. character pattern when the character pattern is 5 X 10 dots. Above examples indicate Sf. , g, v respec-
tively.

117
DOT MATRIX LCD CONTROLLER MSM6222B-01GS . 1 1 - - - - - - - - -

8. Cursor/Blink Control Circuit:


This is a circuit that generates the LCD cursor and address set to the ADC.
blink. The figure below shows an example of the curson/
This circuit is under the control of the CPU program. blink position when the value of ADC is set at "07"
The display of the cursor and blink on the LCD is (hex.).
made at a position corresponding to the DD RAM

DBO
ADC I L ILL L
' - - _ - - ._ _ -J.~

o 7

First
digit 2 3 4 5 6 7 8 9 79 80

In l-linedisplay mode I I I
00 01 02 1 03 1 04 1 05 1 061 ~71 081 ~14E 14FI
l Cursor and blink position

First
digit 2 3 4 5 6 7 8 9 39 40
Fi rst line
In 2line display mode {
Second line

Cursor and blink position

(Note) The cursor and blink are displayed even when the CG RAM address is set to ADC.
For this reason, it is necessary to inhibit the cursor and blink display while the CG RAM address is set to the
ADC.

9. LCD Display Circuit (COM 1 to 16, SEG


1 to 40, L, CP, DO, and OF):
As the MSM6222B-Ol GS provides the COM sig.nal (CP), latch output terminal (Ll. and display
outputs (16 pes.) and the SEG signal outputs (40 frequency termin~I, (DF). The character pattern
pes.), it can display 8 characters (l-line display) data is serially transferred to MSM5259GS thr<;lugh
or 16 characters (2-line display) as a unit. DO and CP. When the data of 72 characters 360-bit
The SEGl '" SEG40 are used to display 8 digit (= 5-bit/ch. x 72 ch. = l-line display) or 32 char-
display on the LCD. To expand the display, an acters 160-bit (5-bit/ch. x 32 ch. = 2-line display) is
MSM5259GS is used. output, the latch pulse is also output through
The MSM5259GS, 40 dot segement driver, is used term inal L. By th is latch pulse, the data transferred
for expansion of the SEG signal output. serially to MSM5259GS is latched to be used as
interface with the MSM5259GS is made' through display data. The display frequency signal (DF)
data output terminal (DO), clock output terminal required when LCD is displayed is also synchronous-
ly output from DF terminal with this latch pulse.

118
- - - - - - - - - . DOT MATRIX LCD CONTROLLER, MSM6222B-01GS.

10. Built-in Reset Circuit


The MSM6222B-Ol GS is automatically initialized Character font: 5 x 7 dots (F = L)
when the power is turned on. ADC: Increment (I/O = H)
During initialization, the busy flag (BF) holds No display shift (SH = L)
"H" and does not accept instructions (other than Display: Off (01 = L)
the busy flag read). Cursor: Off (C = L)
The busy flag goes to "H" for 15 ms after V DO No blink (B = L)
reaches 4.5V or more. When the builtin reset circuit is used, it is required
During initialization, the MSM6222B-Ol GS executes to satisfy the following power supply conditions.
the following instructions: As the built-in reset circuit does not operate normally
Display clear unless these power supply conditions are met,
Data length of interface with CPU: initialize the MSM6222B-Ol GS by instruction
8 bits (8B/4B = H) through the CPU (refer to initialize instruction).
LCD: l-line display (N = L) When a battery is used as supply voltage source, it
is required to initialize the instruction.

I
I
0.2 V I 0.2 V

Voo I I
I
~I
tOFF

I
tON;;;;' 100 ms tOFF;;;;' 1 ms

Fig 1 Power ON/OFF waveform

11. Data Bus with CPU The first time data input/output is made for
4-high order bits (DB4 to DB7 when the
The data bus with CPU is available either once for interfaces data length is 8 bits) and the second
8 bits or twice for 4 bits allowing the MSM6222B- time data input/output is made for 4-low
01GS to be interfaced with either an 8-bit or 4-bit order bits (OBO to DB3 when the interface
CPU.
data length is 8 bits!' Even when the data
input/output can be completely made through
(1) When the interface data length is 8 bits
4-high order bits, be sure to make another
Data buses DBO to DB7 (8 pes.) are all used input/output of 4-low order bits. (Example:
and data input/output is carried out simul- Busy flag Read)
taneously. Since the data input/output is carried out in
two steps but as one execution, no normal
(2) When the interface data length is 4 bits data transfer is executed from the next input/
The 8-bit data input/output is carried out in output if accessed only once.
two steps by using only 4-high order bits of
data buses DB4 to DB7 (4 pes.!.

119
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - -

RS
/
I \
III R/W

Busy
J
(internal
operation) ===>< No
I
X 7 ~
'"
IR7 \'Bus y
DB7
Busy

DB6 ===>< IR6


X >eX ~ ~
DBs ==>< IR5
X >CY ~ ~
DB4 = = > < IR4
X >CY >S< ~
DB3==>< IR3
X >eX ~ ~
DB2 ===>< IR2
X >eX >E9< ~
DB.==X IRl
X >C)( >E9< ~
DBo==X IPQ
X >C)( ~ ~
Instruction Busy flag (BF) and address Data register
register counter (ADe) read (DR) write
(IR) write

Fig. 2 Example of 8bit data transfer

120
__________________________________ ~I
RS

R/W ------------~I \~_________

Busy (internal ~ ____________________~r___


C
opcr:ltion) o
-4
No~
DB7 ~ 7 \LOO)( \BUSY~- - - - - '~ s:
--_..... Busy -4
:c
OBI> ___. . .~ >CY>CX ~ ~ X
r-
DB,
---_~ >CY>CX ~ ~ (")
C
(")
DB4 ________~ >CY>CX ~ ~ o
2
-4
:c
Instruction register
(IR) write
Busy flag (BF) and address
counter (ADe) read
Data register
(DR) write
or-
r-
m
:c
s:
en
s:
en
N
N
N

-
OJ
Fig. 3 Example of 4bit data transfer 6
G)
... en
~

~
- DOT MATRIX LCD CONTROLLER MSM6222B-01GS - . . . . - - - - - - - - -

12. Instruction Code


the LCD display, the busy status continues longer
The instruction code is defined as the signal through than the CPU cycle time.
which the MSM6222B-01 GS is accessed by the CPU. Under the busy status (when the busy flag is set to
CPU. "H"), the MSM6222B-01GS does not execute any
The. MSM6222B-01 GS begins operation upon receipt instructions other than the busy flag read.
of the instruction code input. Therefore, the CPU has to verify that the busy flag
As the internal processing operation of MSM6222B- is set to "L" prior to the input of the instruction
01GS is started with a timing that does not affect code.

111 (1) Display clear:

Instruction code
R/W
L
RS
L L L
DBS
L L L L L
DBo
H

When this instruction is executed, the LCD (Note) All DO RAM data goes to "20" (hex.).
display is cleared. while the address counter (ADC) goes
When the cursor and blink are 'in display. the to "00" (hex.). The execution time,
blinking position moves to the left end of the when the OSC oscillation frequency
LCD (the left end of the first line in the 2line is 250 KHz is 1.64 ms (max.).
display model.

(2) Cursor home

R/W RS DB7 DB6 DBs DB4 DB3 DB2 OBI DBo


Instruction code L L L L L L L L H X
X: Irrespective of H/L

When this instruction is executed. the blinking (Note) The address counter (ADC) goes to
position moves to the left end of the LCD (to "00" (hex.). The execution time, when
the left end of the first line in the 2-line display the OSC oscillation frequency is
mode) when the cursor and blink are being 250 KHz, is 1.64 ms (max.).
displayed.
When the display is in shift, the display returns
to its original position before shifting.

(3) Shift mode set

R/W RS DB7 DB6 DBs DB4 DB3 DB2 OBI DBo


Instruction code L L L L L L L H I/O SH

CD When the I/O is set. the 8bit character code shifts to the left (I/O = H) or to the right
is written or read to and from the DO RAM, (I/O = L) by 1 character position.
the cursor and blink shift to the right by 1 When the character is read from the DO
character position (I/O = H; increment) or RAM when SH = H is set, or when the
to the left by 1 character position (I/O = L; character pattern data is written or read
decrement) . to or from the CG RAM when SH = H is
The address counter is incremented (I/O = H) set. the entire display does not shift. but
or decremented (I/O = L) by 1 at this time. normal write/read is performed (the entire
Even after the character pattern code is display does not shift. but the cursor and
written or read to and from the CG RAM. blink shift to the right (I/O = H) or to the
the address counter (ADC) is incremented left (I/O = L) by 1 character position.
(1/0= H) or decremented (I/O = L) by 1. When SH = L is set, the display does not
@ When SH = H is set, the character code is shift. but normal write/read is performed.
written to the DO RAM. and then the The execution time when the OSC oscillation
cursor 3nN blink stop and the entire display frequency is 250 KHz is 40 Jis.

122
- - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6222B01GS.

(4) Display mode set

R/W RS DB, DBs DBo


Instruction code L L L L L L H 01 C B

CD The 01 bit controls whether the character @ The blink is cancelled when B = L and it is
pattern is displayed or extinguished. executed when 01 = Hand B = H.
When 01 is "H", this bit makes the LCD In the blink mode, all dots (including the
display the character pattern. cursor), displaying character pattern, and
When 01 is "L", this bit distinguishes the cursor are displayed alternately at 409.6 ms
LCD character pattern. The cursor and (in 5 X 7 dots character font) or 563.2 ms
blink are also cancelled at this time. (in 5 X 10 dots character font) when the
(Note) Different from the display clear, esc oscillation frequency is 250 KHz.
the character code is absolutely The execution time when the esc
oscillation
not rewritten. frequency is 250 KHz is 40 /lS.
(3) The cursor goes off when C = L and it is
displayed when 01 = Hand C = H.

(5) Cursor and display shift

R/W RS DB, DBs DBo


Instruction code L L L L L L DIC R/L x x
X: I rrespective of HI L

When DIC = Land R/L = L, the cursor and blink positions are shifted from the first line
blink position are shifted to the left by 1 to the second line when the cursor is shifted
character position (A DC is then decremented to the right next to the fortieth digit (27; hex.)
by 1). in the first line. No such shifting is made in
When D/C = Land R/L = H, the cursor and other cases.
blink position are shifted to the right by 1 When shifting the entire display, the display
character position (A DC is then incremented pattern, cursor, and blink positions are in no
by 1). case shifted between lines (from the first line
When D/C = Hand R/L = L, the entire display to the second line or vice versa).
is shifted to the left by 1 character position. The execution time when the esc oscillation
The cursor and blink positions are also shifted frequency is 250 KHz is 40 /lS.
with the display (ADC remains unchanged).
When D/C = Hand R/L = H, the entire display
is shifted to right by 1 character position. The
cursor and blink positions are also shifted
with the display (ADC remains unchanged).
In the 2line display mode, the cursor and

(6) Initial set

R/W RS DB, DBO


Instruction code L L L L H I 8B/4B I N F x x
X: Irrespective of LIe
CD When 8B/4B = H, the data inputloutput to steps through of 4 bits DB7 to DB4.
and from the CPU is carried out simul- The 2-line display mode of the LCD is
taneously by means of 8 bits DB7 to DBO. selected when N = H, while the l-line
When 8B/4B = L, the data inputloutput to display mode is selected when N = L.
and from the CPU is carried out in two

123
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - -

@ The 5 X 7 dots character font is selected This initial set has to be accessed prior to
when F = L, while the 5 X 10 dots character other instructions excepting the busy flag
font is selected when F = Hand N = L. read after powering ON the MSM6222B
01GS.

Number of Number Number of


Character
N F display Duty ratio of COMMON
font
lines biases signals
L L lline 5 X 7 dots 1/8 4 8
L H lline 5 X 10 dots 1/11 4 11
H L 2line 5 X 7 dots 1/16 5 16
H H 2line 5 X 7 dots 1/16 5 16

Generate biases externally and input them


to the MSM6222B-Dl GS (VDD Vl, V2,
V3, V4, and V5). ,
When the number of biases is 4, input the
same potential to V2 and V3. The execution
time, when the OSC oscillation frequency
is 250 KHz, is 40 p.s.

(7) CG RAM address set

R/W RS DB, DBS DBo


Instruction code L L L H Cs Co

When CG RAM addresses, bit C s to Co from the CPU begins with addresses, bit Cs to
(binary), are set, the CG RAM is speCified, Co, starting from CG RAM selection.
until the DD RAM address is set. The execution time, when the OSC oscillation
Write/read of the character pattern to and frequency is 250 KHz, is 40 J,ls.

(8) DO RAM address set

R/W RS DB, DBs DBo


Instruction code L L H DS DO

When the DD RAM addresses D6 to DO (binary) Likewise, in the 2line mode, D6 to Do (binary)
are selected, the DD RAM is specified until must be set to one of the values among
the DD RAM address is set. "00" '" "27" (hex.! or "40" - "67" (hex.!.
Write/read of the character code to and from When any value other than the above is input,
the CPU begins with addresses D6 to Do it is impossible to make a normal write/read
starting from DD RAM selection. of character codes to and from the DD RAM.
In the lline display mode (N = H), however, The execution time, when the OSC oscillation
D6 to Do (binary) must be set to one of the frequency is 250 KHz, is 40 J,ls.
values among "00" to "4F" (hex.1.

124
- - - - - - - - - 1 . DOT MATRIX LCD CONTROLLER MSM6222B01GS.

(9) DO RAM and CG RAM data write

R/W RS DBs DBo


Instruction code L H Es Eo

When E7 to EO (binary) codes are written to display shift". The execution time, when the
the DD RAM or CG RAM, the cursor and OSC oscillation frequency is 250 KHz, is
display move as described in" (5) Cursor and 40 ~s.

(10) Busy flag and address counter read

R/W RS DBS DBo


Instruction code H L BF Os 00

The busy flag (BF) is output by this instruction match the DD RAM address or CG RAM
to indicate whether the MSM6222B.Q1 GS is address. The decision of whether it is a DD
engaged in internal operations (BF = "H") or RAM address or CG RAM address is made by
not (BF = "L"). the address previously set.
When BF = "H", no new instruction is ac Since the address counter value when BF = "H"
cepted. It is therefore necessary to verify BF = is sometimes incremented or decremented by 1
"L" before inputting a new instruction. during internal operations, it is not always a
When BF = "L", a correct address counter value correct value.
is output. The address counter value must Execution time is 1 ~s.

(11) DO RAM and CG RAM data read

R/W RS DBs DBo


Instruction code H H Ps Po

Character codes (bit P7 to Po) are read from (Note) Conditions for the reading of correct
the DD RAM, while character patterns (P7 to data:
PO) from the CG RAM. 1 When the DD RAM address set or
Selection of DD RAM or CG RAM is decided CG RAM address set is input
by the address previously set. before inputting this instruction.
After reading those data, the address counter 2 When the cursor/display shift is in
(ADC) is incremented or decremented by 1 put before inputting this instruction
as set by the shift mode mentioned in item in case the character code is read.
"(3) shift mode set". 3 Data after the second reading from
The execution time, when the OSC oscillation RAM when read more than 2 times.
frequency is 250 KHz, is 40 ~s. Correct data is not output in any
other case.

125
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - -

13. Instruction Initialization


(1) When data input/ouput to and from the
CPU is carried out by 8 bits (080 to 087):
CD- Turn on the power (After this, do not change the LCD line
- Wait for 15 ms or more after VDD has number and character font.)
reached 4.5V or more. @ - Check No Busy.
- Set 8B/4B at H by initial reset of instruc- @- Clear the display by setting the display mode.
tion. - Check No Busy.
@- Waitfor4.1 ms or more. (j]) -
Clear the display.
- Set 8B/4B at H by initial reset of instruction. @- Check No Busy.
- Wait for 100 J.lS or more. @- Set the shift mode.
m- Set 8B/4B at H by initial reset of instruction. @- Check No Busy.
- Check the busy flag as No Busy. @_. Initialization completed.
- Set 8B/4B at H. Set LCD line number (N)
and character font (F).

Example of Instruction Code for Steps @, , and (J).

R/W RS DB7 DBS DBo


L L L L H H X X X x
X: Irrespective of H/L

(2) When data input/output to and from the


CPU is carried out by 4 bits (084 to 087):
CD- Turn on the power. @- Check No Busy.
- Wait for 15 ms or more after VDD has @- Clear the display.
reached 4.5V or more. @- Check No Busy.
- Set 8B/4B at H by initial reset of instruc- @- Set the shift mode.
tion. @- Check No Busy.
@- Wait for 4.1 ms or more. @- Initialization completed.
- Set 8B/4B at H by initial reset of instruction. Example of Instruction Code for Steps @,
- Wait for 100 J.lS or more. , and (j).
m- Set 8B/4B at H by initial reset of instruction.
R/W RS DB7 DB6 DBs DB4
- Check the busy flag as No Busy.
- Set 8B/4B at L. Set LCD line number (N) L L L L H H
and character font (F).
@- Check No Busy.
@- Set 8B/4B at L. Set LCD line number (N) Example of Instruction Code for Step .
and character font (F).
- Check No Busy. R/W RS DB7 DB6 DBs DB4
(j])- Clear the display by setting the display L L L L H L
mode.

LCD DRIVE WAVEFORM


Figures 4, 5 and 6 show the LCD driving waveform The relation between duty and frame frequency is
consists of COM signal, SEG signal OF signal and L described in the table below.
(latch pulse waveform) signal, in the duty of 1/8, 1/11
and 1/16 respectively. Duty Frame frequency
1/8 78.1 Hz
1/11 56.8 Hz
1/16 78.1 Hz

(Note) The OSC oscillation frequency is assumed to


be 250 KHz.

126
- - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B-01GS.

S \, 12 1 3 1 4 \ 5161 7 IS 19 1'12

ooM' c,~r
1 =f1~1 ttl!ttlljjlljj"~1ttll.:ttII~1
Vs
1t=1 =====
1-=111=1=1

I ' frame I
I
ooM+f -+I-HII-It--I++11-t-t11-H11-t-11H-1++11++II-tI-I- - -
l

COMS !"rVs
II I I I III I I I I I I I III I I I I
COM91Vl .~:D -11-+-1I~I+-+1I +-+11-+-+11--+-1111-+-1+-+-11+-+11-+-+11-+-11IH-I- - -
V. --'--'L....I......I..................l........l-.I.--'-L-I...~-'--'--'~'----_ __

Vs

COM' 61Vl.~:D
V.
--tl--+-ll I~I+-+-1I +-+11+-+11-+-1111-+-1+-+-1I +-+11+-+1I-HIIr-t--I- - -
Vs

SEG
(Output
"del
jVl.~:D ---1..-1
V.
+-r--I


.
. I------J.-111---r-------
I -----L.-f---rll .I . .
V, '--'"
t 1
-......,/ y L'ghtong
'---------"------"--- waveform

DF --

Figure 4 LCD driving waveform at 1/8 duty.

127
- DOT MATRIX LCD CONTROLLER' MSM6222B01GS ---- - - - -

11 I 1 I2 I 3 I 4 I 5 16 I 7 I8 I 9 I 10 111 I 1 I 2 I

OOM' { :T I I II I II I 1111 II I 1111 III I I II I I

I 1 frame I

OOM' F~1 II II II I I II II II II II II II II II II

WM"{ v'T II 11111111111111111111 II I111

COM12 {V2~~: ~I--'--'IIr-r-"I,. . . .,. .I . - .-I . . - .-I . . . - . I ~I . . . . .- -I. . . . . - I . .II-...-.-II-.--.II~I


V4~~~~~~~~~~~-
..... . . . . . .~II-
.11
V~ - - - - - - - - - - - -

COMI6{V:~; =1=1=11=11=11=11=11=1=11=11=11=11=1=11=11=11==
V~ - - - - - - - - - - - -

Extinguishing
r-.-----y------(.,......--_........-, waveform
~ r ,~ ,-

waveform

OF - I I I I I I I I I I I I I I I I I I I I I I I I I I I I
L -- I I I I I I I I I I I I I I ____ __

Figure 5 LCD driving waveform at 1/11 duty.

128
----II. DOT MATRIX LCD CONTROLLER MSM6222B-01GS.

'DO "I I:' I , I' I ' I ' I , I ' I , J " I" I " I" I " I " I "I j :'
OM'~:V: I:
{
I
11111111111111111111111111111
I
I 1 trame I

OM2 {r ~~
III
I
II 11111111111111111111111111111
I

OOM";~ {
'DO II_ 111111111111111111111] 1111111
II II
:
V~ 1

OF -

L -- I I I I I I I I I I I I I I I I I I

Figure 6 LCD driving waveform at 1/16 duty.

129
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - - -

INPUT/OUTPUT TIMING TO AND


FROM THE CPU AND OUTPUT
TIMING TO MSM5259GS
Table 4, 5 and 6 show input characteristics from the
CPU, output characteristics to the CPU and output
characteristics to MSM5259GS respectively.

Input characteristics from the CPU


0
(VDD = 4.5 -5.5V, Ta = -20 _+75 C)

Range
Item Symbol Unit
MIN TYP MAX
R/W and RS set-up time tB 140 - - nS
E and H pulse width tw 280 - - nS
R/W and RS holding time tA 10 - - nS
E rise time tr - - 25 nS
E fall time tf - - 25 nS
E and L pulse width tL 280 - - nS
E cycle time tc 667 - - nS
DBo to DB, input data set-up time tI 180 - - nS
DBo to DB, input data holding time tH 10 - - nS

Table 4: Input characteristics from the CPU

Output characteristics to the CPU


(VDD=4.5-5.5V, T a =-20-+750C)

Range
Item Symbol Unit
MIN TYP MAX
R/W and RS set-up time tB 140 - - nS
E and H pulse width tw 280 - - nS
R/W and RS holding time tA 10 - - nS
E rise time tr - - 25 nS
E fall time tf - - 25 nS
E and L pulse width tL 280 - - nS
E cycle time tc 667 - - nS
DBo to DB, data output delay time tD - - 220 nS
DBo to DB, data output holding time to 20 - - nS
Table 5: Output characteristics to the CPU

130
- - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B.01GS.
Output characteristics to MSM5259GS
(Voo = 4.S ...... S.SV. Ta = -20 ...... +7S0C)

Range
Item Symbol Unit
MIN TYP MAX

CP and H pulse width tHW1 800 - - nS

CP and L pulse width tLW 800 - - nS

DO set-up time ts 300 - - nS

DO holding time tOH 300 - - nS

L clock set-up time tsu SOO - - nS

L clock holding time tHO 100 - - nS

Land H pulse width tHW2 800 - - nS

OF delay time tM -1000 - 1000 nS

Table 6: Output characteristics to MSMS2S9GS

Figures 7. 8 and 9 show input timing from the CPU. output timing to the CPU and output timing to
MSM5259GS respectively.

Input timing from the CPU

R/W "~VIL VIL ..,V

RS )IoCVIH VIH -'


k.. VIL VIL :; K
IS IW
~
IL
~
~
VIL VIH
VIL VIL

I, If
II
l!&
Inpul
~
DBO - DS7 )jVIH VIH
K VIL dala VIL

tr.

Figure 7

131
DOT MATRIX LCD CONTROLLER MSM6222B01GS .11---------
Output timing to the CPU

7<- VIH VIH


R/W ...l

11 RS )1 VIH
"'" VIL ~:t l(
IW
~
IB

IL

VIL
VIH VIH ~ VIL ~
Ir If

~ r!2-
Oulpul
DBO - DB7 ) cVOH
kYOL dala
VnH
VOL K
IC

Figure 8

Output timing to MSM5259GS

DO

CP

OF

Figure 9

132
- - - - - - - - - 1 . DOT MATRIX LCD CONTROLLER MSM6222B-01GS.

TYPICAL APPLICATION
Interface with LCD and MSM5259GS
Display examples V'Jhen setting the 5 X 7 dots Examples of these bias voltages are shown in Figures
character font lline mode, 5 X 10 dots character 13, 14, 15, and 16. Basically, this can be done by
font 1line mode, and 5 X 7 dots character font dividing the voltage of the resistors as shown in
2line mode through instructions are shown in Figures 4 and 5. If the value of resistor R is made
Figures 10, 11, and 12, respectively. larger to reduce system power consumption, the
When the 5 X 7 dots character font is set in the LCD operating margin decreases and the LCD drive
1line display mode, the COM signals COM9 to To prevent this, a bypass condenser is serially
COM 16 are output for extinguishing. connected to the resistor to lower voltage division
Likewise, when the 5 X 10 dots character font impedance caused by the splitting of resistors
(l-line is set, the COM signals COM12 to COM16 as shown in Figures 15 and 16.
are output for extinguishing. As the values of R, VR, and C vary according to
The display example shows a combination of 16 the LCD size used and VLCD (LCD drive voltage),
characters (32 characters for the 2line display mode) these values have to be determined through actual
and the LCD. When the number of MSM5259GSs experimentation in combination with the LCD.
are increased according to the increase in the number (Example set values:
of characters, it is possible to display a maximum R = 3.3 - 10 Kn, VR = 10 - 30 Kr2, and
of 80 characters. C = 0.0022 J.lF to 0.047 J.lF)
Besides, it is necessary to generate bias voltage Figure 17 shows an application circuit for the
required for LCD operation by splitting resistors MSM6222B01GS and MSM5259GS including a bias
outside the IC to input it to MSM6222B01GS and circuit.
MSM5259GS. The bias voltage has to maintain the following
potential relation:
VDD > VI > V 2 ~ '.13 > V4 > Vs

In the case of 1line 16 characters display (5 x 7 dot/font).

COMl

~
LCD

COM8 -
~ -........
SEGl 01 - - - - - - - 0 4 0
- - - - - - - SEG40
DO I- 011
MSM6222B01 GS MSM5259GS
CP I- CP
OF l LOAD OF 0020 0121

-{ I u
Figure 10

133
DOT MATRIX LCD CONTROLLER MSM6222B-01GS ...- - - - - - - - -

In the case of 1-line 16 characters display (5 x 10 dot/font)

COMl

~
COMll
LCD

-.......,., -...,
SEGl _____________ SEG40 01 --------040

MSM6222B-01 GS DO t - Oll MSM5259GS


CP t- CP
OF L LOAD OF 0020 0121

I I U
I j
Figure 11

In the case of 2-lines 16 characters display (5 x 7 dot/font)

COMl

COM7
~
COM8

COM9

) --
... -

--
COM15

--
COM16 -- --

_________ 040
SEG1~SEG40 01

MSM6222B-01 GS DO I - - - 011 MSM5259GS

CP I - - - CP
OF L LOAD OF 0020 0121

l l
J
u
Figure 12

134
----------11. DOT MATRIX LCD CONTROLLER MSM6222B-01GS.

Bias voltage circuit (1line display mode) Bias voltage circuit (2line display mode)

-
Voo ~----~~--~--
VOO
~ R
Vi
R
V2
MSM6222B-01 GS MSM6222 B01GS ~
V3 B VLCO
V3
V4
R

Vs V4

VR R ~VR
Vs ....

Figure 13 Figure 14

Bias voltage circuit (1line display mode) Bias voltage circuit (2line display mode)

Voo
Voo ~----~~---.--~------

V2
MSM6222B-01GS MSM6222B01 GS
V3

Vs

Figure 15 Figure 16

(VLCO: LCD driving voltage)

135
f!
...
w
en '/ C
Z l>
"C
~
0
-I

~
0'
1C 0 ~
0'
s:
::J :t>
-I
\ ~. JJ
?~
~
~
n

~~ ~~ ~. X
r
n
c
n
COM1 -16 SEG1 -40 01 -040 01 -040 01 -040
0
:2
MSM5259GS MSM5259GS MSM5259GS -I
JJ

~
DO 011 0040 011 0040 011 0040
-.--- CP 0020 r-- CP 0020 r--- CP
0020
0
r
r--
LOAD
OF
0121 tJ r-- LOAD
.--- OF
0121
.--
...-
LOAD
OF
0121
r
m
JJ
VOO VSS V2 V,l VEE Ivoo VSS V2 V) VEE VOO VSS V 2 V) VEE
"T1
cO'
s:
C/)
t:
iil
CP ~
s:
m
~
MSM6222B-01 GS L
OF
\t-- N
N

VOO
\\ N
OJ
6
~

C)
GNO C/)

V,
V2 I
V)
V4
Vs ':"
( I
('
~+.f- HI
C C C C
/1
H~ H~ II
' \ II
1/
"
-vv v v "'I';
A A A A A VA

() () 6
+5V -5V OV
OKI semiconductor
MSM6240GS
DOT MATRIX LCD CONTROLLER

GENERAL DESCRIPTION
The OKI MSM6240GS is a CMOS Si-gate LSI to control large size dot matrix LCD in characters and graphics_

Three kinds of display modes are provided; Semi-graphic mode, Full-graphic mode and Character mode.

FEATURES

Number of characters: 32,40,64 and 80/line Applicable LCD duty: 1/32, 1/48,1/64,1/72,1/80,
Number of lines: 4 X 2, 6 X 2, 8 X 2 and 16 X 2 1/96, ;/108, 1/128, 1/144
Font composition (vertical): 8, 12, 18 and 20; here- Low power CMOS Silicon gate technology
inafter called VP (vertical pitch) Single +5V power supply.
Font composition (horizontal): 5,6, 7, 8, 10, 12, 14
and 16; herei nafter called HP (horizontal pitch)
60 pin plastic flag package (bent lead)

Address: Straight binary


Attribute
1) Display inversion
2) Display blank
3) Cursor display
4) Character blink
5) Cursor blink

PIN CONFIGURATION
(Top View) 60 Lead Flag Package

s: s: s: s: s: s: s: s: s: s: s: r- r- r- r- r-
l>
;; l' :t J' ? ? 1: ? ~ ~ J> 1: ? ~ ~ J>

MAil GNO
Do 0 C5"
01 C5 1
02 5"
OJ 51
04 52
vOO SJ
O~ OEEN
Db XT

07 XT

MCE CL

002 HS o
E02 HS I
001 HSl

m z r- ....
!;)
~ ~
." CD 0
~
." 0 (") C C
0 (") :IJ
~ :;; ~
m
~ iii ~
s: in VI Z ~
-< Z Z ;:j .... Z Z

137
r:!
...w to
(Xl
r o
o
("') o
OlEN OEEN ~O) ED) 0;)2 E02 CP
-i
"o :s:
DATA 8bit 8bit Cursor

C)
l>
-i
JJ
JJ
OO~07 Register Latch PIS Control
l> X
Control LIP :s: r
("')
FRP
o
FRM ("')
REN
BUSY
o
Z
OAEN -i
MCE
Attribute JJ
CHBL
UOEN
Control o
r
r
UOBL m
CSEN JJ

TEST1
:s:
VJ
TEST2 Test
Blink
Counter
:s:
0)
Control N
,J::I.
C
~~
C)
VJ

CL ~ CLR

Address 3 State MAo-MA))
Counter Buffer LAo~LA4

Temporary
XT Address
XT Counter

HS2 HS) HS o CSo CSt So S) S2 S3


- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

ABSOLUTE MAXIMUM RATING

Parameter Symbol Condition Rating Unit


Power supply voltage VOO Ta = 25C -0.3 -6.0 V
Input voltage VIN Ta = 25C -0.3 -VOO V
Storage temperature T stg - -50 -150 c

OPERATING RANGE

Parameter Symbol Condition Rating Unit


Power supply voltage VOO - 4.5 -5.5 V
Operating temperature Top - -20-85 c

INPUT CHARACTERISTICS
10%, Ta = 25C)
(VOO = 5V

Parameter Symbol Condition MIN TYP MAX Unit Applicable terminal


"H" Input voltage VIH - 204 - - V 0 0 - 0 7, REN
OAEN, CHBL, CSEN,
"L" Input voltage VIL - - - 0.8 V
UOEN, UOBL, OlEN
"H" Input voltage VIH - 3.6 - - V HS o - HS 2 , CSo,
"L" Input voltage VIL - - - 1.0 V CSl, So -53, OEEN

"H" Input current IIH - - - -1 J.1A 0 0 - 0 7 , REN, OAEN,


CHBL, CSEN, UOEN, UOBL,
"L" Input current IlL - - - 1 J.1A FS, 01 EN, HSo - HS2,
eso, CSl, So -S3, OEEN

"H" Input current IIH -- - - -1 J.1A


TEST1 - TEST3
"L" Input current IlL - - 500 J.1A
"H" I nput current IIH - - - -1 J.1A CL

"L" Input current IlL - - 50 J.1A

OUTPUT CHARACTER ISTICS


(VOO = 5V 10%, Ta = 25C)

Parameter Symbol Condition MIN TYP MAX Unit Applicable terminal

MAo - MAll,
"H" Output current 10H VOH = 2.8V -500 - - J.1A LAo - LA4, 001,
EOl, 002, E02,
"L" Output current 10L VOL = Oo4V 2.1 - - mA CP, BUSY, FRM,
FRP, MCE, LIP

139
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -

POWER CONSUMPTION
(Ta = 2SoC)

Parameter Symbol VDD Condition MIN TYP MAX Unit


Static current IDDS 5 fosc = o Hz - - SO I1A No load
Operating current IDD 5 fosc = 10 MHz - - 10 mA No load

11
SWITCH ING CHARACTER ISTICS
(VDD = sv 10%)

i1 b
10%

~ 1
/ "--
tr tf

Parameter Symbol Load condition MIN TYP MAX Unit Applicable terminal
Clock pulse tr CL = 150PF - - 100 ns
All output terminals
Rise and fall time tf CL = 150PF - - 100 ns

MAXIMUM OPERATING FREQUENCY


(VDD = sv 10%)

Parameter
Oscillation frequency

140
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

INTERFACE WITH EXTERNAL RAM, ROM

Refresh cycle

(CL BOpF)

Parameter Symbol MIN TYP MAX Unit


Memory address time to the upper part tMAL 500 - - ns
Memory address time to the lower part tMAH 500 - - ns
Memory data delay time of the upper part tMDL - - tMAL70 ns
Memory data delay time of the lower part tMDH - - tMAH70 ns

Note: tMAL and tMAH is calculated by the following formula .


. tMAL = tMAH = 2/fos c X HP/2
tMAL and tMAH become the minimum speed when HP is set at 5 and fosc is 5MHz.

Drawing cycle
DIEN
... O.BV 2.4V I
tA d 2
2.4V 2.4V "l
display
address display address
O.BV O.BV
bus floating

(CL = 150pF)

Parameter Symbol MIN TYP MAX Unit


Drawing address delay time tAd! 20 ns
Display address delay time tA d 2 120 ns

141
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -

THE DISPLAY DATA TO LCD DRIVERS


1) Without ODD/EVEN data processing

J
11
BUSY

MAil
l I
D7 -D o

CP

4.2V
0.8V

4.2V
0.8V

000 address lower data 001 address


lower data

142
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

2) Under ODD/EVEN data processing

BUSY

D,-D u

CP

(CL 80pF)

Parameter Symbol Condition MIN TYP MAX Unit

Shift clock pulse cycle time tfs - 300 - - ns

Shift data delay time tDAH - - - 50 ns

Shift clock pulse cycle time 2 t fs - 400 - - ns

Shift clock data delay time tOED - - - 80 ns

143
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -

PIN DESCRIPTION

Terminal name I/O/Z Function

00 1 (Odd data) Output of serial data for X driver


0 (Even data) Upper screen's data
EDI
00 2 (Odd data) Output of serial data for X driver
0 (Even data) Lower screen's data
ED2
- (Latch pulse)

11 LIP

FRP
0

-
0
Latch pulse for one line
(Frame pulse)
Signal input to Y driver
- (Frame)
FRM 0
Frame inversion signal
(Shift clock pulse)
CP 0 Shift clock pulse for X driver
- "READY" SIGNAL
BUSY 0
L druing suspension of serial transfer
(Display enable)
DIE~J I
Display enable signal; active H

(Chip Enable)
MCE 0 Memory chip enable control signal
(Clear)
a. I
Clear terminal

XT I (X'tal OSC)
- -
XT 0 Crystal oscillation

VOD +5V
GND OV
OEEN I Odd-number even-number data enable; active H

144
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

Terminal
name 1/0/2 Function

MAo (Memory address)


~ 0/2 Memory refresh address output, straight binary address
MAIO MAo -MAll and LAo"" LA4 are at high impedance during OlEN =L
MAll 0/2 Highest order bit of address signal, switching of upper and lower surfaces
MAo - MAll and LAo"" LA4 are at high impedance during OlEN = L

LAo (Line address)


S 0/2 Line scan output for character generation
MAo - MAll and LAo - LA4 are at high impedance during OlEN =L
LA4
Do
S I Display data input
07
So
Selection of number of VP and lines
~ I
Refer to Sec. 10
S3
CSo Selection of number of CSt L L H H
S I characters to be displayed
CSo L H L H
CSt
No. of characters 32 40 64 80

HSo
(Horizontal select)
5
HS 2
I
HP programming

REN I (Reverse enable) Display inversion; active H


DAEN I Data input enable signal; active H
UDEN I Cursor display; active H
CHBL I Character blink; active H
UDBL I Cursor blink; active H
CSEN I Cursor display; active H
TEST1
5
TEST3
I Test pins. On-chip pull-up resistors

145
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -

FUNCTIONAL DESCRIPTION
1. Selection of HP

HP is determined by the logic levels of HS 2 HS 1 and HS o .

HS2 HSI HSO HP

L L L 5 dot

L L H 6
L H L 7
L H H 8
H L L 10
H L H 12
H H L 14
H H H 16

The horizontal space in a font


The horizontal space is determined by HP and
number of horizontal dots/character (hereinafter
called CNH) in the character generator ROM.
HP > CNH Space = HP = CNH

(Example) (Example)
HP = 8 (HS2 HS 1 HS o :011) HP = 5 (HS 2 HSI HSo:OOO)
CNH = 5

Do Do DATA
0 0 0 -0 E 0 0 o C
0 0 o 0
0 0 :1 00 0 0 0 3 F
0 0 1 1 0 o 4
0 0 0 0 0 1 F 0 o 4
0 0 1 1
Not displayed
0 o 4
0 0 1 1 0 0 1 8
o 0 o 0
:3:do, ~ ~--H-P--=r------ 5 x 8 font
....._sp-a-ce-_ _ _C_N_H_ _ ~-l 8 X 8 font
1
HP

HP = CNH No space
*The data Ds - D, are invalid for display.
HP < CNH No space

146
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

The vertical space in a font VP > CNV Space = VP - CNV


The vertical space is determined by VP and VP = CNV No space
vertical dots/character (hereinafter called CNV) VP < CNV No space
in the character ROM. The data whose number of bits are more than
the number of HP are invalid for display.

2. Selection of Number of Characters


Number of characters controlled by MSM6240GS (Note) When HP is set to 10, 12, 14 or 16, display
is determined by the logic levels of CSo and CSl, of characters on the LCD panel is made by
as follows: accessing twice to the character generator
ROM.
CSl L L H H The memory address signal, MAo'" MAIO,
to the LCD panel is addressed as shown in
CSo L H L H the table below.
No. of characters 32 40 64 80

8(4 X 2) lines X 80 characters


This is the case when HP is 8 or less. When HP is
10 '" 16, the display on the LCD panel becomes
8(4 X 2) lines X 40 characters.

000 001 04E 04F


050 051 09E 09F
MAll = L
OAO OAl OEE OEF
OFO OFl 13E 13F
000 001 04E 04F
050 051 09E 09F
MAll = H
OAO OAl OEE OEF
OFO OFl .. 13E 13F

OFO means following data.


MA
10 9 8 7 6 5 4 3 2 1 0
L L L H H H H L L L L

147
- DOT MATRIX LCD CONTROLLER . MSM6240GS------------

3. Selection of Number of HP and lines

No. of Number of characters/line


S3 S2 SI So VP Duty
lines HPis10-16 HP is 8 or less
L L L L 8 4 80 64 40 32 80 64 40 32 1/32
L L L H 8 6 80 64 40 32 80 64 40 32 1/48
L L H L 8 8 80 64 40 32 80 64 40 32 1/64
L L H H 8 12 80 64 40 32 80 64 40 32 1/96
H H H H 8 16 (80) 64 40 32 80 64 40 32 1/128
L H L L 12 4 80 64 40 32 80 64 40 32 1/48
L H H L 12 8 80 64 40 32 80 64 40 32 1/96
H L L L 18 4 80 64 40 32 80 64 40 32 1/72
H L L H 18 6 80 64 40 32 80 64 40 32 1/108
H L H L 18 8 80 64 40 32 80 64 40 32 1/144
H H L L 20 4 80 64 40 32 80 64 40 32 1/80

*Number of lines on above table is half of the actual number of lines on the LCD panel.
When all of S3 - So are set at high level (which means HP is 16 and number of characters/line is 80), the display on
the LCD panel becomes as shown below because the capacity of the display RAM overflows.
HP = 8

{ Number of lines = 12
VP = 16
Number of characters/line = 80

4. Attribute Function
This function is determined by the data of the
external attribute RAM. The attribute function
per font is available.

Character Display, Blink


DAEN CHBL Display
L L Blink
L H Blink
H L Display
H H Blink

Cursor Display and Blink


UDBL CSEN UDEN Cursor Display
L L L None
L L H None
L H L None
L H H Cursor display
H L L "lone
H L H None
H H L Cursor blink
H H H Cursor blink*

*The character and cursor blink alternately.

148
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

Cursor display position


Cursor is displayed in the bottom line of the
font. The number of horizontal dots/font is
same as that of HP.
(Example)
8 X 8 font 8 X 12 font

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 - Cursor

Blink
The blink cycle is 640 ms (FRP = 50 Hz) and is
cynchronized to FRM signal.

FRM

~ ________ ________r--
~"\

640 ms

Display inversion

Inversion

REN = L REN = H

The display of character and cursor is inverttld.

149
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -

5. Display RAM (2K bytes)


The MSM6240GS is applicable to both character
mode and graphic mode, which is only determined
by system configuration, not by software.

When using Display RAM in the character mode

< System configuration>

11
CHARACTER GENERATOR R:l~1

Out

Upper Panel

-- DISPLAY RAM (4K byte)

Lower Panel

",-_ _~_ _-,,7

p"-----
The character code is programmed in the Display The MSM6240GS is capable of controlling 4,096
RAM in 8-bit configuration. The data of Display characters maximum, however, this capacity is
RAM is converted to the data necessary to display affected, as is shown on the Sec. 13, by the LCD
a character on the LCD, and is input to Do -- 0 7 , drivers speed.
display data input, of the MSM6240GS.

150
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

Relationship between LAo -- LA4 and VP


LAo -- LA4 are valid for octal, duodecimal, octdicimal and vigesimal signals.

VP = 8 VP = 12

LA2 LAl LAo LA3 LA2 LAl LAo

r' L L L rt L L L L

L L H L L L H

L H L L L H L

L H H L L H H

H L L L H L L

H L H L H L H
H H L L H H L

H H H L H H H
H L L L
H L L H
H L H L
'- H L H H

VP = 18 VP = 20

LA4 LA3 LA2 LAl LAo LA4 LA3 LA2 LAl LAo

r+ L L L L L r" L L L L L

L L L L H L L L L H
L L L H L L L L H L
L L L H H L L L H H

L L H L L L L H L L
L L H L H L L H L H

L L H H L L L H H L
L L H H H L L H H H

L H L L L L H L L L
L H L L H L H L L H
L H L H L L H L H L
L H L H H L H L H H
L H H L L L H H L L
L H H L H L H H L H

L H H H L L H H H L
L H H H H L H H H H
'- H L L L L H L L L L
H L L L H
H L L H L
'-- H L L H H

151
DOT MATRIX LCD CONTROLLER MSM6240GS . - - - - - - - - - - -

Limitation of No. of characters and No. of lines


The No. of characters and the No. of lines are
subject to limitation according to the RAM
capacity.

When HP is set at 8 or less

No. No. of characters/line No. of lines Display RAM area

11 1
2
3
80
64
40
16
16
16
000 -4FF (H)
000 -3FF (H)
000 - 27F (H)
4 32 16 000 - 1 FF (H)

When HPissetat 10-16

No. No. of characters/line No. of lines Display RAM area

5 80 12 000 -77F (H)


6 64 16 000 -7FF (HI
7 40 16 000 -4FF (H)
8 32 16 000 -3FF (H)

(Note) Number of lines on above table is half of the actual number of lines on the LCD panel.

(Example) RAM area 000 -3BF

Memory address MAll' MAIO I MA9 I MAs' MA, I MA6 i MAs ,MA4 'MA3 : MA2 ,MAl 'MAo
Start address L ,
I
L I L I L I L :, L I L ,
I
L I L I L ,
I
L I L
End address L ,
I
L
I
H ,
I
H
I
H , L ,
I
H
I
H
I
H
I
H
I
H
I
H
Start address H ,
I
I

,
I I
I
I
L
I
, L
I
L
I
,
I
L
I
,
I
L
, I
L
I

,
I
L
I

,
I
L
L L L I
,
I
,, I
, I
,
End address H I' L ,I H
I
H H
: L
I
I
H
I
I H
I
H
i
I
H
I
H ,
I
H

152
DOT MATRIX LCD CONTROLLER MSM6240GS.

Set HP at 8 or less I
No.1 In the case of 80 characters/line (Number of lines: 161ines max.)

000 001 002 003 04E 04F


050 051 052 053 09E 09F
OAO OA1 OA2 OA3 OEE OEF
OFO OF1 OF2 OF3 13E 13F
140 141 142 143 18E 18F
190 191 192 193 1DE 10F
1EO 1E1 1E2 1E3 22E 22F
230 231 232 233 27E 27F
280 281 282 283 2CE 2CF
200 201 202 203 31E 31F
320 321 322 323 36E 36F
370 371 372 373 3BE 3BF
3CO 3C1 3C2 3C3 40E 40F
410 411 412 413 45E 45F
400 401 402 403 4AE 4AF
4BO 4B1 4B2 4B3 4FE 4FE

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.

No.2 In the case of 64 characters/line (Number of lines: 16 lines max.)

000 001 002 003 03E 03F


040 041 042 043 07E 07F
080 081 082 083 OBE OBF
OCO OC1 OC2 OC3 OFE OFF
100 101 102 103 13E 13F
140 141 142 143 17E 17F
180 181 182 183 1BE 1BF
1CO 1C1 1C2 1C3 1FE 1FF
200 201 202 203 23E 23F
240 241 242 243 27E 27F
280 281 282 283 2BE 2BF
2CO 2C1 2C2 2C3 2FE 2FF
300 301 302 303 33E 33F
340 341 342 343 37E 37F
380 381 382 383 3BE 3BF
3CO 3C1 3C2 3C3 3FE 3FF

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.

153
DOT MATRIX LCD CONTROLLER MSM6240GS . - - - - - - - - - -

No.3 In the case of 40 characters/line (Number of lines: 16 lines max.)

000 001 002 003 026 027


028 029 02A 02B 04E 04F
050 051 052 053 076 077
078 079 07A 07B 09E 09F
OAO OAl OA2 OA3 OC6 OC7
OC8 OC9 OCA OCB OEE OEF
OFO OFl OF2 OF3 116 117
118 119 llA llV 13E 13F
140 141 142 143 166 167
168 169 16A 16B 18E 18F
190 191 192 193 lB6 lB7
lB8 lB9 lBA lBB lDE lDF
lEO lEl lE2 lE3 206 207
208 209 20A 20B 22E 22F
230 231 232 233 256 257
258 259 25A 25B 27E 27F

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panet. Whether it be the upper or lower will be determined
by the H/L condition of MAll.

No.4 In the case of 32 characters/line (Number of lines: 16 lines max.)

000 001 002 003 OlE 01F


020 021 022 023 03E 03F
040 041 042 043 05E 05F
060 061 062 063 07E 07F
080 081 082 083 09E 09F
OAO OAl OA2 OA3 OBE OBF
OCO OCl OC2 OC3 ODE ODF
OEO OEl OE2 OE3 OFE OFF
100 101 102 103 llE l1F
120 121 122 123 13E 13F
140 141 142 143 15E 15F
160 161 162 163 17E 17F
180 181 182 183 19E 19F
lAO lAl lA2 lA3 lBE lBF
lCO lCl lC2 lC3 lDE lDF
lEO 1 El lE2 lE3 lFE lFF

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll'

154
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

ISetHPat10- 1s l
NO.5 In the case of 80 characters/line (Number of lines: 12 lines max.)

000 001 002 003 09E 09F


OAO OA1 OA2 OA3 13E 13F
140 141 142 143 1DE 1DF
1EO 1 E1 1E2 1E3 27E 27F
280 281 282 283 31E 31F
320 321 322 323 3BE 3BF
3CO 3C1 3C2 3C3 45E 45F
460 461 462 463 4FE 4FF
500 501 502 503 59E 59F
5AO 5A1 5A2 5A3 63E 63F
640 641 642 643 6DE 6DF
6EO 6E1 6E2 6E3 77E 77F

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.

No.6 In the case of 64 characters/line (Number of lines: 161ines max.)

000 001 002 003 07E 07F


080 081 082 083 OFE OFF
100 101 102 103 17E 17F
180 181 182 183 1FE 1FF
200 201 202 203 27E 27F
280 281 282 283 2FE 2FF
300 301 302 303 37E 37F
380 381 382 383 3FE 3FF
400 401 402 403 47E 47F
480 481 482 483 4FE 4FF
500 501 502 503 57E 57F
580 581 582 583 5FE 5FF
600 601 602 603 67E 67F
680 681 682 683 6FE 6FF
700 701 702 703 77E 77F
780 781 782 783 7FE 7FF

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll'

155
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -

No.7 In the case of 40 characters/line (Number of lines: 161ines max.)

000 001 002 003 04E 04F


050 051 052 053 09E 09F
OAO OAl OA2 OA3 OEE OEF
OFO OF1 OF2 OF3 13E 13F
140 141 142 143 18E 18F
190 191 192 193 1DE lDF
lEO lE1 lE2 lE3 22E 22F
230 231 232 233 27E 27F
280 281 282 283 2CE 2CF
2DO 2Dl 2D2 2D3 31E 31F
320 321 322 323 36E 36F
370 371 372 373 3BE 3BF
3CO 3Cl 3C2 3C3 40E 40F
410 411 412 413 45E 45F
460 461 462 463 4AE 4AF
4BO 4Bl 4B2 4B3 4FE 4FF

The table above shows the memoray address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.

No.8 In the case of 32 characters/line (Number of lines: 16 lines max.)

000 001 002 003 03E 03F


040 041 042 043 07E 07F
080 081 082 083 OBE OBF
OCO OCl OC2 OC3 OFE OFF
100 101 102 103 13E 13F
140 141 142 143 17E 17F
180 181 182 183 lBE lBF
lCO lCl lC2 1C3 lFE lFF
200 201 202 203 23E 23F
240 241 242 243 27E 27F
280 281 282 283 2BE 2BF
2CO 2Cl 2C2 2C3 2FE 2FF
300 301 302 303 33E 33F
340 341 342 343 37E 37F
380 381 382 383 3BE 3BF
3CO 3Cl 3C2 3C3 3FE 3FF

The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/ L condition of MA 11.

156
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER' MSM6240GS.

When using Display RAM in the graph mode

I r~------Y
Out

DISPLAY
RAM

'" ,/

11 11 LA o -LA 4

~ MAo-MAII

(Note) The cursor display should not be used by setting CSEN at L.

(Example)HP = 8, VP = 8,64 characters/line, 16 lines

MSB Address configuration for Display RAM LSB

IMAIII MA91 MAR I MA7 I MAo I LAl I LAI I LAo I MAs I MA41 MA31 MAl (MAl I MAo I
0000
0040
0080
003F
007F
OOBF T
Upper
surface
8K byte
,LJ ~L

, ...

t
,~

1FCO 1FFF
2000 203F
2040 207F
2080 20BF

Lower
surface
8K byte
,'- ~'-

157
DOT MATRIX LCD CONTROLLER MSM6240GS .---.-------~

6. Dien Signal processing is proceeded.


The purpose of ODD/EVEN number data processing
Before writing the data into DISPLAY RAM or is to reduce the shift pulse "CP" speed by half.
ATTRIBUTE RAM, OlEN signal should be set at L. When MSM6240 is applied to wide LCD's control,
the speed of shift pulse becomes high and it exceeds
7. Memory Chip Enable Signal (MCE) the maximum clock frequency of the LCD drivers,
Normally this signal is set at L. This signal becomes so, to reduce the shift pulse speed is required.
H when BUSY signal or 0 I EN signal become L, When OEEN is set at L, ODD/EVEN number data
which reduces the current consumption of the processing is not proceeded.
OEEN may set at L only when HP is set at 8 or less.

11
external RAM by half.
In this case, the data is sent to 00 1 (upper part)
8. ODD/EVEN Number Data Processing and 00 2 (lower part).

When OEEN is set at H, 'ODD/EVEN number data

CP

9. Frame Pulse, Frame, Latch


Time chart

1st line stop 2nd line stop 3rd line stop lst line stop
I I I I I I I I I I
Memory address =:JJ..J...1.ll-:::::a:::::::x:t::.-'~.:.~::: x:crr.j~=x:x:xxxx: :'.::Y:C:J.
LIP ..Il ~ If 'l--fr" !l-
FRP id
I ,
~I I rf---1 :I L
FRM
: : : I If ~
I I I I I
I I I ,

X driver
j ~ 1st I,"ne X 2nd I,"ne v..---,f-v
~------(l-~-"!'!!''':'::'':;=-----1'I'-....!.!.~~---f'---JJ-A N th line
I
pilline
Y driver _y....:.l_ _ _ _---J1 I : If i
~IY-2~-------------J: ~/r'-------~I-- I
I I
_'y~N~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___{fl~ ~

_y~I~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~%~------~r---

The proper FRP frequency is 50 to 70 Hz.


f osc must be calculated so that it might match
with FRP frequency.

158
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

10. X'TAL Oscillation

XT

et------f s
XT
R

Power ON reset

The frequency of the crystal is calculated by follow- HPisl0-16


ing formula. fosc = (Number of characters X 2 + 16)
HP is 8 or less X 8 X l/duty X FRP X 2
f osc = (Number of characters + 8) X HP
X l/duty X FRP X 2

11. X'T AL Oscillation Frequency Table

HP '" 8, FRP + 50 -70 Hz

No. of
1\ characters 32 40 64 80

"
Duty
1/128 4.1-5.7 4.9-6.9 7.4 -10.3 9.0 -12.6
1/96 3.1 -4.3 3.7 -5.2 5.5- 7.7 6.8- 9.5
1/64 2.0-2.9 2.5 -3.5 3.7- 5.18 4.5- 6.3
1/48 1.5-2.1 1.8 -2.5 2.8- 3.9 3.4 - 4.8

HP = 7, FRP = 507'"' 70 Hz

~Duty
No. of
characters 32 40 64 80

1/128
1/96
"" 3.6-5.0
2.7 -3.8
4.3 -6.0
3.2 -4.5
6.5 -9.1
4.8-6.7
7.9 -11.1
5.9- 8.3
1/64 1.7-2.5 2.2 -3.1 3.2-4.5 3.9- 5.5
1/48 1.3 -1.8 1.6-2.2 2.5-3.5 3.0- 4.2

159
DOT MATRIX LCD CONTROLLER MSM6240GS . - - - - - - - - - - -

HP = 6. FRP = 50 ...... 70 Hz

1\ Duty
No. of
characters 32 40 64 80

1/128
1/96
'" 3.1 ...... 4.3
2.3 ...... 3.2
3.7 ...... 5.2
2.8 ...... 3.9
5.6 -7.8
4.1-5.7
6.8 ...... 9.5
5.1 ...... 7.1
1/64 1.5 ...... 2.1 1.9 ...... 2.7 2.8 ...... 3.9 3.4 ...... 4.8

11 1/48 1.1 ...... 1.5 1.4 ...... 2.0 2.1 -2.9 2.6 ...... 3.6

HP = 5. FRP = 50 ...... 70 Hz

~
No. of
characters 32 40 64 80
Duty '\
1/128 2.6 ...... 3.6 3.1 ...... 4.3 4.6 -6.4 5.6 ...... 7.8
1/96 1.9 ...... 2.7 2.3 -3.2 3.4 ...... 4.8 4.3 ...... 6.0
1/64 1.3-1.8 1.6 ...... 2.2 2.3 -3.2 2.8 ...... 3.9
1/48 0.9 ...... 1.3 1.1 ...... 1.5 1.8 ...... 2.5 2.1 ...... 2.9

HP = 10 ...... 16. FRP = 50 ...... 70 Hz

1\ Duty
No. of
characters
'\
32 40 64 80

1/128 8.2 ...... 11.5 9.8 ...... 13.7 14.7 ...... 20.6 18.0 -25.2
1/96 6.1 ...... 8.5 7.4 ...... 10.4 11.1 - 15.5 13.5 ...... 18.9
1/64 4.1 ...... 5.7 4.9 ...... 6.9 7.4 - "10.3 9.0 ...... 12.6
1/48 3.1 ...... 4.3 3.7 ...... 5.2 5.5 - 7.7 6.8 ...... 9.5

The value on above tables are affected by the For example. the fosc is limited as follows when
maximum frequency of LCD driver's shift clock MSM5260GS. whose maximum frequency of shift
input and an maximum frequency of fos c . pulse is 3.3 MHz. is connected to MSM6240GS.
The relation between fosc and shift clock is as When ODD/EVEN data processing is proceeded
follows. fosc ~ 10 MHz
When ODD/EVEN data processing is proceeded When ODD/EVEN data processing is not pro-
CP = fosc/4 ceeded
When ODD/EVEN data processing is not pro- fosc ~ 6.6 MHz
ceeded
CP = fosc/2

160
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.

TYPICAL SYSTEM CONFIGURATION

EVEN SEG DRV


~____~~.r----------------_EDI

ODD SEG DRV L-__~~~--_______________ ODI

LIP
FRP
L...--4-___ FRM

ODD SEG DRV


a--------------4----0D2

EVEN SEG DRV


~____~~r-------------+----ED2

L=============~~===ti~======jt~========~---cp

161
OKI semiconductor
MSM6255GS
DOT MATRIX LCD CONTROLLER

GENERAL DESCRIPTION

III The OKI MSM6255GS is a CMOS Si-gate LSI designed for use in controlling large size of DOT MATRIX LCD panels
in characters and graphics,

FEATURES
Display control capacity Scrolling and paging
16
Graphic mode: 512,000 dots (2 bytes) Display system: AC inversion at each frame
. Memory address MA?6"'" MA1S Data output (upper and lower display outputs)
- Character mode: 65,536 characters (2 bytes) 4-bit parallel output, 2-bit parallel output
Display address MAo"'" MA15 1-bit serial output
Direct interface with 8085 or Z80 CPU Crystal oscillation
Duty: 1/2 to 1/256 selectable Low C-MOS Silicon gate process
Attribute Single +5V power supply
Screen clear 80-pin flat package
- Cursor ON/OFF/blink

PIN CONFIGURATION

i' ,f' <t


ex: ex: ~ ~ 0
ex: g ~
~. 0
ex: fi fl co
0
co
0
co
0
co
0
co
0
co
0
Iii
0
co
0 I~ I~ I~ I~

.."' ~ :ll ~ :;; :ll :g :l.

Xl ADF
Xl
VSS

TEST1
0 DISN

BUSV

CHq,
TESl2 UD"

DiV UD,

MAB UD,

MAI4 UDo

MAIJ VDD

MAil LDJ

MAil LD,

MAIO LD,

MA.,

MA.

MA,
LOu

FRMB

CLP

MA., CEI'>

- N M . '" '" " <Xl en ~


= ~ !:! :! ~ ~ ::: ~ 2? ~ N ~ ::l ~

.;; ; .;. .t' <t <i <t <t <t <t <t <t J
.; ,f .i .;; ; .; ,f' <t <i "- "-
ex: :::;
::; ::; ::; ::; ::;::;

162
OJ
r-
o
n
RD - - - - - - - - ,
WR - - - - - - - ,
"5>c
G')
CS ::0
l>
DBo S
S
DB,
Instruction
_r1'!l!s!.eL _____ _

~
.,-
R/W control

MAo
:;;e
.;::J
~
MA IS
1-0

RES - - c
ADF
o-i
S
l>
-i
::0
II lAo X
S r-
~-------DIEN
A I5
n
c
:;~::;s ==> Rto RA.l
n
o
2-bit parallel 2:
output -i
-4-bi;-p-;;a~I---~UDO-UD3 ::0
~U}I?':!.t_______ LDo-LD.l or-
8 bit parallel/ -CLP
senal r-
TImIng generator -CEq, m
circuit for CH ::0
PS and Load
II jRpO
XT R~
S
_ FRP en
DIV
J.
:I:
>- ~
Vl..J ~
U :J - FRMB 0)
(I]
N
U1
U1
G')
... en
al
W
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating value Unit

Supply voltage VDD Ta = 25C -0.3 -6 V

Input voltage VIN Ta = 25C -0.3 -VDD V

Storage temperature T stg - -50-150 c

11 OPERATING RANGE

Parameter Symbol Condition Range Unit

Supply voltage VDD - 4.5 -5.5 V

Operating temperature - -20 -85 Vc


Top
Operating frequency fosc VDD = 5V 10% 0-11 MHz

INPUT CHARACTERISTICS
(VDD = 5V 5%, Ta = -20 - 85C)

Parameter Symbol MIN TYP MAX Unit Applicable terminal

"H" input voltage VIH 2.4 - - V DBo - DB 7 , CS, RD, WR, Ao - AIS,
"L" input voltage - - V DIEN,ADF, RDo -RD 7
VIL 0.7
"H" input voltage VIH 4.5 - - V RES,DIV, XT
"L" input voltage VIL - - 1.0 V
"H" input voltage IIH - - 1 pA DBo"" DB 7 , CS, RD, WR Ao "" AIS.
"L" input voltage - - -1 DIEN. ADF RDo - RD 7 RES. DIV
IlL pA
"H" input voltage IIH - - 250 pA TEST1, TEST2
"L" input voltage IlL - - -1 pA

OUTPUT CHARACTER ISTICS


(VDD = 5V 5%, Ta = -20 - 85C)

Parameter Symbol Condition MIN TYP MAX Unit Applicable terminal

"H" output current IOH VOH = 2.8V -500 pA LDo - LDJ


- - UDo - UDJ
MAo -MAIs
"L" output-current IOL VOL = OAV 204 mA RAo - RAJ
CHrp. CErp. LIP, FRP
- -
FRMB. BUSY, CLP
DBo - DB 7

164
- - - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6255GS-

CURRENT CONSUMPTION
(Voo = 5V 5%, Ta = -20 - 85C)

Parameter Symbol VOO Condition MIN TYP MAX Unit


Static current IOOS 5 fosc = 0 Hz, No load - - 50 J1A
Dynamic current 100 5 fosc = 10 MHz, No load - - 15 mA

Note: TESTl and TEST2 are open, and other inputs are either VOO or GNO.

SWITCHING CHARACTERISTICS

0.8 VOO I ~ 0.8 VOO

/ 1\ [0.2 VOO

- ,I-

Parameters Symbol Load condition MIN TYP MAX Unit Applicable terminals
Rising time tr 60 pF - - 100 ns
All output terminals
Falling time tf 60 pF , - - 100 ns

MAXIMUM OPERATING FREQUENCY


(VOO = 5V 5%, Ta = -20 - 85(;)

Parameter Symbol Condition MIN TYP MAX Unit Notes


Oscillating frequency fosc DIV = "L" 11 - - MHz Crystal oscillator
Basic clock frequency fs OIV = "H" 5.5 - - MHz External clock

165
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -

LCDC CONTROL SIGNAL TIMING CHARACTERISTICS


5%, T a = -20'" 85C)
(CL = 30pF, VDD = 5V

Parameter Symbol MIN TYP MAX Unit


Clock cycle time tcp 180 - - ns
Clock "H" level pulse width PWH 80 - - ns
Clock "L" level pulse width PWL 80 - - ns

- -

11
Clock rising/falling time tcr/ tcf 20 ns
Character clock delay time tCH - - 200 ns
Memory address clock delay time tMA - - 100 ns
Memory address disable delay time tAD1 - - 40 ns
Memory address enable delay time tAD2 - - 40 ns
CPU address delay time tAD3 - - 100 ns
Refresh address delay time tAD4 - - 100 ns
Reset "H" level pulse width tRES 1 - - /.IS

tcp

XT
External
clock

CHcp

MAO-MAlS Lower Side Address

MAo-MAlS Floating
RAo-RA3

tAD2

DIEN \~ }

MAo-MAlS Refresh Address


~t- CPU Address
~~ It"
Refresh Address

- tAD3 I - - - tAD4 I---

l-tREs~
166
- - - - - - - - - - - . - DOT MATRIX LCD CONTROLLER MSM6255GS-

BUS TIMING CHARACTERISTICS


(Cl = 50pF, VDD = 5V 5%, Ta = -20 - 85C)

Parameter Symbol MIN TYP MAX Unit


Ao, CS Set up time tcs 100 - - ns
RD, WR Pulse width tcw 300 - - ns
Address hold time tAH 40 - - ns
Data set-up time' tDS 200 - - ns
Data hold time tDH 40 - - ns
Output disable time tOH 0 - 40 ns
Access time tACC - - 200 ns

AH
r----

Ao, CS
=x ~ tew
:~
/
WR,RD \.- ,k'
tDH

DBO"-'DB7
(WRITE) ~: :K
DBo"'DB7
(READ)
7 f-

~ Ie-
VALID
:>-
tACC tOH

167
- DOT MATRIX LCD CONTROLLER MSM6255GS - - - - - - - - - - - - -

LCD DRIVER INTERFACE TIMING CHARACTERISTICS


(CL = 30pF, VDD = 5V 5%, Ta = -20 "'+85C)

Parameter Symbol MIN TYP MAX Unit


Data delay time tDA - - 100 ns
1 Character cycle time tCHI/> 730 - - ns
Latch signal delay time tQ - - 200 ns

11 - -
Latch signal "H" time tLiP 1.46 ns
Chip enable clock delay time tCE - - 200 ns
Chip enable clock "H" time tCEI/> 730 - - ns
Ready signal delay time tB - - 200 ns
Ready signal "H" time tBUSY 5.11 - - p.s
Frame signal delay time tFRP 2tCHI/> - 2tCHI/> +200 ns
Alternating frame signal delay time tFR - - 200 ns

CLP

UDO"'UD3-------+~
LD o"'LD 3 ______-+-J

CHI/>

LIP

CEI/>

BUSY

tB tB

LIP

FRP

FRMB

tFR tFR

168
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6255GS.

TIMING FOR FETCHING PATTERN DATA

Parameter Symbol MIN TVP MAX Unit


Upper side data set-up time tUDS 120 - - ns
Upper side data hold time tUDH 40 - - ns
Lower side data set-up time tLDS 120 - - ns
Lower side data hold time tLDH 40 - - ns

CHc/>

RDO-RD7

IUDS IUDH ILDS

169
DOT MATRIX LCD CONTROLLER MSM6255GS --.- - - - - - - - -

PIN DESCRIPTION

Terminal No. Terminal name I/O/Z Function


1 "'6 MAo
-
S O/Z Address output for displaying RAM.
71 '" 80 MA lS
7 Ao
S ) I Memory address input terminals.

11 22
23
24
25
A lS
FRP
LIP
CE>
0
0
0
Frame signal .... Synchronization of display
Display data latch signal
Chip enable clock for LCD segment driver.
26 CLP a Display data shift clock
27 FRMB 0- AC signal
28 LDo
S
31
S 0- Display data parallel output for lower side.
LD3
32 VDD Supply voltage
33 UDo
) S a Display data parallel output, Upper display 4bit output
(001, ED1, 002 and ED2 outputs)
36 UD3
37 CH> 0" Character clock

- Ready state signal. This signal is used while serial


38 Busy a transmission stops.
Display enable signal. When this signal is H, display is
39 OlEN I
enabled.
Address floating input. When this signal is L, MAo'"
40 ADF I MAlS RAo"'RA3 are high impedance. Whereas, it is H,
Ao""AlS or a refresh address is output to MAo"'MAlS'
41 CS I Chip select.
42 RD I Read ...... Reading data is valid when RD =L
43 WR I Write ...... Data is written when WR =H
44 RES I Reset .. ',' .. Resets each counter.

45 DBo
S
52
S
DB,
I/O/Z 8bit data bus ... Common terminal for three state I/O.

53 ROo
ROM/RAM data input ... Dot pattern data for the
S S I
character generator
60 RD,
61 RAo
Raster address output.
S
64
S O/Z
*This output is not used in the graphic mode.
RA3
65 XT I
X'tal osc .... When an external clock is used by setting
- 01 V to "L", feeds it to XT.
66 XT a
67 Vss Ground pin.
"H": EXT clock.
70 DIV I
"L": Selfexcided oscillation

170
-----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.

FUNCTIONAL DESCRIPTION

1. LCDC Internal Registers


The internal registers include one instruction register (I RI and nine data registers. (See Table 11.

Table 1 MSM6255GS internal registers

Instruction
Data bit
CS Ao register Register Register name READ WRITE
3 2 1 0 7 6 5 4 3 2 1 0
H X X X X X Invalid - -
L H X X X X IR Instruction register 0 0 X X X X
Mode control
L L L L L L MOR
register
X 0 X

Character pitch
L L L L L H PR
register
0 0 X

Horizontal character
L L L L H L HNR
number register
0 0 X

L L L L H H DVR Duty number register X 0


L L L H L L CPR Cursor form register 0 0
Start address !lower)
L L L H L H SLR
register 0 0
Start address (upper)
L L L H H L SUR
register 0 0
Cursor address
L L L H H H CLR 0 0
(lower) register
Cursor address
L L H L L L CUR 0 0
(upper) register

Note: "L" is read if the data of the registers marked X is read.

Instruction register
The instruction register is a register for specifying the address of the data register which is accessed.
This register is cleared when ~ input is "L".

171
DOT MATRIX LCD CONTROLLER MSM6255GS .
.------------

Mode control register

The mode control register is specified by writing "OOH" in the instruction register.

Register Ao 0, D6jD 5jD41 D3jD2jDtj Do


Instruction register H L L IL IL I L IL IL I L
IJ Mode control register L L MODE DATA

06 05 04 03 O2 0 1 Do Output system
L L l-bit serial
H L 2-bit parallel
L Character display
X H
4-bit parallel
X H
H/L H/L H/L H/L
L L l-bit serial
H L 2-bit parallel
H Graphics
X H
4-bit parallel
X H

.JL
.=
]!
e
--
Qi
~~
Q)

E
.;; .. u. ..
u. :0 u.
>u. <C <CQ)

...0. c.",
:c ......
W
.JL 00 0 ..!!!O
"'--
.= :;2
iii UO u
~
:J
0.--
.~ 2
00 N
:C:C
~..:.
0
0
~
L.,..-l

LH' Display ON
L: Display OFF

05 04
L L Cursor OFF
L H Cursor OFF
H L Cursor ON
H H Cursor blink

H: 16 frames
Half of blinking cycle
L: 32 f rames )

172
-----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.

- Character pitch register

Register Ao 07 I 06 I Os I 04 03 02 1 01 I 00
Instruction register H L I L I L I L L L T L 1 H

Character pitch register L (V p -11 L (Hp -11

Hp represents the number of bits to be displayed


among one byte display data sent from RAM.
The value of Hp is the following five types. 02 01 00
Hp
4 L H H
5 H L L
6 H L H
7 H H L
8 H H H

- Horizontal character number register

Ao 07 06 I 05 I 04 I 03 I 02 I 01 I 00
Instruction register H L L I L I L I L I L I H I L
Character number register L L (HN -1)

Assuming the total horizontal dot number of the display is 17H.

where HN = 2 -128.

The maximum value of 17H = 8 x 128 = 128 bytes = 1.024 dots.

- Duty number register

Register Ao 07
I 06
I 05 I 04 I 03 I 02 -, 01 I 00
I nstruction register H L I L I L I L I L I L I H I H
Time division register L (NX - 11
Nx = 2 -256

- Cursor form register

Register Ao 07
I 06 I 05 I 04 03 I O2 I 01 I 00
Instruction register H L I L I L I L L
I H
1 L
1 L
Cursor position register L (Cpu -11 (Cpd - 11

The cursor is displayed on the lines from Cpu to The cursor is not displayed in graphic mode.
Cpd in the character display mode. The length of The relation between the cursor and Vp is as
the cursor in the horizontal direction is equal to follows.
the character pitch in the horizontal direction.
Hp.

173
- DOT MATRIX LCD CONTROLLER MSM6255GS - . - - - - - - - - - - -

Font configuration of Hp = 7 and Vp = 8

o O--t---t--+--+--+--+-+- o

2 i-- -- 2 --t-~r--t--r--t-~r--t-- 2 --~-H~~~~H-4H~~

3 3--r--t-;--+--r-~~- 3
4 4---+-+--+-+--+-+--+-- 4 ---fH~R-TH-+R-~~~~--

5 5---r--tr-~-+-+--+-+-- 5--~~~B-~~~H-eT-
6 6-~-+R-~-A~~~~~- 6---r--t--+--+-+--+-t--
7 7---tt:Ji-fH--tili-fH--fH1--fH--fR~ 7---+--1----f---1----f---1---f---

Cpu = 8, Cpd = 8 Cpu = 7, Cpd =8 Cpu = 2, Cpd = '6

Note: (1) Setting of Cpu! Cpd > Vp is not available.


(2) The cursor signal and pattern data are displayed subject to EX-OR.

Start address (lower) register

Register Ao 07 I 0 I 05 I 0 I 0 3 I Dz I 0 1 I Do
6 4
Instruction register H L IL I L IL I L I H I L I H
Display start address register (lower byte) L Start address (lower)

- Start address (upper) register

Register Ao 07 I 0 6 I 05 I 0 4 I 0 3 I Oz. I 0 I Do 1

Instruction register H L IL I L IL I L I H IH I L
Display start address register (upper byte) L Start address (upper)

The display start address shows an address of The start address is composed of upper and
the RAM which stores data displayed at the left lower 8 bits (16 bits in total I.
end and the most upper position.

- Cursor address (lower! register

Register Ao 07 I 0 6 I 05 I 0 4 I 0 3 I Dz I 0 1 I Do
Instruction register H L I L I L I L IL H I I H I H
Cursor address register (lower byte) L Cursor address (lower!

- Cursor address (upper) register

Register Ao 07 I 0 6 I 05 I 0 4 I 0 3 I Dz I 0 1 I Do
Instruction register H L IL I L IL IH I L IL IL
Cursor address register (upper byte) L Cursor address (upper)

By this instruction, the value of the cursor


address is written in the cursor address register.
The cursor is displayed at the position specified
by the cursor address register.

174
- - - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6255GS-

2. LCD Display

000 001
00.000_01
I
01:1_000.0 I
~ gg:~~~:gl 1
> 00.000.01
DI:1. a 00. a./" cpu I
'-P--- -r-
::~ :::~ :I.c- Cpd
----f-- ---
~r-----l--
l - - - - ---1----
1

> 8: I I
2 I
I 1

I I
'----- - -t--- ----~-----
I 1

I I
I I
I
--- ------- ---I--
I
OJ I I
>!---- - I - - - - - - - - r - - -
I 1

1 I
I I
1 I

Table 2 Legend

Symbol Name Meaning Value


Pitch of characters in horizontal
Hp Horizontal pitch 4 -8 dots
direction
Pitch of characters in vertical
Vp Vertical pitch 1 -16 dots
direction
Number of characters per line or
HN Number of characters in one line 2 - 128 characters
number of words per line

VQ Number of rows Display duty 2-256


A position where the cursor starts
Cpu Cursor start position Line 1 -16
display
A position where the cursor stops
Cpd Cursor end position Line 1 -16
display

175
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -

3. Built-In Bus Averter 6. Power Down Function


The bus averter which switches the address buses Power down function of the MSM5279GS (seg-
Ao - A 1S of the CPU with the memory address ment driver) can be used by connecting the
buses of the refresh. The refresh memory addresses output terminal of CE to the ECLK input of the
are output to MAo - MAls when the input terminal MSM5279GS. This function is valid only in 4-bit
of OlEN is set at high level and Ao -A1s are output parallel output mode.
to MAo - MA 1S when the input terminal of OlEN
is set at low level.
7. Refresh Memory Address

11 4. External Clock Operation


An external clock enables the MSM6255GS to
operate when the input terminal of OIV is set at
(MAo - MAls:) Operation
In the horizontal direction, MAxx is counted up
at the trailing edge of CH. Upper side is addressed
high level. The external clock is input to XT.
while CH is set at low level and lower side is
addressed while CH is set at high level.
MAxx is counted up even if it exceeds the number
of horizontal display characters, but this does not
5. Address Output Floating affect the display since no data is being transferred
MAO - MAls and RAo - RA3 become high at the time.
impedance when the input terminal of AOF is The period in which the data transfer is suspended
set at low level. This function is used when the corresponds to eight characters. When the period
address buses of memory are opened to others passes, one horizontal cycle is completed and the
than MAo -MAls. next cycle is commenced.
MAo - MAlS and RAo. - RA3 become normal Memory address operation in the graphic mode is
impedance when the input terminal of AOF is shown in Fig. 2 and that in the character mode is
set at high level. shown in Fig. 3.

Address configuration of display RAM

HSB LSB

Flg.2 Memory <Jddress In the graphiC mode 1640 x 2001


uspenSlon 0

/1 word
v------.
0000 I 0001 I I 004E
~
I 004F I
0050 I 0051 I I 009E I 009F I

UPJJe r

+
lEFO 11EFI I 11F3E I lF3F I
1 F40 11 F41 I J lF8E I lF8F I
lF90 11F91 I 11FDE I lFDF I

Lowt~1

3E30 13E31 I

Note: L is output for RAo '" RA3.


13E73 13E7F ! 1
176
- - - - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6255GS.

HN (Number of characters in horizontal display line)


Suspension of
Test /1 character data transfer
address
~ \I-~
~~~ --
0000 0001 004E 004F

{
0000 0001 004E 004F
010
011
Line 1
100
101
110
111
000
0000
0050
0001
0051
-- 004E
009E
004F
009F

111 0050 0051


-- 009E 009F Uppe

! l
0370 0371
-- 03BE 03BF

u,,,, fOO

r111

000
0370
03CO
0371
03Cl
--
-- 03BE
040E
03BF
040F

Line 13 ~

l111 03CO 03Cl 040E 040F

Low

000 0730 0731 077E 077F

line 24

t, 0730 0731 077E 077F

Note: Start address is 0000, 80 characters x 24 lines and Vp : 8.

Fig.3 Memory address in the character mode (80 characters x 24 linesl

177
DOT MATRIX LCD CONTROLLER MSM6255GS ...- - - - - - - - - -

8. Output Mode
Three kinds of modes, 1 bit serial, 2bit parallel
and 4 bit parallel, are available as output modes.
Data flow of each mode is shown below.

Data shift
Segment UDo
driver

Upper
LCD panel

Lower

Segment
driver
Data shift

Fig.4 1 bit seriel data transfer

Upper

------------------~~~~
Lower

i I
r- - oJ. .....

I ~4-------

Figure 5 2bit parallel data transfer

178
----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.

CEcp

Upper
LCD panel

Lower

Fig.6 4 bit parallel data transfer

Time charts corresponding to data transfers shown


in Fig. 4 - Fig. 6 are shown in Fig. 7 - Fig. 9.

179
!!
...
co
o
C
o~
s:

~
fs J1J1I1JUUl..flI-_ ::0
X
CHr/>~ _ _ _ r-
(')
C
M~~A1S ENON EN~I ~=~~~~_~_A_N~_S_~_M~ILs_T_A_~_I~I_s~T_A_M_+l~I_ _~_ _~_ _~_ _~_ _~ (')
Suspension of data o
transfer z
~
::0
CLP ------ -- or-
-------- r-
m
UOo I I I I I I I 10710610514131211100 1071615141312111 061 07\6151413121110J II ::0

L EN ON data I STAN data STAN+l data


s:
en
s:
en
UOI CIrri 1110-,161514131211100 10?/6151413121110Joh15141312111 0d II N

t- ENOM data I STAM data


I STAM+l data
I
U1
U1
C)
en

Note: STAN: First memory address of one horizontalline.in the upper side
STAM: First memory address of one horizontal line in the lower side
EN DN: Last memory address of one horizontal line in the upper side
ENDM: Last memory address of one horizontal line in the lower side

Fig. 7 1 bit serial data transfer


f s J 1 J l J l . . f U U U U U 1 -_
~
-==-=-==
---1
=--=-= =- ==-= ====-=- == =-
r---
==-=-=--_-_-=
CHrp - - - - - -

MAo-MA 15 ENDN I EN OM I -_I....._ST_A_N---'-_S_TA_M----LoI_s_TA_N_+l--1l_s_T_AM_+_qL--_--'-_ _ ---L-_-----'-


...L...-_----I._ _

I Suspension of data
/--!!Jlnsfer
-J
CLP

UDo I 1 10 7 lOs 10.1 1 D. 10 7 lOs 10 3 1 D. 1 0 7 1 Os 10 .1 ID. I 1 1- 1 1 I


UD. c
Do
o
ENDN data -i
s:
~
-i
LID. _ I 10 7 I Os I OJ I D. I 07 I Os 10 3 I D. I 0 7 lOs 10 I D. I
.1 :c
X
UD3 Do r
(")
C
ENDM data (")
o
2:
-i
:c
Note: STAN: First memory address of one horizontal line in the upper side o
r
STAM: First memory address of one horizontal line in the lower side r
ENDN: Last memory address of one horizontal line in the upper side m
ENDM: Last memory address of one horizontal line in the lower side :c
s:
(I)
Fig. 8 2-bit parallel data transfer s:
Q)
N
U1
U1
... C)
(I)
~

r!
0;
N

o
o
-f
fs ---- --- 3:
_--J
r - .. ' L_________ J L ~
CHq,

MAo-MAts ENON ENOM I ENON+l I ENOM+l r _ -=- -= ====- =--


Suspension of data transfer
STAN STAM I STAN+l ISTAM+l I
::0
X
r-
n
o
n
o
CLP z
-f
::0
UOJ 07 03 07 03 07 03 07 D) I o
r-
I r-
U02 o;-CO;---C-[)b- 02 06 02 06 02 [ m
::0


UO. Os D) Os 01 Os D) Os D) 3:
en
3:
UOo 04 DO 04 DO 04 DO 04 DO en
N
UI
.- ENOM-l data EN ON data STAN data STAN+l data
UI
C)
en
LO] I 07 I 03 I 07 I O.l I 07 03 I 07 I 03 I
L02 06 02 06 02 06 O2 06 O2

LO) 05 --r -0 1 - --, Os 01 Os D) Os D)

LO o I 04 DO I 04 Do 04 Do 04 I Do

,. ENOM-l data
I ENOM data STAM data STAM+l
1 data

Fig.9 4 bit parallel data transfer


-----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.

9. LCD Driver 10. Relation Between Duty and


Number of Lines
The most suitable LCD drivers for 4-bit parallel
data transfer are MSM5278GS (common driver) and Number of lines is determined by V p , vertical
MSM5279GS (segment driver). MSM5260GS is the character pitch, and VQ' number of lines in vertical
most suitable common/segment LCD driver in the direction.
case of l-bit serial data transfer and 2-bit parallel Number of lines = VQlV p X 2
data transfer.
Note: 4-bit parallel data transfer cannot be applied Note: In the graphic mode, number of lines should
to MSM5260GS. Both l-bit serial data trans not be odd number.
fer and 2-bit parallel data transfer cannot be
applied to MSM5279GS.

11. Calculation of Crystal Oscillation


Frequency (fosd

Tablll 3 Calculation formula of fosc

DIV Output mode Calculation formula of fosc Calculation example (MHz)

l
CD FRP X (HN + 8) X Hp X VQ X 2 9.856
@ FRP X (HN + 8) X VQ X 4 2.464

H
CD FRP X (HN + 8) X Vp X VQ 4.&28

@ FRP X (HN + 8) X VQ X 2 1.232

Note: (1) Table 3 shows a calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and VQ = 100, how
ever, the example of Hp = 4 - 7 in 4-bit parallel is not included.
(2) Output mode CD Hp = 4 """ 7 in l-bit serial, 2-bit parallel and 4-bit parallel
Output mode @ : Hp = 8 in 4-bit parallel

12. Calculation of Character Clock


(CHI/ Frequency

CHI/> = FRP X (HN + 8) X VQ

Example: Assuming FRP = 70 Hz, HN = 80 and VQ = 100,


CHI/> = 1.62 (J.1s)

13. Calculation Shift Clock (CLP)


Frequency
Table 4 Calculation formula of Clf"

Output mode Calculation formula of CLP Calculation example (MHz)


1 bit serial FRP X (HN + 8) X Hp X VQ 4.928
2-bit parallel FRP X (HN + 8) X Hp X Vf} X 1/2 2.464
4-bit parallel FRP X (HN + 8) X Hp X VQ X 1/4 1.232

Noto: Table 4 shows an calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and VQ = 100.

183
DOT MATRIX LCD CONTROLLER MSM6255GS . - - - - - - - - - -

14. Relation Between Reference Clock (fs)


and External Clock

oiV

XT

(oW = 1)

fs functions as a dot clock in LCOC and the dot counter inside the IC is counted up at the tailing edge of f s .
The dot counter operates in N number system and its signals are output as CH</>.
(Refer to time charts Fig. 7-9 and Fig. 14.1

15. Access to the Display RAM BUSY is high), the display on the screen does
not flicker.
In writing/reading the data to/from the CPU, 01 EN
should be low level. By setting 01 EN signal at low Note: This method is effective when the size of
level, the address from the CPU are output from screen is small. In the case of big size
MAo-MAts, and this enables the access to the screen, 640 x 200 dot, 1-character needs
display RAM. approx. 1.6ps. So, in this case, the period
There are 3 method about accessing display RAM when BUSY is at high level is 11.2ps,
from the CPU. which is impossible to write a lot of data.

(1) Direct access from CPU (3) Synchronized access


Display RAM is accessed directly from the Refresh scycle and CPU scycle are alternately
CPU, irrespective of MSM6255GS condition performed. So, there is no flickering on the
(refresh cycle or notl. screen and there is no need to scence the BUSY
In this method, the RAM address changes to signal.
the CPU address when the display is on the In this method, however, some external circuits
screen. So, frequent address to the RAM causes are necessary. The timing chart of this method
flickering on the screen. is described in the Figure 10 below.

(2) Access during BUSY signal is at high level


BUSY signal indicates the period when the data
transfer is stopped and BUSY signal is set at
high level during the data transfer is stopped.
The period when BUSY signal is high corre-
sponds to that of seven characters'. If display
RAM is accessed during this period (when

184
- - - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6255GS.

DIEN

display
RAM
OUT

Figure 10 Basic timing of synchronized access to the display RAM.

legend
TC Period wihen the address bus is MAo-MAts output address to the upper side
occupied by CPU when DIEN is high and CHI/> is low_
Period when the LCDC fetches To perform synchronized access method, the
the refreshed data timing between DIEN and CHI/> should be as
tRAM Refresh address delay time + described in Figure 10.
memory access time
tUDS Upper side data set-up time
tUDH Upper side data hold time

M-WR
M-RD

V-RAM
SELECT--------~

DIEN

READY
DATA LATCH

Figure 11 Wait function controlling circuit

Display RAM must meet following require- should be synchronized so that the write pulse
ment. should occur during the period of TC. In read-
ing the pattern data from the CPU, the data of
TL>tRAM + tUDS
display RAM should be talched first.
In writing data into the display RAM, LCDC Figure 11 shows the controlling circuit.

185
DOT MATRIX LCD CONTROLLER" MSM6255GS ...- - - - - - - - - -

16. DIEN
DIEN has to be generated when the display RAM is
accessed by Synchronized access method described
in 15-(3).

(1) Control the LCD module by separating


upper side and lower side
Timing chart of XT and CHI/> is described as
below. In this case, 4-bit data transfer is applied
and Hp=B.

XT

DIEN 'signal is generated by XT and CHI/> .


DIEN signal generating circuit is described in
the figure bellow.

[)o-- DIEN
CHI/>

=Er D Q

When Hp~B in the 1-bit serial, 2-bit parallel and


4-bit parallel mode, the relation between XT
and CHI/> should be refered to Figures 7 and B.

17. ScrollPaging
Scroll"paging is enabled by setting the display start
address to the scroll address register.

(1) Memory address of vertical scroll paging


Figure 2 shows the memory address when the
start address is 0000. When the start address is
set at 0050, display will be vertically shifted by
+1.
By setting the starting address one by one,
screen will scroll vertically.
Paging will be performed by setting the start
address as 3EBO.

(2) Memory address of horizontal sera"


When the starting address is set at 0001 in
Figure 2, the display on the screen will be
shifted by +1 byte horizontally. The data
shown as 004F in Figure 2 corresponds to the
memory data in the 2nd line shown as 0050.

186
----------__ DOT MATRIX LCD CONTROLLER MSM6255GS-

INTERFACE WITH CPU

MSM6255GS
I""r- ",....
8085 -
~ - ~
WR
- '-- -
WR ~r- ~ RD

AD

101M
~r- r- r- - Decoder - C
A -A., CS

ADo-AD7 U
bel
I--

ALE
HLDA

As-A 1S
LJ1 '--
-,
DBo-DB7

Ao-A 1S

"'~

MSM6255GS

280
'" f"

~ l- """\.. WR
-
~I-- I- '- RD
WR
RD

--
~f- f - I- r---c f-c
-
CS
IORQ A -A., Decoder

,
I-
0 0 -0 7 DB o -o8 7
I--

'--
Ao-A1S Ao-A 1S

jjj If-.

187
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - - - - - -

MSM6255GS

8086

11

*Minimum mode

MSM6255GS

6800

VMA

R/Iii ~~~ ______L-)O~-----a WR

t----(1 CS

188
I I
r
I II I I I I
cs FD DR L MSM
L
~
1'-
~
i'-.J
B l~
=> DBo-DB7
.UDo
S
,
4 bit
5279GS l-
I--
f::
I--
~

n6~40H245
DIEN
UD3

CLP
.----
\ \
CEq)
I
V
~
V
RDO-RD7 LIP
Jr>
'---
WR
lID

Display
FRP
FRMB
MSM
5278GS
rLb
~
1----- - - - - - - - - - - -

RAM
MSM6255GS

l
It MAo
MA 1S
~ f--

~
~
0 r--
P
~
r--

I I r Ir~

or J
Decoder
I I 1
Ao-A 1S LDo....,.LD J
1 I
Ao-AIS 0
Figure 12 System configuration in graphic mode

...co
co

~
r!
-
U)
o

o
--- o
-f
3:

ill :r>
-f

~~;7~S~ "~
:0
CS RD WR X
UDo I
C")
S 4 bit
o

.. I
ROO
S
UD J

CLP
r---
II IJ C")
o
2:
-f
RD7 CE.p r----\ :0
CPU
Character
RAo
~ o
,,
generator I
S LIP
I
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Figure 13 System configuration in character mode


Ts
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Memory N I Start address

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I
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BUSY -----------~-- ______________ ~-----+--~~~~----------------~------------------------
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Figure 14 Time chart during suspension of shift clock -.of
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OKI semiconductor
MSM6265GS
DOT MATRIX LCD CONTROLLER

GENERAL DESCRIPTION

The OKI MSM6265GS is CMOS Si-gate LSI to control large size dot matrix LCD in characters and graphics.

FEATURES

Software compatibility with HD6845 and HD46505 Attributes: Cursor ON/OFF/BLINK


CRT controllers. Scrolling, paging
Display control capacity Data output: 4-bit parallel output, ODD/EVEN out-
14
Number of characters: 16,384 (2 ) characters put
Display addresses Display system: AC inversion at each frame
MAo to MA13 Crystal oscillator, external clock input
Raster addresses Low power CMOS silicon gate process
RAo to RA4 Single +5V power supply
Duty: 1/100 X 2 aD-pin flat package
Number of characters per row: 2 to 128 (program-
mable)
o Font configuration: Vp: programmable
Hp = 8 (4bit parallel output),
Hp = 4 to 8 (ODD/EVEN
output)

PIN CONFIGURATION

LOl
LJ HP1
LO .
HP,


UOo HPo
UO,
4BIOOEV
U'o2
NC
NC
6400
UO.I
MAl/>
VOO
Is
CHI/> OINH
BUSY OIV
EXBL TEST l
AOF TEST,
RS MONO
cs
AD
WR 0 VSS

Xl
XT

co co
o 0
co
o z
U co
0
0 U 0 (S 0 0
a: z a: a: a: a:
aa: 0
a:
0' : <i
a: a: a:

196
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

BLOCK DIAGRAM

XT XT OIV F1ES
CH
j
I

MONO

'3 OOO/(V~N FRP


~r~f'~i~ _ _
CE~
~ 4blt parallel ROo to RDi
_ output
E- -8-~t----
~ ---CLP
a parallel
_ _ _ FRMB

UO" to UD, OINM


MAo to MAl.'
LOu 10 LO,t
L--------4WOOEV

Figure 1 Block diagram

197
f!
...co en
m -<
en C
~ 0
m ~
CRT/LCD switching signal
s: s:
OJ l>
..... r ~
-I
CRT controller
r- - 0
(')
JJ
X
~
r---I
6845
CRT screen "
C r
(')
C
l>

11
Ci) (')
Address
bus 1 1 JJ
l>
0
2:
M
s: ~
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'--
,.... t---
P V-RAM II- JJ
~ X I'" 0
....,
~ r

CPU

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M
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M
code
Data
r
m
JJ

s:en
)
- t--"1
L---

~
r-
-"-(
H
P
X
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h
r---I
CG
ROM [ Driver circuit
J s:en
Data
bus
0
g
0
JJ
t
0
s:
f0
;;: JJ
j l - -
-
J I\)
en
(J1
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en
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JJ
l>
l> ~
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)
Character data

J1
JJ
0
LCD driver
~~
V
-
2 .)
LCD controller
-
t--
f----
r----;

LCD
driver
W LCD panel
640 x 200

II ~

Figure 2 System block diagram


- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit


Power supply voltage VDD Ta = 25C -0.3 - 6.0 V
Input voltage VIN Ta = 25C -0.5 - VDD + 0.5 V
Storage temperature T stg - -55 - 150 c

OPERATING RANGES

Parameter Symbol Condition Rating Unit


Power supply voltage VDD - 4.5 - 5.5 V
Operating temperature Top - -20 - 85 c

INPUT CHARACTERISTICS
(VDD= 5V 10%, Ta = -20 - 85C)

Parameter Symbol MIN TYP MAX Unit Applicable terminal


"H" input voltage VIH 2.2 - VDD V DBo - DB 7 , RD, WR, DINH, RDo - RD 7 ,
ADF, CS, WIDE, RS, RES, EXBL.
"L" input voltage VIL -0.3 - 0.8 V
MONO, 4B/ODEV.
"H" input volage VIH 3.6 - VDD V
XT,TEST1,TEST2,DIV
"L" input voltage VIL -0.3 - 1.0 V
"H" input voltage VIH 204 - VDD V HP o - HP 2
"L" input voltage VIL -0.3 - 0.6 V 640D
"H" input current IIH - - -1 IJ.A RS, CS, WR, RD, ADF, RES, DIV,
MONO, 640D, HP o - HP 2 , DINH,
"L" input current IlL - - 1 =A
DBo to DB 7 , RDo to RD7
"H" input current IIH - - -1 IJ.A
TEST1, TEST2,
"L" input current IlL - - 100 IJ.A
Input capacitance CI - - 5 pF All input terminals

OUTPUT CHARACTERISTICS
(VDD = 5V 10%, Ta = -20 - 85C)

Parameter Symbol MIN TYP MAX Unit Applicable terminal


"H" output current IOH VOH = 2.8V -500 f..LA MAo - MAl3,
- -
VOH = 4.2V -100 f..LA DBo - DB 7 ,
UDo - UD3,
"L" output current IOL VOL = OAV 2.1 - - rnA
LDo - LD3,
CLP, FRP, FRMB
LIP, BUSY,
CHq> MAcIJ, fs

199
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

POWER CONSUMPTION
ITa = 25C)

Parameter Symbol VDD Condition MIN TYP MAX Unit


Static current IDDS 5v fosc = 0 Hz, No load - - 50 J1A
Dynamic current IDD 5v fosc = 10 MHz, No load - - 15 mA

Note: TEST1 and TEST2 are open, and other inputs are either VDD or GND level.

SWITCHING CHARACTERISTICS
(VDD = 5V 10%, Ta = -20 to 85C)

80% r ~

20"10 ~
I 1\
-t-

~ f-- tr
- f--tf

Parameters Symbol Load condition MIN TYP MAX Unit Applicable


terminal
tr 60pF - - 40 ns All output
Rising and falling times
tf 60pF - - 40 ns terminal

MAXIMUM OPERATING FREQUENCY


(VDD = 5V 10%, Ta = -20 - 85C)

Parameter Symbol Conditions MIN TYP MAX Unit


Oscillating frequency fosc DIV = "L" 11 - - MHz Crystal oscillator
Basic clock frequency fs DIV = "H" 5.5 - - MHz External clock

200
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

PIN DESCRIPTION
Pin No, Pin name I/O/Z Function
1 WIDE I Expansion mode when "H", Normal when "L",
2 MAl3
Address output to display RAM,
I I O/Z
High impedance when ADF = "L",
17 MAo
18 FRP 0 Frame signal
19 LIP 0 Display data latch signal
20 CE 0 Segment Drv chip enable clock
21 CLP 0 Display data shift clock
22 FRMB 0 Alternate signal
23 LDo
I I 0 Display data parallel outputs (lower side)
26 LD3
27 UDo
I { 0 Display data parallel outputs (upper side)
30 UD3
32 VDD +5V
33 CH 0 Character clock
34 BUSY 0 Ready status signal. "H" during serial transfer halt period,
35 EXBL I Cursor control signal input
36 ADF I Address floating input, Floating when "L",
37 RS I Register select input
38 CS I Chip select, , , selection status when CS =" L"
39 RD I Read, , , data reading possible while RD = "L"
40 WR I Write, , , data writing executed by WR leading edge,
41 RES I Reset signal input, Reset when "L",
42 DBo 8-bit data bus, , , three-state input/output common pins
I I I/O/Z Pull-up registor on-chip
50 DB7 Positive logic
51 RDo
I I I ROM data inputs, , , Dot pattern data of CGROM,
59 RD7
60 RAo
I I O/Z Raster address outputs, High impedance when ADF = "L",
64 RA4
65 XT I Crystal oscillator pins
66 xl' 0 External clock is input to XT, (XT is open,)
67 GND OV
Change R9, R 10, and R 11 contents when "H ",
68 MONO I
Normal when "L", Direct VDD and GND connections possible
69 TEST I Test input pins
I
70 TEST2 Left open for use,
External clock when "H", Self-oscillation when "L",
71 DIV I
Direct VDD and GND connections possible,
72 DINH I display OFF signal input. Display OFF when "L",
73 fs 0 Dot clock
74 MA 0 Memory address counter clock output
40-character memory address output and 80-character data read-
75 640D I ing when "H"
Normal when "L"
4-bit parallel output when "H", ODD/EVEN output when "L",
77 4B/ODEV I
Direct VDD and GND connections possible,
78 HPo 1 font horizontal pitch program input,
I 1 I Direct VDD and GND connections possible,
80 HP2

201
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

TIMING CHARACTERISTICS OF LCDC CONTROL SIGNAL

tCH tCH

MA~ _______________ ~--+--J

Lower side Upper side


MAO to MAI3 Upper side
address address address
RAo to RA4

tMAH
tMAH
tMAL

I~
-'r

MAO to MAl3 ~ Floating r


RAo to RA4
Display 7 Display
address 7~ ~i<:.. address

1- ItREA
tWRA

tRES l
_}.....------.I\'---------

202
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

LCDC Control Signals


(CL = 30pF, VDD = 5V 10%, Ta = -20 to 85C)
Parameter Symbol MIN TYP MAX Unit
Clock cycle time tcp 180 - - ns
Clcck "H" level pulse width PWH 80 - - ns
Clock "L" level pulse width PWL 80 - - ns
Clock rising and falling edge time t cr , tcf - - 20 ns
Dot clock delay time tfs - - 110 ns
Character clock delay time tCH - - 100 ns
Memory address clock delay time tMA~ - - 340 ns
Memory address hold time tMAH 5 - - ns
Upper side address delay time tMAU - - 290 ns
Lower side address delay time tMAL - - 120 ns
Drawing address delay time tWRA - - 40 ns
Display address delay time tREA - - 40 ns
Reset "H" level pulse width tRES 1 - - fJs

203
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

BUS TIMING CHARACTERISTICS

tAH
I---

~K
111
RS,CS
l-: ,I-

tRCS

tcw

\ -V
tDS tDH

I.
DBo ..:. DB7
(WRITE) Ix~ VALID
,:K
DBO - DB7
./
(READ) ~~
VALID

l-
"
,/

t ACC
tOH

Bus Timing Characteristics


(CL = 50pF, VDD =5V 10%, Ta = -20 to 85C)

Parameter Symbol MIN TYP MAX Unit


Rs, CS set-up time tRCS 300 - - ns
RD, WR pulse width tcw 300 - - ns
Address hold time tAH 40 - - ns
Data set-up time tDS 200 - - ns
Data hold time tDH 40 - - ns
Output disable time tOM 0 - 40 ns
Access time tACC - - 200 ns

204
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

LCD DRIVER INTERFACE TIMING CHARACTERISTICS

CLP

UDo - UD3
LDo - LD3 _ _ _--1---'

LIP

BUSY

LIP

FRP

tFRP

FRMB

FR t'=-R

205
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

LCD Driver Interface Timing Characteristics


(CL = 30pF, VDD = 5V 10%, Ta = -20 - 85C)

Parameter Symbol MIN TYP MAX Unit


Data delay time tDA - - 100 ns
Cycle time for 1 character tCH 730 - - ns
Latch signal delay tim'e tQ - - 200 ns
Latch signal "H" time tLiP 1.46 - - J1s

11 Chip enable clock delay time


Chip enable clock "H" time
Ready signal delay time
tCE
tCE
ts
730
-

-
-
-
-
200
-
200
ns
ns
ns
Ready signal "H" time tSUSY 5.11 - - J1s
Frame signal delay time tFRP 2tCH - 2tCH+ 200 ns
AC signal delay time tFR - - 200 ns

PATTERN DATA FETCHING TIMING

CH~

MAo to MAIJ
RAo to RA4 _ _ _oJ

ROo to RD7

tUDS
tUDH

Parameter Symbol MIN TYP MAX Unit


Upper side data set-up time tUDS 140 - - ns
Upper side data hold time tUDH 40 - - ns
Lower side data set-up time tLDS 140 - - ns
Lower side data hold time tLDH 40 - - ns

206
- - - - - - - - - : - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

FUNCTIONAL DESCRIPTION
1. LCDC Internal Registers Cursor display mode B

The internal registers include one address register


(AR l. and eight data registers R 1 and R9 '" R 15. 06 Os EXBL= "L"
(See Table 1).
L L
1) Address register (AR) L H
No cursor display
When a data register is accessed, this register H L
specifies the number of that register. Once this
register has been written, the same value. is held H H
until the power is switched off without being
influenced by RES. Note 1 & 2:
Blinkingcycles:
I On I Off
2) Horizontal display character number setting ~
register (R 1 ) 32 or 64 frame interval
Setting of the number of characters per line on Note 3:
the screen. Any value from 2 to 128 can be set. I f the blinking cvcle is applied to EXBL from an.
Example: 80-character setting (50H) external source with 0 6 = 0 and 0 s = 0, the cursor
isblinked on and off by the EXBLfrequency.

5) Cursor end raster address (R11)


3) Maximum raster address register (R9) This is another cursor control register. This
Setting of the value obtained by subtracting register specifies the raster address of the bottom
from the raster counter corresponding to one edge of the cursor. The relation to Rl0 is out-
line. The vertical pitch Vp for 1 font can be lined below.
set to any value from 1 to 32.
Example: Vp = 8 setting HP = 7, Vp = 11, cursor start address
~ cursor end address
~ maximum raster address

o
1
4) Cu rsor start raster regi ster (R 10)
2
This is one of the cursor control registers. The 3 --~-+--~4--+--~4--
raster address of the top edge of the cursor is 4 --~-+--r-;--+--~;--
specified in the five lower order bits, and the
5 ---r-;--+--r--~4--+--
cursor display mode is specified in the two
higher order bits. The cursor display mode is 6 ---r--r-~~--+--+--+--

set to either mode A or mode B by the EXBL 7


input pin. 8
9
Cursor display mode A
10---r-;--+--r--r-4--+---

0 6 Os EXBL = "H" Cursor start address = 9


Cursor end address = 9
L L Cursor displayed in stationary position
L H No cursor display

Note 1 H L Cursor blinked on and off every 32 frames


Note 2 H H Cursor blinked on and off every 64 frames

207
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

o o-+--+---I-+--t--t-+--
1
2 2~Hi--ttlf-t-tt-tti--ffHft-ffi-

3 3-ffi-H~ft-~~~Hi-~~

4 4-~~~~tiT~~~~-

5 5--ffi-ti~~~~ft-~~~-

6 6--~~-+--+~r-+--t---

7 7--~---i--+--+--+--+--~-

8 8--+~-+--+~r-+--+---

9 9-+--+-t-~~-+--+-

10--~~~~~~~~~ L

Cursor start address = 9 Cursor start address = 1


Cu rsor start address = 10 Cursor end address = 5

HP = 7, V p = 11, cursor start address> cursor end address

o
1
2
3
4
5
6
7
8
9
~ .... ....
10 I' t' t' I' I' +' " --- Displayed up to the maximum raster address.

Cursor start address = 9


Cursor end address = 8

Maximum raster address < cursor start address;:i cursor end address.
Cursor display is switched off.
Note: When the cursor overlaps pattern data, the result of an EX-OR operation between the cursor signal and the
pattern data is displayed.

6) Start address registers (R12 & R13) 7) Cursor registers (R14 & R15)
Register for setting the memory address The cursor display address is specified by two
corresponding to the first character in the first bytes. The LCDC controls the cursor when the
line on the screen. The LCDC commences data memory address MAxx reaches this address
display from this address. Both reading and while within the R10/Rl1 range.
writing are possible, and when reading, the two Both reading and writing are possible, and when
higher order bits become "00". reading, the two higher order bits become "00".

208
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

Table 1 MSM6265GS internal registers

Address register Data bit


CS RS Register Register name READ WRITE
3 2 1 0 7 6 5 4 3 2 1 0
H X X X X X Invalid - -
L L X X X X AR Address register X 0 X X X X

Horizontal display
L H L L L H Rl X 0 X
character count
Maximum raster
L H H L L H R9 X 0 X X X
address
L H H L H L RIO Cursor start raster X 0 X B P
L H H L H H Ru Cursor end raster X 0 X X X
L H H H L L R12 Start address (H) 0 0 X X
L H H H L H Rl3 Start address (L) 0 0

L H H H. H L Rl4 Cursor (H) 0 0 X X


L H H H H H RIS Cursor (L) 0 0

Note 1: B denotes cursor blinking, and P denotes the blinking cycle period.
Note 2: "00" is read if registers marked X are read.

2. R9, R10, & R 11 Register Re-Reading


Function
Th.e maximum raster register (R9), cursor start Note: Since MSM6265 has been fixed at 1/100 duty
raster (R1O), and cursor and raster (Rll) are X 2, the 25-line structure will no longer be
re-read in the following way when the MONO possible if Vp exceeds 8. If this function is
input pin is switched to "H". Normal operation used, 25-line displays can be achieved even
when "L". if Vp > 8 is set by the CRTC application
software.
Maximum raster address (R9)
07 06 Os D4 03 O2 0 1 Do
Ix X X

[22LI
Set V p -l
R9 setting R9 re-reading
0"'7 o to 7 (according to setting)
8 '''IF(H) Fixed at 7

Cursor start raster (Rl0)


07 Os DO
IX B P

R 1 0 setting R lOre-reading
0"'6 o to 6 (according to setting)
7 '''IF(H) Fixed at 6

Cursor end raster (R 11)


Rl1 setting R 11 re-reading
0"'7 o to 7 (according to setting)
8"'1 F Fixed at 7

209
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

3. 40-Character Mode 6. Address Output Floating


If the 640D input pin is set to "H", memory MAO '" MA13 and RAo '" RA4 are switched to
addresses for 40 characters per horizontal line are high impedance when the ADF input pin is set
output to MAo'" MA13 regardless of the R1 con- to "L". This function can be used when the memory
tents. Pattern data equivalent to SO characters per bus is opened to other than LCDC (for example to
horizontal line is fetched. drawing cycle from refresh cycle).
Normal when "L". See time chart in Figures 9
and 11.
7. Power Down Function

11 4. Display Off Function


Whenthe DINH input pin is set to "L", 0 is output
by UDo '" UD3 and LDo '" LD3, resulting in the
The LCDC generates the CEifJ output
select of the segment driver. This
connected to the ECLK input of
signal for chip
CEifJ signal is
MSM5279GS.
display being switched off. This function is useful Note that this function can only be used when in
in cases where the power supply is switched on, 4-bit parallel output mode. See the time chart in
and where the display is to be left off for relatively Figure 13.
long periods of time. Leave set to "H" when the
function is not to be used.
8. Expansion Mode
5. External Clock Operation The shift clock count is doubled when "H" is
Operation by external clock is enabled when the applied to the WIDE input pin. Normal mode, when
DIV input pin is set to "H". The external clock is "L" is applied. In this mode, the clock frequency
applied to XT input. has to be changed.
The crystal oscillator is used when the pin is left Example: When 40-characters per line has been set
at "L". The number of display dots in the
horizontal direction is changed to
640.
The difference between SO-characters per line in
normal mode and 40-characters per line in expansion
mode is outlined in the following diagram.

.... .... .... h. h.

'17

"A" displayed in normal mode "A" displayed in expansion mode

The data transfer time charts are shown in Figures 3 and 4.

210
Is

CH. ~L-_ _ _.--J

MAo to MAI3 STAN STAM ~ --~- r- STAM+l STAN+2 STAM+2


o
o
CLP -t
s:
UOo fD;fD;1 0;- I~ 10 3 r0
2 l O-;-I~r 07 1Ob lOs 10 10 4 3 J

-I
jJ

UO, 10 lOb lOs 10:; 115 10 10,-1 00 I 0, 10 lOS 10 103 I


7 3 2 6 4 X
r-
STAN data STAN+l data (")
o
(")

U02 10 7 106 lOs 10 4 1031 02 10, 100 10 7 lOb 10~041~31 ~


-I
jJ
UOJ fD-;j~ro;l~TD.I -[D21D;l~ 10 IDs 1 LO,l
6 0 4
or-
STAM data STAM+l data r-
m
Figure 3 ODD/EVEN data transfer in the expansion mode jJ

s:en
s:en
N
en
UI
C)
~
en

~
f!
~
N

o
o
-I
fs ~

-I
CH ----,.......
_-----' :II
X
MAO to MA13 r STAN -I STAM - 1- STAN+l - - 1- STAM+l STAN+2 STAM+2 [ .-n
o
n
o
z
CLP -I
:II
U03 0, Os I 03 D) 07 I Os 03 I D)
o.-
.-
m
UOl I 0, OS, 03 ,D) 07 - , - 05 --I -D31 D) :II

~
UO, I 06 I 04 , 01 'DO , 06 ,- 04 O2 ' DO rn
~
en
UOo 1 06 1 04 1 02 1 Do 1 06 - 1- 0 4 -, - O2 1 Do N
en
STAN+l data
U1
STAN data C)
rn

L03 0, O s , - 03 I D) 0, I Os I 03 I D)

L02 0, Os, 03 -, D) r 0, - , - 0-;- I -=-[)3-1 D)

LO) '06 04 I 02 I Do , 06 I 04 I 02 I Do

LOo I 06 - ,- 54 -, -02 - -, Do r 0 6 - , - 0 4 I D2- 1 Do


STAM data I- STAM+l data

Figure 4 4-bit parallel data transfer in the expansion mode


- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

9. Refresh Memory Address


(MAo -- MAl3 ) Operation
1) MAo -- MAl3 Operation
In the horizontal direction, the MAxx output which data transfer is stopped corresponds to
is synchronized with the CHI/> trailing edge. eight characters, and when that interval is
And although MAxx is counted up even if the exceeded, a single horizontal cycle is completed
horizontal display charaC't~r count is exceeded, and the next cycle is commenced. Memory
this does not effect the display since no data is address operation is as indicated in Figure 5
being transferred at the time. The interval in below.

Number of characters in horizontal display line

Raster
address !
1 characte; \ ~~~n~~nsfer
-r

I
000 0000 0001 004E 004F
001 0000 0001 004E 004F
010
011
Line 1
100
101
110
111 0000 0001 004E 004F
000 0050 0051 009E 009F

Up per
Coo" ( sid

111 0050 0051 009E 009F

l 1
000 0370 0371 03BE 03BF
001
010
011
Co"," (
100
101
110
111 0370 0371 03BE 03BF
000 03CO 03Cl 040E 040F
001
010
011 1-
Coo," ( 100
101
110
111 03CO 03Cl
-- 040E 040F

l l
000 0730 0731 077E 077F
Lo wer
sid
Coo," (

111
000
0730
0780
0731
0781
-- 077E
07CE
077F
07CF
001
010
011
Co"," ( 100
101
110
111 0780 0781
-- 07CE 07CF
-
Figure 5 Refresh memory address (MAo"'MA131

Note: When start address is DODO, 80 characters x 25 lines, Vp = 8.

213
DOT MATRIX LCD CONTROLLER . MSM6265GS.-----------

2) Upper and Lower Screen Division Simultaneous output of upper and lower
screen halves
Since the screen is divided into upper and lower The upper and lower screen half addresses
halves, MAxx for the upper side and MAxx for are sent upon being switched within a single
the lower side are sent by LCDC. character period. The upper side address is
sent when the CH is "L" while the lower
side address is sent when CH is "H ".

------~---
MAu to MAl J ~1~O_O_OO~I_03_C_O~I_OO_O_l~_03_C_1~I_OO_O_2~I_O_3C_2~1______ _ I 004F I
040F I
I. One horizontal memory address
I

10. Output Mode Setting


Output mode is set by the 48/0DEV input pin.

No. 48/0D-l=V Output mode

Simultaneous output of upper side and lower side data under 2-bit parallel
Mode 1 L
data processing mode.
Simultaneous data output of upper side and lower side data under 4-bit
Mode 2 H
parallel data processing mode.

The time charts for modes 1 and 2 are shown in Figure 10 - Figure 13.

214
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.

, . . . - - - - - - , _ UD 1
Data shift
UDo

Upper side
LCD panel

Lower side

Common Drv

- t - - - UD 2
Data shift UD 3
-

EVEN Segment Drv

Note: MSM5260GS is used for the segment and common drivers. See Figure 8 and Figure 9
for the time chart.
Figure 6 Mode 1 data flow

LCD panel

Common Drv

LDo to LD J

Note: MSM5279GS is used for the segment driver, and MSM5278GS is used for the common driver.
See Figure 10 and Figure 11 for the time chart.

Figure 7 Mode 2 data flow

215
~
~
al

C
o
-i
~

Is

CH
J1JUUU1J1Jl.JlJ
_~r-_-_____
----
=I ---- ----- -i
:c
X
r-
(")
----r----""T----r- - - - - --
MAO to MA IJ ENON ENOM I STAN I STAM I STAN+l I STAM+l 1
C
---- (")
o
,- Oata transfer stopped
2
-i
:c
CLP o
r-
r-
m
UOo 1 0 7 10 5 1 0 31 0 1 10-7-1~loJ 10 1 IV 7 10~ID;TDI I :c
UOI I Ob rO~TD2 1 0 0 ---rD;;ID~1 O 2 1 O;-r 0b 104 1 02 I O~ ~
C/)

ENON data STAN data STAN+l data ~


0)
II.)
0)
U1
U02 I 07 I Os 03 01 I 07- ~I 03 I 01 10 7 r Ds ro;\Dl I G)
C/)

UOJ I b I 0;-02 00 'Ob ,D O2 1 0 0 I0 04 O2 TOo ,



4 -, 6 , ,

ENOM data STAM data 1_ _I


1- ,-
STAM+l data
-I

Note: STAN: Start address of one horizontal line in upper side


ENDN: End address of one horizontal line in upper side
STAM: S~art address of one horizontal line in lower side
ENDM: End address of one horizontal line in lower side

Figure 8 Mode 1 memory address and data transfer


fs

CN

MA _____ --=--= =- --,


MAo to
MAil
ENDN I ENDM I ENDN I ENDM I STAN I STAM I STAN I STAM I STA~STAM+l
CD @ Q) Data transfer stopped cv

C
o
CLP -I
s:
UDo l>
-I
:::JJ
UD.
DO X
Data in <D 1_ Data in @ r-
(")
C
(")
UD2 F;-TosJD3]OI
.
KJ DsFIDl - 10
I
1Dsl~Dl 10,1
7 OS IDJ 10 I
1 o
2
-I
UDJ Do :::JJ
1_ Data in @ _1 Data in @ _ 1 Data on _I Data in@
or-
1- -1- r-
m
:::JJ

s:
en
s:
en
N
en
U1
G)
Figure 9 Mode 1 memeory address and data transfer in the expansion mode
~
en
....

~
DOT MATRIX LCD CONTROLLER MSM6265GS.

~
0 0
0'" 0'" 0- 0 0'" 0 0- 0

0 0
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0 0 .0'" 0'" 0
..

0'"

0
0

0
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0
0

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0
0

0
c

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0-

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Q

01
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~
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0 c. 0 0 c:i 0 0
.. u:

z
o
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-s. o o
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Q.
...J O' 0 0 o o o
u U ~ ~ ~ ~ ...J ...J

218
DOT MATRIX LCD CONTROLLER MSM6265GS.

e o o 0 6 @)
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c5 0 0 u::

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219
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -

11. Relation between Duty and


Number of Lines
Duty is fixed at 1/100 X 2. The screen is divided oiv
into upper and lower halves. The number of lines
is determined according to the following equation.

Number of lines (number of characters in vertical


display) = 200IV p ~---I.Xl--- Is

Note: Vp is the vertical pitch for 1 font


(R9 contents)
Example 1. 25 lines when Vp = 8
Example 2. 20 lines when Vp = 10
Example 3. When Vp = 14 is set, only two rasters
of contents are displayed in the line fosc calculation equation
8 font. fosc = FRP X (HN + 8) X Hp X l/Duty X M
where FRP is the frame frequency,
12. Hp Setting H~ is the horizontal display character count.
HP is the horizontal pitch for 1 font.
The horizontal pitch Hp for 1 font is set by input 8 denotes the data'transfer stopped interval,
pins HP o '" HP 2 . 8 characters per horizontal line, and
M = 2 when Di'V is L
HP2 HPl HPo HP M = 1 when DIV is H

L H H 4 Example of crystal oscillator Frequency Calculation


H L L 5 Calculation of output modes 1 and 2 with horizontal
H L H 6 display character count of 80 characters, HP of 8,
Vp of 8, and l/duty = 100.
H H L 7
Substitute FRP = 70 Hz, HN = 80, Hp = 8,
H H H 8 l/duty = 100, and M = 2 into the equation.
fosc = 9.856 (MHz)

Note: Hp = 8 is fixed in 4-bit parallel output mode.


Hp = 4 to 8 can only be set in ODD/EVEN
14. Character Clock (CHcp) Frequency
output mode. Calculation
L denotes GND, and H denotes VDD. CHcp = FRP X (HN + 8) Xl/Duty
Example: FRP = 70 Hz, HN = 80, and 1 /Duty = 100
CHO = 70 X 88 X 100 = 616 (KHz)
13. Crystal Oscillator Frequency = 1.62 (/lS) (approx.)
Note: The CHcpcycle period is not related to output
Calculation
mode.
External clock or self-oscillation is selected by the
DIV input pin. 15. Shift Clock (CLP) Frequency
Calculation
DIV Oscillation source If the same conditions as in the fosc calculated are
L Crystal oscillator used,
CLP = fs/2 = 2.464 (MHz) (Output mode 1)
H External clock connected to XT input pin.
CLP = fs/4 = 1.232 (MHz) (Output mode 2)

16. LCD Driver Interface


Signals related to the LCD driver include FRP,
FRMB, CLP, CEiJ, and LIP. The time charts for
these signals are shown in Figures 13 and 14.

220
Is - - nnnnnnnnnn - - - _ -
_ _ JUUUUUUUUUL _ _

CHI/>

MAO to MAI3

CLP

LIP

CEI/>
-I~------------------------------
,-------------------- - - - - -
BUSY

C
Figure 12 Mode 2 data transler stop interval 0
~
3:

~
jJ

X
r-
LIP (')

CLP
-----I